Semiconductor Back Grinding

Semiconductor Back-Grinding
The silicon wafer on which the active elements are created is a thin
circular disc, typically 150mm or 200mm in diameter. During diffusion
and similar processes, the wafer may become bowed, but wafers for
assembly are normally stress relieved and can be regarded as flat.
Frequently there will be a departure from roundness, with a flat or notch
indicating crystal orientation.
The grinding process
A typical wafer supplied from the ‘wafer fab’ is 600–750µm thick. This
thickness is determined by the stresses during processing, and the
requirements for handling robustness. However, for most IC assembly
uses the wafer thickness is reduced to around 50% of this, partly for
mechanical reasons, but also to improve thermal transfer. Dice for other
applications are frequently thinner:
• Integrated circuits for Smart cards are normally 180µm thick, to

meet an overall thickness requirement and optimise mechanical
strength.
• Small signal transistors are ground to around 150µm, because

the die area may be as small as 350µm square.
In the past, the slice would be waxed onto a support, and its reverse
lapped. Current practice is to use vacuum or an adhesive tape to secure
the wafer to the chuck, and reduce the thickness by grinding.
As illustrated in Figure 1, a standard back grinder has a rotating work

chuck, across the centre of which a rotating diamond cup wheel sweeps.
Downward movement of the spindle carrying the cup wheel removes
material from the surface of the wafer, creating a flat surface.
Figure 1: Schematic of a rotational grinder
Obtaining uniformity of wafer thickness has become increasingly

important. However, it is difficult to measure this in situ, so post-grinding
measurements are made using a non-contact capacitative probe. The
parameter normally assessed is Total Thickness Variation (as defined in
ASTM Standard F533), where a typical target value is <1µm. Whilst the
vertical displacement of the spindle is the main determinant of the
thickness, fine control of the thickness distribution can be exercised by
making very small angular adjustments to the spindle (in the range of
0.0001°).
In a practical machine, water is used to cool the wafer, and the thickness
reduction is accomplished in two or three passes. Often the chuck will be
designed to traverse between two wheels, one with coarse and one with
fine grit.
Reducing stresses and flaws
Stresses applied during encapsulation may crack the die and cause other
stress-related failures. Optimised wafer strength is needed to ensure
reliability during both fabrication and packaging. However, grinding
anything inevitably leaves flaws on its surface, which can weaken both
the wafer and the individual dice sawn from it. Given thermal or
mechanical stress, these flaws may then spread into active regions, and
may crack the die. Experiments have shown that there are significant
differences in the degree of damage between normal grinding practice
and an optimised process.
Grinding is a complex process, and Figure 2 illustrates the parameters for

a three-pass grinding operation. Lewis ground wafers to constant
thickness under different conditions and then, using a three-point bend
test mechanism, measured the break strength of dice from different
locations on the wafer. His findings were consistent with the theory that,
since silicon behaves much like glass, grinding scratches act as cleaving
lines for the chip to break along.
Figure 2: The parameters for a wafer-grinding operation
Table 1 summarises the effects that changes in parameters had on the

wafer break strength. In general, wafer strength benefited from using fine
wheel grits, increased wheel and chuck speeds, and reduced feed rates,
even for the first two passes. However, changing grinder settings such as
coarse feed rate can have a major impact on machine throughput. A
compromise is therefore necessary between throughput and die strength,
but Lewis found that a 45% die strength increase could be achieved
without putting machine performance outside acceptable limits.
Table 1: Effect of grinding parameters on wafer break strength

The most significant factors are listed first in each column
factors decreasing break strength factors increasing break strength
increasing coarse thickness decreasing finish wheel grit

increasing finish feed rate increasing coarse wheel grit
increasing rapid feed rate increasing finish wheel rpm
increasing coarse feed rate increasing work chuck rpm
increasing finish thickness
Even after careful grinding, there will still be some damage to the wafer.
This can be divided into two layers: the top layer, typically 5–7µm thick,
is full of micro-cracks, which cause warpage and stress in the wafer; the
second layer, 50–70µm thick, contains crystal dislocations, which cause
degradation of some electrical properties.
At least the top layer is usually removed by etching away perhaps 10–
20µm of material, leaving a smooth but not polished finish, a process
often referred to as ‘SEZ-etch’ after the equipment used.
If possible. probe testing is carried out after the back grinding operation.
This ensures that parts damaged by the process are not transferred to
bonding.
Source : http://www.ami.ac.uk/courses/topics/0265_sbg/
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Semiconductor Back-Grinding

The grinding process

• Integrated circuits for Smart cards are normally 180µm thick, to

• Small signal transistors are ground to around 150µm, because

As illustrated in Figure 1, a standard back grinder has a rotating work

Figure 1: Schematic of a rotational grinder

Obtaining uniformity of wafer thickness has become increasingly

Reducing stresses and flaws

Grinding is a complex process, and Figure 2 illustrates the parameters for

Table 1 summarises the effects that changes in parameters had on the

Table 1: Effect of grinding parameters on wafer break strength

factors decreasing break strength factors increasing break strength

increasing coarse thickness decreasing finish wheel grit

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