Cadence IC Design Manual

For EE3408C

ZHENG Huan Qun

June 2020

Department of Electrical & Computer Engineering

National University of Singapore

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Contents
1. INTRODUCTION ..................................................................................................................................... 3
1.1. Overview of Design Flow............................................................................................................... 3
1.2. Getting Started with Cadence ....................................................................................................... 5
1.3. Using Online Help.......................................................................................................................... 7
1.4. Exit Cadence .................................................................................................................................. 7
2. SCHEMATIC ENTRY ................................................................................................................................ 8
2.1. Creating a Schematic Cellview ...................................................................................................... 9
2.2. Adding Components to Schematic .............................................................................................. 10
2.3. Adding Pins to Schematic ............................................................................................................ 11
2.4. Adding Wires to Schematic ......................................................................................................... 12
2.5. Saving Your Design ...................................................................................................................... 13
3. SYMBOL AND TEST CIRCUIT CREATION............................................................................................... 14
3.1. Creating Symbol .......................................................................................................................... 14
3.2. Editing Symbol ............................................................................................................................ 15
3.3. Building Test Bench ..................................................................................................................... 17
4. SIMULATING YOUR CIRCUIT................................................................................................................ 20
4.1. Start the Simulation Environment .............................................................................................. 20
4.2. Selecting Project Directory.......................................................................................................... 20
4.3. Setup Model Library .................................................................................................................... 21
4.4. Choosing the Desired Analysis .................................................................................................... 21
4.5. Setup Variables ........................................................................................................................... 25
4.6. Saving Simulation Data ............................................................................................................... 26
4.7. Saving Output for Plotting .......................................................................................................... 26
4.8. Viewing the Netlists .................................................................................................................... 28
4.9. Running the Simulation ............................................................................................................... 29
5. VIEWING SIMULATION RESULTS…………………………………………………………………………………………………… 30

5.1. AC Simulation Results…………………………………………………………………………………………………………… 30

5.2. DC simulation Results…………………………………………………………………………………………………………….32
5.3. Transient Simulation Results………………………………………………………………………………………………….34
5.4. XF Simulation Results…………………………………………………………………………………………………………….35
6. CONCLUSION ....................................................................................................................................... 38

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1. INTRODUCTION
This manual describes how to use Cadence IC design tools.

The manual aims to provide a guide for fresh users. Following the manual, users can start
doing analog IC design even though the users don’t have any knowledge of the tools.

An inverter is used to illustrate the whole cycle of analog IC design, and Cadence
Generic 45nm (cg45nm) kit is the technology library used for implementing the inverter. The
method stated in the manual can be applied to other type of analog circuit design.

1.1. Overview of Design Flow

Figure 1 shows a typical analog IC design flow.

The design flow starts from schematic entry with the Cadence schematic capture tool –
Schematic Editor. Devices or cells from the cg45nm or other libraries are used to build your
circuit. Your design is hierarchical; therefore higher level schematics also incorporate cells
which you have already developed. The schematics which you enter at this stage therefore
typically consist of a number of base library cells and also lower level cells designed yourself.
These are described in Sections 2 and 3 of the manual.
When you have finished designing a particular circuit, you need to simulate it to ensure
that it works as expected. It would be unlikely that your circuit works as expected at the first
time so you have to repeat the cycle to improve the circuit, as shown in Figure 1, until the
circuit works satisfactorily. This must be done for each sub-circuit of your design and then for
the top level design. How to simulate and view the performance of simulation results are
presented in Sections 4 of the manual.
When the performance of the circuit is satisfactory, it is ready to start the physical design
or layout of the circuit. The layout starts with the cell or device placement. Once the cells have
been placed, routing can be carried out. Routing connects the cells/device of the design.
After finishing placement and routing, the layout has to go through the Design Rule Check
(DRC) with rule decks provided by PDK provider, to ensure that there is no design rule
violation in the layout. The layout has to be rectified accordingly to the rules’ requirement till
it passes DRC.
Upon a successful DRC, it is Layout-versus-Schematic (LVS) check, to assure that all
connections in the layout are correct. The layout has to be amended accordingly to the
schematic If LVS doesn’t pass. DRC has to be done whenever layout is changed. The process
is repeated until the LVS passes.

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Figure 1. Analog IC Design Flow

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 The next step is parasitic extraction (PEX) to get the extracted view of the circuit, which is
used for post–layout simulation. The extracted view includes the parasitic effects in both the
instances/devices and the required wiring interconnects of the circuit.
Following DRC, LVS and PEX, it is post-layout simulation. The post-layout simulation is
essential to make sure that the circuit with the extra parasitic parameters functions well and
still meet the design specifications. If the performance of the post-layout simulation is not
acceptable, back to the stage of schematic entry to check the circuit. Basically, re-design the
circuit is necessary. Repeat the whole flow until the results of the post-layout simulation meet
the design specifications.
If everything is satisfactory, the next stage is GDSII Generation. It generates a file which
depicts the low level geometry of layout. GDSII format is industry standard format suitable for
a semiconductor company to fabricate and manufacture the chip of layout. This is briefed in
the last section of the manual.
This manual include the contents up to schematic level simulation only.

1.2. Getting Started with Cadence

Upon logging into your account, you will be brought to the Linux Desktop Environment.
Right click on the desktop and click Open Terminal to open a “window” on the desktop. This
window is the Linux command line prompt at which you can run Linux commands. After
running a Linux command, this window also shows the output of the command.
The following steps show how to start Cadence virtuoso for doing schematic level simulation.
A. Create a working directory - project (it can be any name as you like) with the
command:
mkdir project
where mkdir is Linux command and the project is the directory name;
B. Enter the working directory with the command:
cd project
where the cd is the Linux command;
C. Check with GA about the environment setup for using the respective PDK.
D. Start cadence in the working directory – project with the following command:
virtuoso &
where virtuoso is the command to start Cadence IC design tool.
Now, Cadence tools are successfully started. Keeps only the Command Input Window
(CIW) which is shown in Figure 2.

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 Figure 2. CIW Window
Do not close this CIW and try to keep it in view whenever you are using Cadence. Error
messages and output from some of the tools are always sent to the CIW. If something doesn't
appear to be working, always check the CIW for error messages. In addition, the CIW allows
the user great control over Cadence by interpreting skill commands which are typed into it.
E. In the CIW, select ToolsLibrary Manager. The Library Manager pop up as in
Figure 3. The Library Manager is where you create, add, copy, delete and organize
your libraries and cell views. The sample

Figure 3. Library Manager Window

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 You can see that the library gpdk045 as well as some other libraries appear in the Library
column of the library manager. Yours could be different if different design kit is used.
Now, you have started Cadence tool and loaded the design kit successfully. There are some
documents in the doc folder under the design kit installation directory, and you can always refer
to these documents for the information such as devices, device models, DRC rules and others
related to the kit.
Next time, you need only to repeat the steps B and D, for launching Cadence virtuoso and
doing your project.

1.3. Using Online Help

Cadence provides a comprehensive online manuals for all Cadence tools. You can launch
the online help by typing the following command at the Linux prompt.
cdnshelp
This invokes the online software manuals. Alternately, there is a help menu on each Cadence
window. Manual which is related to that window related will pop-up once clicking on the help
button.

1.4. Exit Cadence

To exit Cadence, just click on the cross sign X or FileExit in CIW. It is necessary to exit
Cadence when it is not in use. Your library file would be locked or cannot edited next time if
Cadence was not exited properly.

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2. SCHEMATIC ENTRY
Now that Cadence is running, you are almost ready to start entering schematics. However,
you must first create a library which will be used to store all the parts of your design. Then,
schematic can be created in the library. Creating a New Design Library
A. In the Library Manager window, select FileNewLibrary. New Library form
pops up as shown in Figure 4.
B. In the New Library form referring to Figure 4, key in your design library name
(example: test) in the field of Name, and then click Ok.
C. Click Ok in the pop-up window - the Technology File for New Library, referring to
Figure 5.
D. Choose gpdk045 in the Attach Library to Technology Library form, referring to
Figure 6, and then click Ok.

Figure 4. New Library Form

Figure 5. Technology File for New Library Form

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 Figure 6. Attach Library to Technology File Form
A new library, named test, should appear in your Library Manager window.

2.1. Creating a Schematic Cellview

A. In Library Manager, select the Library where you would like to create a schematic. Then,
select FileNewCell View.
B. Set up the New File form as Figure 7

Figure 7. Create CellView

C. Click OK when done. A blank schematic window for the "inv" (your cell name)
schematic appears.
Explore the functions available by putting your mouse over the toolbar and fixed menu icons.

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 In addition, note that some of the menu selections have alphabets listed to the right of
them. These are bind-key or shortcut-key definitions which are very useful in the long run.
Test them out during the schematic drawing in subsequent steps.

2.2. Adding Components to Schematic

Figure 8 shows the schematic which you are going to patch, and the property of each
component is listed in Table 1.

Figure 8. Inverter Circuit

Tabel 1. Component Properties of Figure 8: Inverter Circuit

Components Library Name Cell Name Properties
PMOS gpdk045 pmos1v l:45nm w:120nm (default size)
NMOS gpdk045 nmos1v l:45nm w:120nm (default size)

Here is the example on how to add component instances by placing cell views from
libraries. Type “i” bind-key or select CreateInstance in the schematic window or click
on the menu bar to display Add Instance form. Then in the Add Instance window, select
gpdk045 as Library, choose the NMOS transistor by selecting nmos1v in Cell and also
choose symbol as View, as shown in Figure 9.

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 Figure 9. Add Instance Form
Similarly, add the pmos1v into the schematic. As an example, here we just keep all the
parameters as default.
If you place a component with the wrong parameter values, select the component and type
“q” bindkey or use the EditPropertiesObjects command to change the parameters. Use
the EditMove command or type “m” if you place components in the wrong location.

2.3. Adding Pins to Schematic

You must place I/O pins in your schematic to identify the inputs and the outputs. A pin can
be an input, output or an input-output (bi-directional) pin.
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 Type “p” or select Add Pin from inv Schematic Window or click the Pin fixed menu
icon in the schematic window. The Add Pin form appears as Figure 10.

Figure 10. Add Pin Form

Click Hide and move you cursor to the Schematic Window. Place pins at the correct places and
click right mouse key to rotate the pin if necessary.
Add pins according to Table 2, paying attention to the direction.
Table 2. Pin Names and Direction of inv

Pin Names Direction

Vin Input
Vout Output
VDD, GND Input-Output

Caution: Do not use the add component form to place schematic pins.

2.4. Adding Wires to Schematic

Add wires to connect the components and pins in the design.

A. Type “w” or select Add Wire (narrow) in Schematic Window or click (narrow)
fixed menu icon.
B. In the schematic window, click on a pin of one of your components as the first point
for your wiring. A diamond shape appears over the starting point of this wire.

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 C. Follow the prompts at the bottom of the design window and click left mouse key on
the destination point for your wire.
D. Continue wiring the schematic. When done wiring, press Esc with your cursor in the
schematic window to cancel wiring.

2.5. Saving Your Design

Check the design to ensure that it is correct and save the design.
A. Click the Check and Save icon in the schematic window.
B. Observe the CIW output area, for the information of the check and save action.

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3. SYMBOL AND TEST CIRCUIT CREATION
Symbols are useful when creating designs as it is impractical to show every transistor on the
top level schematic. Instead, the symbols of cells are created in order to instantiate them in the
higher level schematics and make them more readable (i.e. hierarchical designs). Create a symbol
for your design so you can place it in a test circuit for simulation.

3.1. Creating Symbol

A. In the inv schematic window, select Create  Cellview  From Cellview. Cellview
From Cellview pops up as shown in Figure 11.

Figure 11. Cellview From Cellview Form

B. Click OK in the Cellview From Cellview form. The Symbol Generation Options form
appears as Figure 12. Enter the information listed in Table 3 for the symbol.

Table 3: Pin Spectifications

Left Pins : Vin
Right Pins : Vout
Top Pins: VDD
Bottom Pins: GND

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 Figure 12. Symbol Generation Options Form

C. Click OK in the Symbol Generation Options form. A window with a symbol created
automatically by the tools pops up, referring to Figure 13.

Figure 13. Symbol Generated Automatically

D. Observe the CIW output pane and note the messages stating Adding ‘CDF
information ...’.

3.2. Editing Symbol

You can modify the symbol to have a more meaningful shape for easy recognition.

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A. Move your cursor over the symbol, until the entire green rectangle is highlighted. Click
left to select it.
B. Click Delete icon in the symbol window to delete the green rectangle.
C. Select CreateShapePolygon. Follow the prompts at the bottom of the symbol, and
draw the triangle shown in Figure 14.
D. Type “m” or click Move icon in the symbol window, move the pins to the final
destination.
E. Select [@partName], and use EditPropertiesObject to change it to inverter as
shown in Figure 14.

Figure 14. Edit Object Properties Form

F. Save your edited symbol view. The final symbol is shown in Figure 15.

Figure 15. Symbol of inv

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 3.3. Building Test Bench

To test the inverter that you have just built, you need to create a test bench. This test bench
will also be used during the post-layout simulation.

Creating an inv_test schematic cellview with the below information, following the steps
listed in Section 2 – SCHEMATIC ENTRY. The test bench is as shown in Figure 17.
Library Name : test
Cell Name : inv_test
View Name : schematic

Library Name Cell Name Properties

test inv_test
analogLib Vdc VDD
analogLib Vsin Referring to Figure 16
analogLib gnd GND
analogLib cap 1f F

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Figure 16. Vsin Form

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 Figure 17. Test Bench – inv_test for inv Circuit

Note:
There are wire names Vin and Vout in Figure 17. These can be created by clicking on
CreateWire Name on the inv_test schematic window. Key in Vin Vout in the Names field of
the Add Wire Name form, and then click Hide. Moving your mouse to the schematic window,
click the wire where you want it to be named in the same sequence as typing the names in the
Names field.

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4. SIMULATING YOUR CIRCUIT
Before starting the simulation, make sure that the schematic (inv_test) is open, then perform
the following steps.

4.1. Start the Simulation Environment

In your schematic window, select Launch ADE L. The Analog Design Environment
(ADE) window appears as shown in Figure 18.

Figure 18. ADE Window

4.2. Selecting Project Directory

In the ADE window, select SetupSimulator/ Directory/ Host. A Choosing Simulator

form appears as Figure 19. In the Project Directory blank, type in /var/tmp/(desired folder
name) to save your simulation files in the /var/tmp directory on the local server. Click OK to
confirm.

Figure 19. Choosing Simulator/Directory/Host Form

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 As each user account has a limited quota, this helps to conserve memory space in your account
and prevents you from exceeding your account quota. However, note that contents in this folder is
deleted periodically every 30 days automatically.

4.3. Setup Model Library

In the ADE window, select SetupModel Libraries. The Model Library setup form
appears. Double click the column of section, and then click the down arrow to choose tt which is
typical N and P model parameters. The model library setup for the inv_test circuit is shown in
Figure 20. Click ok on the setup form to finish the settings.
The information of models can be found in
/app11/cg45nm/gpdk045_v4_0/docs/gpdk045_pdk_referenceManual.pdf. Checking with GA
for the reference about the models you used if necessary.

Figure 20. Model Library Setup for inv_test

4.4. Choosing the Desired Analysis

In the ADE window, click the Choose Analyses icon . The Choosing Analyses form
appears. Cadence ADE is able to run several types of simulations consecutively. You are then able
to view the signals from different simulations at the same time. In this example, we will do AC,
DC, transient and XF analyses, so we shall setup through the ADE as follows.
 AC Analysis (Figure 21): This analysis simulates the frequency dependent characteristics
of the circuit.
 DC Analysis (Figure 22): This analysis simulates the DC operating points of transistors
and other devices.
 Transient Analysis (Figure 23): Specify a Stop Time of 6ns. The internal engine time step
is generally a function of the interval you specify.
 XF analysis (Figure 24): Transfer function analysis, it simultaneously computes
individual transfer function from every independent source to a single output.

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Figure 21. Setup for AC Analysis

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Figure 22. Setup for DC Analysis

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Figure 23. Setup for Transient Analysis

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 Figure 24. Setup for XF Analysis
.

4.5. Setup Variables

There is a variable, VDD, in the inv_test circuit. We need to set a value to it before starting
simulation.

In the ADE window, click Variables. Enter the name as the variable name VDD, then set the value
as 1.1, and finally click Ok. Please take note that 1.1v is the nominal voltage for this technology.

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 Figure 25. Editing Design Variables

4.6. Saving Simulation Data

The simulation environment is configured to save all node voltages in the design by default.
In larger designs, where saving all of the data requires too much disk space, you can select a
specific set of node to save. Following steps show you how to select terminals to save.
1. In the ADE window, select OutputsSave All.
2. The Keep Options form appears. Do not modify the form at this time. However, if you
need to save less data, under the first option “Select signals to output”, Click “selected”.

4.7. Saving Output for Plotting

Select the signals that you would like to observe.

A. Select OutputsTo Be PlottedSelect On Design.
B. Note that if you click on wires / nets, voltage signals are selected. If you click on
connection nodes, currents flowing through that note and into the component are saved.
C. Follow the prompts at the bottom of the schematic window. Click on the output wires
labeled with Vout (select the wire that you want to monitor).
D. Press Esc with your cursor in the schematic window when finished.

Now you have set up the simulation environment which as shown in Figure 26. You can save
the simulation state. This saves all the information such as the Model Path, outputs, analyses,
environment options, and variables so that you do not need to repeat theses processes the next time.

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 Figure 26. ADE window with completed settings

In the ADE window, select SessionSave State. Tick Cellview and then click OK. You can
recall your settings by selecting SessionLoad State afterwards as Figure 27.

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 Figure 27. Saving Session State

4.8. Viewing the Netlists

Sometimes, you need to view the netlist of your circuit or design. You can do so through
the ADE, select SimulationNetlistCreate / Display / Recreate.

If there are any errors encountered during this step, check the messages in the CIW and
retrace your steps to see that all data was entered properly.

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 4.9. Running the Simulation

Select SimulationNetlist and Run to start the simulation or click on the Run
Simulation icon in the Simulation Window. After the simulation is done, a waveform window
will pop up as Figure 28.
Next session, will show how to browser the simulation results.

Figure 28. Output of Simulation

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5. VIEWING SIMULATION RESULTS
In this section, we will browse the simulation results with exploring tools of Cadence
virtuoso.

5.1. AC Simulation Results

Plotting AC Waveform
The direct plot function lets user easily choose signals from a design and plot them directly.
This is very useful in debugging a design while you view the waveforms at different nodes in
your circuit.
A. In the ADE window, select Results—>Direct Plot—>Transient Signal/ Transient
Signal Minus DC/ Transient Sum/ Transient Difference/ AC Magnitude/ AC Phase/
AC Magnitude & Phase
B. Follow the prompts at the bottom of your schematic window and select the nodes for
output.

For example, select Results—>Direct Plot—>AC Gain and Phase. Follow the instructions at

the bottom of the screen to select Vout then Vin. Note that clicking on the waveform
window can separate the waveforms.

Figure 29. AC Gain and Phase of the Inverter

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Using Markers
With Markers, user can find the results of simulation such as phase margin, unity gain, et cetera.
Figure 30 shows two markers created on the waveforms, a horizontal (H2) and a vertical (V1)
markers.

Figure 30. Exploring Waveforms with Markers

You can create a horizontal or vertical marker by clicking Marker —> Create Marker…
on the waveform window. A Create Graph Marker windows pop up. Fill in the field of Y
positions for a horizontal marker (or X positions for a vertical marker), and then click OK.

For example, to create a horizontal marker with a value = 0 dB. Type 0 dB in the Y positions
of the Create Graph Marker window as Figure 31. Then, click OK. A horizontal marker as same
as H2 of Figure 30 will appear.

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 Figure 31. Create a Horizontal Marker

Explore the icons on the toolbar as well as the various items on the menu. Try to add markers
as that is something that will be used often during your simulations. You can also update the titles
and labels on your plot to make them easy to read or more meaningful, if necessary.
*Quick Tip : Shortcuts “a” and “b” to place a delta marker where you observe the difference
between two points. What does shortcuts “v” and “h” do?

5.2. DC Simulation Results

DC operating points of a circuit and transistor operating points are important information, for a
circuit designer. This section, we will see how to get these information after running DC simulation.

DC Operating Points
A. Select the symbol (inverter for this sample) that DC operating points need to be checked,
and then click Edit—>Hierarchy—>Descend Read… (click Return to go back
afterwards).
B. Click OK in the popup window as Figure 32.
C. In the ADE window, select Results—>Annotate—> DC Operating Points. DC
operating point data appears near every component in your schematic window as Figure
33.

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 Figure 32. Edit Schematic Hierarchy

Figure 33. Printing DC Operating Points

Transistor Operating Points

A. In the ADE window, select Results—>Print—>Transistor Operating Points.
B. Select one transistor, the pmos1v transistor for example.
C. A Results Display Window appears with all the available parameters related to the
transistor as Figure 34.

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 Figure 34. Transistor Operating Points

5.3. Transit Simulation Results

You can use direct plot and markers to look into the transient simulation results, as follows.

A. In the ADE window, select Results—>Direct Plot—>Transient Signal.

B. Follow the prompts at the bottom of your schematic window to select the nodes for
ploting, Vout and Vin for the example.
C. Place markers based on your concerns, referring to section 5.1 for placing markers if
necessary.

Figure 35 shows the transient waveforms plotted according to above steps.

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 Figure 35. Transient Simulation Results

5.4. XF Simulation Results

With direct plot function, we can get the xf signal waveform(s) also.

A. In the ADE window, select Results—>Direct Plot—>Main Form…

B. Setup the form as Figure 36. Then select the source on the schematic window, V1 for
example. The voltage gain should appear on the graph window.
C. Unselect dB20 and then select Phase.
D. Repeat step B. The XF simulation waveforms appear as Figure 37.

From this point, Markers can be used to look into the waveforms also as previous sections.

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Figure 36. Direct Plot Form

Figure 37. XF Waveforms

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 By now, you have finished schematic level simulation (pre-layout simulation).
Next, it needs to draw the layout of the inverter circuit and then do post-layout simulation to
check the circuit performance, which is not included in this module.

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6. CONCLUSION
Analog IC design method with Cadence IC 6 – Virtuoso is presented in this manual. The flow
as shown in Figure 1 is iterative and stops only when the design is satisfactory. The details of up-
to the schematic level simulation is described. I wish that the manual is helpful for users who want
to start learning analog IC design. You are welcome to feedback at any time.

REFERENCES
1. Virtuoso ADE Explorer User Guide, Product Version IC 6.1.7, January 2016.
2. Virtuoso Analog Design Environment XL User Guide, Product Version IC 6.1.7, January
2016.

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