Location via proxy:   [ UP ]  
[Report a bug]   [Manage cookies]                
Scribd
Upload
5 views

CA2021_project2_slides

The document outlines the specifications and requirements for an individual project involving a pipelined CPU with an L1 data cache, due on June 15. It details the project components, including memory sizes, cache policies, and output file requirements, along with grading criteria and submission rules. Students must implement their design in Verilog and demonstrate their work to the TA, with penalties for late submissions and compilation issues.

Uploaded by

jasd
Copyright
© © All Rights Reserved
Available Formats
Download as PDF, TXT or read online on Scribd
5 views

CA2021_project2_slides

The document outlines the specifications and requirements for an individual project involving a pipelined CPU with an L1 data cache, due on June 15. It details the project components, including memory sizes, cache policies, and output file requirements, along with grading criteria and submission rules. Students must implement their design in Verilog and demonstrate their work to the TA, with penalties for late submissions and compilation issues.

Uploaded by

jasd
Copyright
© © All Rights Reserved
Available Formats
Download as PDF, TXT or read online on Scribd
You are on page 1/ 16

Project 2: Pipelined

CPU + L1 Data Cache


TA: 陳炫均
Announcement
• Individual Project
• Deadline: 6/15 (Tue.) 23:59

• Demo:
• Time slot: TBD
• Execute your program before TA and answer a few
questions

2
Specification
Use Verilog to model pipeline CPU with
• Off-chip Data Memory
• Size: 16KB
• Data width: 32 Bytes
• Memory access latency: 10 cycles (send an ack when finish
access)
• L1 Data Cache
• Size: 1KB
• Associative: 2-way
• Replacement policy: LRU
• Cache line size: 32 Bytes
• Write hit policy: write back
• Write miss policy: write allocate
• offset: 5 bits, index: 4 bits, tag: 23 bits

3
testbench.v
• (optional) Initialize registers in all modules
• Connecting CPU and off-chip Data_Memory
• Load instruction.txt into instruction
memory
• Create clock signal
• Dump Register files & Data memories in each
cycle
• Print result to output.txt and cache.txt

4
Output Files
• Print result to output.txt
• Output cache status when memory access occurs
• Criteria: we will check the final state is correct or
not (The cycle count does not matter)
• Print result to cache.txt
• Record cache hit or cache miss for each cache
access
• Criteria: we will check the order of hit and miss
accesses is identical to the correct answer (The
cycle count does not matter)
• DO NOT CHANGE THE OUTPUT FORMAT

5
Grading Policy
• (80%) Programming
• You will get 0 point if your code cannot be compiled
• Grading at demo. You have to answer several questions
about how you implement at demo. You may get 0 point
on this part if you cannot clearly answer the questions
(regarded as plagiarism)
• (20%) Report
• Implementation of modules
• Cache controller in detail
• You can draw a picture to explain if you want
• Difficulties encountered and solutions of this projects
• Late punishment: 10 points deduction per day
6
Evaluation Criteria

For output.txt, we will only check the values of registers and data
memory at the last cycle. You don’t have to be exactly the same as
reference output at every cycle.
7
Evaluation Criteria (cont.)

For cache.txt, we will only check number of hit/miss and their order.
cycle count doesn’t matter. 8
Project 1 to Project 2

IF ID EX MEM WB

Project 1

Inst. Data
Mem Mem

IF ID EX MEM WB

Project 2

Inst. Data Data


Mem Cache Mem
9
System Block Diagram
enable: memory access enable
write: write data to memory
ack: memory acknowledge

addr addr
data (32 bits) data (256 bits)
MemRead enable
MemWrite L1 MemWrite
Project 1 Data Data Memory
Cache
stall ack
data (32 bits) data (256 bits)

Off-chip Memory
CPU 10
Example files
L1 Data Cache

Project 1 Cache Controller Data Memory

Cache SRAM
(Tag & Data)

11
Example files
• CPU.v: connection between modules
• dcache_controller.v: handles I/O requests
• dcache_sram.v: Modify the data structure
within it to support 2-way associative cache.
• Data_Memory.v You can modify them as you want
But make sure you include them as
• testbench.v submission

• Instruction_Memory.v
• PC.v
• Registers.v

12
Datapath & Modules

13
2-way associative cache

14
Submission Rules
• studentID_project2 (dir)
• studentID_project2/codes/*.v
• studentID_project2/studentID_project2_report.
pdf
• Pack the above directory into a zip file
• When we unzip your file, the output should be a
single directory named studentID_project2

15
Submission Rules (cont.)
• In testbench.v, you must check the following
settings before submission
• Read instruction from ./instruction.txt
• Dump output to ./output.txt and ./cache.txt
• Your code can be compiled with the follow
command
• $ iverilog –o CPU.out *.v

16

You might also like