2974 F

LTC2974
1
2974f
TEMPERATURE (C)
50
E
R
R
O
R

(
%
)
50 75
0.07
0.06
0.05
0.04
0.03
0.02
0.01
0
0.03
0.02
0.01
2974 TA01b
25 0 25 100
THREE TYPICAL PARTS
Typical applicaTion
FeaTures DescripTion
Quad Digital Power Supply
Manager with EEPROM
The LTC
2974 is a quad, digital power-supply monitor,

supervisor, sequencer, and margin controller. Supervisory
functions include over and under threshold limits for cur-
rent, voltage and temperature on four output channels as
well as OV/UV threshold limits for a single input channel.
Programmable fault response allows the power supplies
to be disabled with optional retry after a fault has been
detected. Serial bus telemetry allows four output voltages,
four output currents, four output temperatures, internal
die temperature and one input voltage to be monitored.
Power supply sequencing, precision point-of-load voltage
adjustment and margining are supported with PMBus
commands. A programmable watchdog timer monitors
microprocessor activity for a stalled condition and resets
the micro if necessary. The 1-wire synchronization bus
supports power supply sequencing across multiple LTC
digital power devices. User programmable parameters
can be stored in EEPROM. Voltage/current supervisor,
voltage/current monitor and temperature faults can also
be logged to EEPROM.
L, LT, LTC, LTM, Linear Technology, the Linear logo and Module and PolyPhase are registered
trademarks and LTpowerPlay is a trademark of Linear Technology Corporation. All other
trademarks are the property of their respective owners. Protected by U.S. Patents including
7382303 and 7420359.
Quad PMBus Power Supply Controller with EEPROM
applicaTions
n
I
2
C/SMBus Serial Interface
n
PMBus Compliant Command Set
n
Configuration EEPROM with CRC
n
Black Box Fault Logging to Internal EEPROM
n
Differential Input, 16-Bit ADC with less than
0.25% of Total Unadjusted Error
n
Four Voltage Servos Precisely Adjust Supply
Voltages Using 10-Bit DACs with Soft-Connect
n
Monitors Four Output Voltages, Four Output Currents
and One Input Voltage
n
Monitors Four External Temperature Sensors and
Internal Die Temperature
n
4-Channel Sequencer, Time Based or Tracking
n
Programmable Watchdog Timer
n
Four OV/UV V
OUT
and One V
IN
Supervisor
n
Four Overcurrent/Undercurrent Supervisors
n
Supports Multi-Channel Fault Management
n
Operates Autonomously without Additional Software
n
LTC2974 Can Be Powered from 3.3V or 4.5V to 15V
n
Available in 64-Lead 9mm 9mm QFN Package
n
Computers
n
Network Servers
LTC2974*
4.5V < V
IBUS
< 15V
GND
TO P
RESETB
INPUT
WATCHDOG
TIMER INTERRUPT
*SOME DETAILS OMITTED FOR CLARITY
ONLY ONE OF FOUR CHANNELS SHOWN
**LTC2974 MAY ALSO BE POWERED
DIRECTLY FROM EXTERNAL 3.3V SUPPLY
V
IN
I
I
+
R20
R30
0.1F
MMBT3906
R10
2974 TA01
RUN/SS
SGND
V
FB
BG
SW
GND
LOAD
DC/DC
CONVERTER
V
PWR
AUXFAULTB
OV
SDA
SCL
ALERTB
CONTROL0
FAULTB1
PMBus
INTERFACE
TO/FROM
OTHER
DEVICES
FAULTB0
SHARE_CLK
ASEL0
ASEL1
WP
V
IN_SNS
V
DAC0
V
SENSEP0
WDI/RESETB
V
SENSEM0
I
SENSEM0
I
SENSEP0
T
SENSE0
V
OUT_EN0
PWRGD
V
DD33**
TG
ADC Total Unadjusted Error vs
Temperature
LTC2974
2
2974f
Table oF conTenTs
Features ........................................................... 1
Applications ...................................................... 1
Typical Application .............................................. 1
Description........................................................ 1
Absolute Maximum Ratings .................................... 4
Order Information ................................................ 4
Pin Configuration ................................................ 4
Electrical Characteristics ....................................... 5
PMBus Timing Diagram ......................................... 9
Typical Performance Characteristics ........................ 10
Pin Functions .................................................... 13
Block Diagram ................................................... 15
Operation......................................................... 16
LTC2974 Operation Overview ......................................... 16
EEPROM .................................................................... 17
AUXFAULTB ................................................................... 17
RESETB .......................................................................... 18
PMBus Serial Digital Interface ....................................... 18
PMBus ....................................................................... 18
Device Address .......................................................... 18
Processing Commands.............................................. 19
PMBUS Command Summary .................................. 22
Summary Table .......................................................... 22
Data Formats ............................................................. 27
PMBus Command Description ................................ 28
Addressing and Write Protect ........................................ 28
PAGE .......................................................................... 28
WRITE_PROTECT ...................................................... 28
WRITE-PROTECT Pin ................................................ 29
MFR_PAGE_FF_MASK .............................................. 29
MFR_I2C_BASE_ADDRESS ...................................... 29
On/Off Control, Margining and Configuration ................ 30
OPERATION ............................................................... 30
ON_OFF_CONFIG ....................................................... 31
MFR_CONFIG_LTC2974 ............................................ 32
Cascade Sequence ON with Time-Based
Sequence OFF ............................................................ 33
MFR_CONFIG2_LTC2974 .......................................... 35
MFR_CONFIG3_LTC2974 .......................................... 35
Tracking Supplies On and Off .................................... 37
Tracking Implementation ........................................... 38
MFR_CONFIG_ALL_LTC2974 .................................... 39
Programming User EEPROM Space ............................... 40
STORE_USER_ALL and RESTORE_USER_ALL ........ 41
Bulk Programming the User EEPROM Space ............ 41
MFR_EE_UNLOCK ..................................................... 41
MFR_EE_ERASE ....................................................... 42
MFR_EE_DATA .......................................................... 42
Response When Part Is Busy .................................... 43
MFR_EE Erase and Write Programming Time ........... 43
Input Voltage Commands and Limits ............................. 43
VIN_ON, VIN_OFF, VIN_OV_FAULT_LIMIT, VIN_OV_
WARN_LIMIT, VIN_UV_WARN_LIMIT and
VIN_UV_FAULT_LIMIT .............................................. 43
Output Voltage Commands and Limits .......................... 44
VOUT_MODE ............................................................. 44
VOUT_COMMAND, VOUT_MAX, VOUT_MARGIN_
HIGH, VOUT_MARGIN_LOW, VOUT_OV_FAULT_LIMIT,
VOUT_OV_WARN_LIMIT, VOUT_UV_WARN_LIMIT,
VOUT_UV_FAULT_LIMIT, POWER_GOOD_ON and
POWER_GOOD_OFF .................................................. 45
MFR_VOUT_DISCHARGE_THRESHOLD .................... 45
MFR_DAC .................................................................. 45
Output Current Commands and Limits .......................... 46
IOUT_CAL_GAIN ....................................................... 46
IOUT_OC_FAULT_LIMIT, IOUT_OC_WARN_LIMIT and
IOUT_UC_FAULT_LIMIT ............................................ 47
MFR_IOUT_CAL_GAIN_TC ........................................ 47
External Temperature Commands And Limits ................ 48
OT_FAULT_LIMIT, OT_WARN_LIMIT, UT_WARN_
LIMIT and UT_FAULT_LIMIT ..................................... 48
MFR_TEMP_1_GAIN and MFR_TEMP_1_OFFSET ...... 48
MFR_T_SELF_HEAT, MFR_IOUT_CAL_GAIN_TAU_INV
and MFR_IOUT_CAL_GAIN_THETA .......................... 49
Sequencing Timing Limits and Clock Sharing ................ 51
TON_DELAY, TON_RISE, TON_MAX_FAULT_LIMIT
and TOFF_DELAY ....................................................... 51
MFR_RESTART_DELAY ............................................. 51
Watchdog Timer and Power Good ................................. 52
MFR_PWRGD_EN ..................................................... 52
Clock Sharing ............................................................ 52
MFR_POWERGOOD_ASSERTION_DELAY ................ 53
Watchdog Operation .................................................. 53
MFR_WATCHDOG_T_FIRST and
MFR_WATCHDOG_T .................................................. 53
Fault Responses ............................................................. 54
Clearing Latched Faults ............................................. 54
VOUT_OV_FAULT_RESPONSE and VOUT_UV_FAULT_
RESPONSE ................................................................ 55
IOUT_OC_FAULT_RESPONSE and IOUT_UC_FAULT_
RESPONSE ................................................................ 56
OT_FAULT_RESPONSE, UT_FAULT_RESPONSE,
VIN_OV_FAULT_RESPONSE and VIN_UV_FAULT_
RESPONSE ................................................................ 57
TON_MAX_FAULT_RESPONSE ................................. 58
MFR_RETRY_DELAY ................................................. 58
MFR_RETRY_COUNT ................................................ 58
Shared External Faults ................................................... 59
MFR_FAULTB0_PROPAGATE and MFR_FAULTB1_
PROPAGATE .............................................................. 59
LTC2974
3
2974f
MFR_FAULTB0_RESPONSE and MFR_FAULTB1_
RESPONSE ................................................................ 60
Fault Warning and Status ............................................... 61
CLEAR_FAULTS ......................................................... 61
STATUS_BYTE ........................................................... 61
STATUS_WORD ......................................................... 62
STATUS_VOUT .......................................................... 62
STATUS_IOUT ........................................................... 63
STATUS_INPUT ......................................................... 63
STATUS_TEMPERATURE ........................................... 63
STATUS_CML ............................................................ 64
STATUS_MFR_SPECIFIC ........................................... 64
MFR_PADS ................................................................ 65
MFR_COMMON ......................................................... 65
Telemetry ....................................................................... 66
READ_VIN ................................................................. 67
READ_VOUT .............................................................. 67
READ_IOUT ............................................................... 67
READ_TEMPERATURE_1 .......................................... 67
READ_TEMPERATURE_2 .......................................... 67
READ_POUT .............................................................. 67
MFR_READ_IOUT ..................................................... 67
MFR_IOUT_SENSE_VOLTAGE ................................... 68
MFR_VIN_PEAK ........................................................ 69
MFR_VOUT_PEAK ..................................................... 69
MFR_IOUT_PEAK ...................................................... 69
MFR_TEMPERATURE_1_PEAK ................................. 69
MFR_VIN_MIN .......................................................... 69
MFR_VOUT_MIN ....................................................... 69
MFR_IOUT_MIN ........................................................ 69
MFR_TEMPERATURE_1_MIN ................................... 69
Fault Logging ................................................................. 70
Fault Log Operation ................................................... 70
MFR_FAULT_LOG_STORE ........................................ 70
MFR_FAULT_LOG_RESTORE .................................... 70
MFR_FAULT_LOG_CLEAR ........................................ 71
MFR_FAULT_LOG_STATUS ....................................... 71
MFR_FAULT_LOG ...................................................... 71
MFR_FAULT_LOG Read Example .............................. 74
Identification/Information .............................................. 78
CAPABILITY ............................................................... 79
PMBus_REVISION ..................................................... 79
MFR_SPECIAL_ID ..................................................... 79
MFR_SPECIAL_LOT .................................................. 79
User Scratchpad ............................................................. 79
USER_DATA_00, USER_DATA_01, USER_DATA_02,
USER_DATA_03, USER_DATA_04, MFR_LTC_
RESERVED_1 and MFR_LTC_RESERVED_2 ............. 79
Applications Information ...................................... 80
Overview ........................................................................ 80
Powering the LTC2974 ................................................... 80
Setting Command Register Values ................................. 80
Sequence, Servo, Margin and Restart Operations ......... 80
Command Units On or Off ......................................... 80
On Sequencing .......................................................... 80
On State Operation .................................................... 81
Servo Modes ............................................................. 81
DAC Modes ................................................................ 81
Margining .................................................................. 82
Off Sequencing .......................................................... 82
V
OUT
Off Threshold Voltage ....................................... 82
Automatic Restart via MFR_RESTART_DELAY
Command and CONTROL pin .................................... 82
Fault Management .......................................................... 82
Output Overvoltage, Undervoltage, Overcurrent, and
Undercurrent Faults ................................................... 82
Output Overvoltage, Undervoltage, and Overcurrent
Warnings ................................................................... 83
Configuring the AUXFAULTB Output .......................... 83
Multi-Channel Fault Management .............................. 83
Interconnect Between Multiple LTC2974s ..................... 84
Application Circuits ........................................................ 85
Trimming and Margining DC/DC Converters with
External Feedback Resistors ..................................... 85
Four-Step Resistor Selection Procedure for DC/DC
Converters with External Feedback Resistors ........... 85
Trimming and Margining DC/DC Converters with a
TRIM Pin .................................................................... 86
Two-Step Resistor and DAC Full-Scale Voltage
Selection Procedure for DC/DC Converters with a
TRIM Pin .................................................................... 87
Measuring Current with a Sense Resistor ................. 87
Measuring Current with Inductor DCR ...................... 87
Single Phase Design Example ................................... 88
Measuring Multiphase Currents ................................ 88
Multiphase Design Example ...................................... 89
Anti-aliasing Filter Considerations ............................. 89
Sensing Negative Voltages ........................................ 89
Connecting the USB to I
2
C/SMBus/PMBus Controller
to the LTC2974 in System .......................................... 90
Accurate DCR Temperature Compensation .................... 91
LTpowerPlay: An Interactive GUI for Digital Power ........ 93
PCB Assembly and Layout Suggestions ........................ 94
Bypass Capacitor Placement ..................................... 94
Expose Pad Stencil Design ........................................ 94
PCB Board Layout ..................................................... 94
Package Description ........................................... 95
Typical Application ............................................. 96
Related Parts .................................................... 96
Table oF conTenTs
LTC2974
4
2974f
pin conFiguraTion absoluTe MaxiMuM raTings
Supply Voltages:
V
PWR
to GND ......................................... 0.3V to 15V
V
DD33
to GND ....................................... 0.3V to 3.6V
V
DD25
to GND ..................................... 0.3V to 2.75V
Digital Input/Output Voltages:
ALERTB, SDA, SCL, CONTROL0, CONTROL1,
CONTROL2, CONTROL3 to GND ........... 0.3V to 3.6V
SHARE_CLK, WDI/RESETB, WP, FAULTB0,
FAULTB1 to GND .................................. 0.3V to 3.6 V
ASEL0, ASEL1 to GND .......................... 0.3V to 3.6V
Analog Voltages:
REFP ................................................... 0.3V to 1.35V
REFM to GND ........................................ 0.3V to 0.3V
V
IN_SNS
to GND...................................... 0.3V to 15V
V
SENSEP[3:0]
to GND ................................. 0.3V to 6V
V
SENSEM[3:0]
to GND ................................ 0.3V to 6V
I
SENSEP[3:0]
to GND .................................. 0.3V to 6V
I
SENSEM[3:0]
to GND ................................. 0.3V to 6V
V
OUT_EN[3:0]
, AUXFAULTB to GND .......... 0.3V to 15V
V
DAC[3:0]
to GND ...................................... 0.3V to 6V
T
SENSE[3:0]
to GND ................................ 0.3V to 3.6V
Operating Junction Temperature Range:
LTC2974C ................................................ 0C to 70C
LTC2974I .............................................. 40C to 85C
Storage Temperature Range .................. 65C to 125C
Maximum Junction Temperature ........................ 125C*
*See OPERATION section for detailed EEPROM de-
rating information for junction temperatures in excess
of 85C.
(Note 1)
orDer inForMaTion
TOP VIEW
65
GND
UP PACKAGE
64-LEAD (9mm 9mm) PLASTIC QFN
V
SENSEP0
1
V
SENSEM0
2
V
OUT_EN0
3
V
OUT_EN1
4
V
OUT_EN2
5
V
OUT_EN3
6
AUXFAULTB 7
DNC 8
V
IN_SNS
9
V
PWR
10
V
DD33
11
V
DD33
12
V
DD25
13
V
DD25
14
T
SENSE0
15
T
SENSE1
16
48 I
SENSEM3
47 I
SENSEP3
46 I
SENSEM2
45 I
SENSEP2
44 I
SENSEM1
43 I
SENSEP1
42 I
SENSEM0
41 I
SENSEP0
40 REFM
39 GND
38 REFP
37 GND
36 ASEL1
35 ASEL0
34 T
SENSE3
33 CONTROL1
6
4

V
S
E
N
S
E
M
1
6
3

V
S
E
N
S
E
P
1
6
2

V
S
E
N
S
E
M
2
6
1

V
S
E
N
S
E
P
2
6
0

N
C
5
9

N
C
5
8

V
D
A
C
3
5
7

V
D
A
C
2
5
6

N
C
5
5

N
C
5
4

V
D
A
C
1
5
3

V
D
A
C
0
5
2

N
C
5
1

N
C
5
0

V
S
E
N
S
E
M
3
4
9

V
S
E
N
S
E
P
3
P
W
R
G
D

1
7
S
H
A
R
E
_
C
L
K

1
8
G
N
D

1
9
G
N
D

2
0
G
N
D

2
1
C
O
N
T
R
O
L
2

2
2
C
O
N
T
R
O
L
3

2
3
W
D
I
/
R
E
S
E
T
B

2
4
F
A
U
L
T
B
0

2
5
F
A
U
L
T
B
1

2
6
T
S
E
N
S
E
2

2
7
W
P

2
8
S
D
A

2
9
S
C
L

3
0
A
L
E
R
T
B

3
1
C
O
N
T
R
O
L
0

3
2

T
JMAX
= 125C,
JCtop
= 7C/W,
JCbottom
= 1C/W
EXPOSED PAD (PIN 65) IS GND, MUST BE SOLDERED TO PCB
LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE
LTC2974CUP#PBF LTC2974CUP#TRPBF LTC2974UP 64-Lead (9mm 9mm) Plastic QFN 0C to 70C
LTC2974IUP#PBF LTC2974IUP#TRPBF LTC2974UP 64-Lead (9mm 9mm) Plastic QFN 40C to 85C
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
Consult LTC Marketing for information on non-standard lead based finish parts.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
LTC2974
5
2974f
elecTrical characTerisTics The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at T
J
= 25C. V
PWR
= V
IN_SNS
= 12V, V
DD33
, V
DD25
and REF pins floating, unless
otherwise indicated. C
VDD33
= 100nF, C
VDD25
= 100nF and C
REF
= 100nF.
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
Power-Supply Characteristics
V
PWR
V
PWR
Supply Input Operating Range V
DD33
Floating (Note 2) l 4.5 15 V
I
PWR
V
PWR
Supply Current 4.5V V
PWR
15V, V
DD33
Floating (Note 2) l 10 13 mA
I
VDD33
V
DD33
Supply Current 3.13V V
DD33
3.47V, V
PWR
= V
DD33
l 10 13 mA
V
UVLO_VDD33
V
DD33
Undervoltage Lockout V
DD33
Ramping Up, V
PWR
= V
DD33
l 2.25 2.55 2.8 V
V
DD33
Undervoltage Lockout
Hysteresis
120 mV
V
DD33
Supply Input Operating Range V
PWR
= V
DD33
l 3.13 3.47 V
Regulator Output Voltage 4.5V V
PWR
15V l 3.13 3.26 3.47 V
Regulator Output Short-Circuit Current V
PWR
= 4.5V, V
DD33
= 0V l 75 90 140 mA
V
DD25
Regulator Output Voltage 3.13V V
DD33
3.47V l 2.35 2.5 2.6 V
Regulator Output Short-Circuit Current V
PWR
= V
DD33
= 3.47V, V
DD25
= 0V l 30 55 80 mA
Voltage Reference Characteristics
V
REF
Output Voltage V
REF
= V
REFP
V
REFM
, 0 < I
REFP
< 100A l 1.220 1.232 1.244 V
Temperature Coefficient 3 ppm/C
Hysteresis (Note 3) 100 ppm
ADC Characteristics
V
IN_ADC
Voltage Sense Input Range Differential Voltage:
V
IN_ADC
= (V
SENSEPn
V
SENSEMn
)
l 0 6 V
Single-Ended Voltage: V
SENSEMn
l 0.1 0.1 V
Current Sense Input Range Single-Ended Voltage: I
SENSEPn
, I
SENSEMn
l 0.1 6 V
Differential Current Sense Voltage:
V
IN_ADC
= (I
SENSEPn
I
SENSEMn
)
l 170 170 mV
N_ADC Voltage Sense Resolution 0V V
IN_ADC
6V, READ_VOUT 122 V/LSB
Current Sense Resolution 0mV |V
IN_ADC
| < 16mV (Note 4)
16mV |V
IN_ADC
| < 32mV
32mV |V
IN_ADC
| < 63.9mV
63.9mV |V
IN_ADC
| < 127.9mV
127.9mV |V
IN_ADC
|
IOUT_CAL_GAIN = 1
15.625
31.25
62.5
125
250
A/LSB
A/LSB
A/LSB
A/LSB
A/LSB
TUE_ADC_
VOLT_SNS
Total Unadjusted Error Voltage Sense Inputs V
IN_ADC
1V l 0.25 %
Voltage Sense Inputs 0 V
IN_ADC
1V l 2.5 mV
TUE_ADC_
CURR_SNS
Total Unadjusted Error Current Sense Inputs 20mV V
IN_ADC

170mV
l 0.3 %
Current Sense Inputs V
IN_ADC
20mV l 60 V
V
OS_ADC
Offset Error I
SENSEPn
and I
SENSEMn
Inputs, V
OS
IOUT_
CAL_GAIN, IOUT_CAL_GAIN = 1
l 35 V
t
CONV_ADC
Conversion Time V
SENSEPn
and V
SENSEMn
Inputs (Note 5) 6.15 ms
I
SENSEPn
and I
SENSEMn
Inputs (Note 5) 24.6 ms
Internal Temperature
(READ_TEMPERATURE2) (Note 5)
24.6 ms
C
IN_ADC
Input Sampling Capacitance 1 pF
f
IN_ADC
Input Sampling Frequency 62.5 kHz
LTC2974
6
2974f
The l denotes the specifications which apply over the full operating
J
= 25C. V
PWR
= V
IN_SNS
= 12V, V
DD33
, V
DD25
VDD33
= 100nF, C
VDD25
= 100nF and C
REF
= 100nF.
I
IN_ADC
Input Leakage Current I
SENSEPn
, I
SENSEMn
,V
SENSEPn
, and V
SENSEMn

Inputs, V
IN_ADC
= 0V, 0V V
COMMONMODE
6V
l 0.5 A
Differential Input Current V
SENSEPn
, and V
SENSEMn
Inputs, V
IN_ADC
= 6V l 10 15 A
I
SENSEPn
, and I
SENSEMn
Inputs,
V
IN_ADC
= 0.17V
l 0.3 0.5 A
DAC Output Characteristics
N_V
DAC
Resolution 10 Bits
V
FS_VDAC
Full-Scale Output Voltage
(Programmable)
DAC Code = 0x3FF
DAC Polarity = 1
Buffer Gain Setting_0
Buffer Gain Setting_1
l
l
1.32
2.53
1.38
2.65
1.44
2.77
V
V
INL_V
DAC
Integral Nonlinearity (Note 6) l 2 LSB
DNL_V
DAC
Differential Nonlinearity (Note 6) l 2.4 LSB
V
OS_VDAC
Offset Voltage (Note 6) l 12 mV
V
DAC
Load Regulation V
DACn
= 2.65V, I
VDACn
Sourcing = 2mA 100 ppm/mA
V
DACn
= 0.1V, I
VDACn
Sinking = 2mA 100 ppm/mA
PSRR DC: 3.13V V
DD33
3.47V, V
PWR
= V
DD33
60 dB
Leakage Current V
DACn
Hi-Z, 0V V
DACn
6V l 100 nA
Short-Circuit Current Low V
DACn
Shorted to GND l 12 4 mA
Short-Circuit Current High V
DACn
Shorted to V
DD33
l 4 12 mA
C
OUT
Output Capacitance V
DACn
Hi-Z 10 pF
t
S_VDAC
DAC Output Update Rate Fast Servo Mode 250 s
Voltage Supervisor Characteristics
V
IN_VS
Input Voltage Range (Programmable) V
IN_VS
= (V
SENSEPn

V
SENSEMn
)
Low Resolution Mode
High Resolution Mode
l
l
0
0
6
3.8
V
V
Single-Ended Voltage: V
SENSEMn
l 0.1 0.1 V
N_VS Voltage Sensing Resolution 0V to 3.8V Range: High Resolution Mode 4 mV/LSB
0V to 6V Range: Low Resolution Mode 8 mV/LSB
TUE_VS Total Unadjusted Error 2V V
IN_VS
6V, Low Resolution Mode l 1.25 %
1.5V < V
IN_VS
3.8V, High Resolution Mode l 1.0 %
0.8V V
IN_VS
1.5V, High Resolution Mode l 1.5 %
t
S_VS
Update Rate 12.21 s
Current Supervisor Characteristics
V
IN_CS
Current Sense Input Range Single-Ended Voltage: I
SENSEPn
, I
SENSEMn
l 0.1 6 V
Differential Voltage:
V
IN_CS
= (I
SENSEPn
I
SENSEMn
)
l 170 170 mV
N_CS Current Sense Resolution IOUT_XC_FAULT_LIMIT IOUT_CAL_GAIN 400 V/LSB
TUE_CS Total Unadjusted Error 50mV V
IN_CS
170mV l 3 %
V
IN_CS
< 50mV l 1.5 mV
V
OS_CS
Offset Error |V
IN_CS
| = 0.8mV l 600 V
I
OS_CS
Differential Input Offset Current OC = Positive Full-Scale, UC = 0A, VIN_CS
= 0V
117 nA
OC = UC = Positive Full-Scale, VIN_CS = 0V 244 nA
OC = 0A, UC < 0A, VIN_CS = 0V 0 nA
t
S_CS
Update Rate 12.21 s
V
IN_SNS
Input Characteristics
V
IN_SNS
V
IN_SNS
Input Voltage Range l 0 15 V
elecTrical characTerisTics
LTC2974
7
2974f
elecTrical characTerisTics The l denotes the specifications which apply over the full operating
J
= 25C. V
PWR
= V
IN_SNS
= 12V, V
DD33
, V
DD25
VDD33
= 100nF, C
VDD25
= 100nF and C
REF
= 100nF.
R
VIN_SNS
V
IN_SNS
Input Resistance l 70 90 110 k
TUE
VIN_SNS
V
IN_ON
, V
IN_OFF
Threshold Total
Unadjusted Error
3V V
VIN_SNS
8V l 2.0 %
V
VIN_SNS
> 8V l 1.0 %
READ_V
IN
Total Unadjusted Error 3V V
VIN_SNS
8V l 1.5 %
V
VIN_SNS
> 8V l 1.0 %
DAC Soft-Connect Comparator Characteristics
V
OS_CMP
Offset Voltage l 3 18 mV
External Temperature Sensor Characteristics (READ_TEMPERATURE1)
t
CONV_TSENSE
Conversion Time For One Channel, (Total Latency For All
Channels Is 4 66ms)
66 ms
I
TSENSE_HI
T
SENSE
High Level Current l 90 64 40 A
I
TSENSE_LOW
T
SENSE
Low Level Current l 5.5 4 2.5 A
TUE_TS Total Unadjusted Error Ideal Diode Assumed l 3 C
N_TS Maximum Ideality Factor READ_TEMPERATURE_1 = 175C
MFR_TEMP1_GAIN = 1/N_TS
1.10 NA
Internal Temperature Sensor Characteristics (READ_TEMPERATURE2)
TUE_TS2 Total Unadjusted Error 1 C
V
OUT
Enable Output (V
OUT_EN
[3:0]) Characteristics
V
VOUT_ENn
Output High Voltage I
VOUT_ENn
= 5A, V
DD33
= 3.13V l 12 13 14.7 V
I
VOUT_ENn
Output Sourcing Current V
VOUT_ENn
Pull-Up Enabled, V
VOUT_ENn
= 1V l 5 7 9 A
Output Sinking Current Strong Pull-Down Enabled,
V
VOUT_ENn
= 0.4V
l 3 5 8 mA
Weak Pull-Down Enabled, V
VOUT_ENn
= 0.4V l 33 50 65 A
Output Leakage Current Internal Pull-Up Disabled,
0V V
VOUT_ENn
15V
l 1 A
General Purpose Output (AUXFAULTB) Characteristics
V
AUXFAULTB
Output High Voltage I
AUXFAULTB
= 5A, V
DD33
= 3.13V l 12 13 14.7 V
I
AUXFAULTB
Output Sourcing Current AUXFAULTB Pull-Up Enabled, V
AUXFAULTB
=
1V
l 5 7 9 A
Output Sinking Current Strong Pull-Down Enabled, V
AUXFAULTB
= 0.4V l 3 5 8 mA
Output Leakage Current Internal Pull-Up Disabled, 0V V
AUXFAULTB

15V
l 1 A
EEPROM Characteristics
Endurance (Note 7) 0C < T
J
< 85C During EEPROM Write
Operations
l 10,000 Cycles
Retention (Note 7) T
J
< 85C l 10 Years
Mass_Write Mass_Write Operation Time (Note 8) STORE_USER_ALL, 0C < T
J
< 85C During
EEPROM Write Operations
l 440 4100 ms
Digital Inputs SCL, SDA, CONTROL0, CONTROL1, CONTROL2, CONTROL3, WDI/RESETB, FAULTB0, FAULTB1, WP
V
IH
High Level Input Voltage FAULTB0, FAULTB1, SDA, SCL l 2.1 V
CONTROLn Only l 1.85 V
V
IL
Low Level Input Voltage FAULTB0, FAULTB1, SDA, SCL l 1.5 V
CONTROLn Only l 1.6 V
V
HYST
Input Hysteresis 20 mV
I
LEAK
Input Leakage Current 0V V
PIN
3.6V l 2 A
LTC2974
8
2974f
t
SP
Pulse Width of Spike Suppressed FAULTB0, FAULTB1, CONTROLn 10 s
SDA, SCL Pins Only 98 ns
t
FAULT_MIN
Minimum Low Pulse Width for
Externally Generated Faults
180 ms
t
RESETB
Pulse Width to Assert Reset V
WDI/RESETB
1.5V l 300 s
t
WDI
Pulse Width to Reset Watchdog Timer V
WDI/RESETB
1.5V l 0.3 200 s
f
WDI
Watchdog Timer Interrupt Input
Frequency
l 1 MHz
C
IN
Input Capacitance 10 pF
Digital Input SHARE_CLK
V
IH
High Level Input Voltage l 1.6 V
V
IL
Low Level Input Voltage l 0.8 V
f
SHARE_CLK_IN
Input Frequency Operating Range l 90 110 kHz
t
LOW
Assertion Low Time V
SHARE_CLK
< 0.8V l 0.825 1.11 s
t
RISE
Rise Time V
SHARE_CLK
< 0.8V to V
SHARE_CLK
> 1.6V l 450 ns
I
LEAK
Input Leakage Current 0V V
SHARE_CLK
V
DD33
+ 0.3V l 1 A
C
IN
Digital Outputs SDA, ALERTB, SHARE_CLK, FAULTB0, FAULTB1, PWRGD
V
OL
Digital Output Low Voltage I
SINK
= 3mA l 0.4 V
f
SHARE_CLK_OUT
Output Frequency Operating Range 5.49k Pull-Up to V
DD33
l 90 100 110 kHz
Digital Inputs ASEL0,ASEL1
V
IH
Input High Threshold Voltage l V
DD33
0.5 V
V
IL
Input Low Threshold Voltage l 0.5 V
I
IH,IL
High, Low Input Current ASEL[1:0] = 0, V
DD33
l 95 A
I
IH,Z
Hi-Z Input Current l 24 A
C
IN
Serial Bus Timing Characteristics
f
SCL
Serial Clock Frequency (Note 9) l 10 400 kHz
t
LOW
Serial Clock Low Period (Note 9) l 1.3 s
t
HIGH
Serial Clock High Period (Note 9) l 0.6 s
t
BUF
Bus Free Time Between Stop and Start
(Note 10)
l 1.3 s
t
HD,STA
Start Condition Hold Time (Note 9) l 600 ns
t
SU,STA
Start Condition Setup Time (Note 9) l 600 ns
t
SU,STO
Stop Condition Setup Time (Note 9) l 600 ns
t
HD,DAT
Data Hold Time (LTC2974 Receiving
Data) (Note 9)
l 0 ns
Data Hold Time (LTC2974 Transmitting
Data) (Note 9)
l 300 900 ns
t
SU,DAT
Data Setup Time (Note 9) l 100 ns
t
SP
Pulse Width of Spike Suppressed
(Note 9)
98 ns
t
TIMEOUT_BUS
Time Allowed to Complete any PMBus
Command After Which Time SDA Will
Be Released and Command Terminated
Longer Timeout = 0
Longer Timeout = 1
l
l
25
200
35
280
ms
ms
The l denotes the specifications which apply over the full operating
J
= 25C. V
PWR
= V
IN_SNS
= 12V, V
DD33
, V
DD25
VDD33
= 100nF, C
VDD25
= 100nF and C
REF
= 100nF.
LTC2974
9
2974f
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: All currents into device pins are positive. All currents out of device
pins are negative. All voltages are referenced to ground unless otherwise
specified. If power is supplied to the chip via the V
DD33
pin only, connect
V
PWR
and V
DD33
pins together.
Note 3: Hysteresis in the output voltage is created by package stress
that differs depending on whether IC was previously at a higher or lower
temperature. Output voltage is always measured at 25C, but the IC is
cycled to 85C or 40C before successive measurements. Hysteresis is
roughly proportional to the square of the temperature change.
Note 4: The current sense resolution is determined by the L11 format and
the mV units of the returned value. For example, a full-scale value of 170mV
returns a L11 value of 0xF2A8 = 680 2
2
= 170. This is the lowest range
that can represent this value without overflowing the L11 mantissa and
the resolution for 1LSB in this range is 2
2
mA = 250A. Each successively
lower range improves resolution by cutting the LSB size in half.
Note 5: The nominal time between successive ADC conversions (latency of
the ADC) for any given channel is 180ms.
Note 6: Nonlinearity is defined from the first code that is greater than or
equal to the maximum offset specification to full-scale code, 1023.
Note 7: EEPROM endurance and retention are guaranteed by design,
characterization and correlation with statistical process controls. The
minimum retention specification applies for devices whose EEPROM has
been cycled less than the minimum endurance specification.
Note 8: The LTC2974 will not acknowledge any PMBus commands,
except for MFR_COMMON, when a STORE_USER_ALL command is being
executed. See also OPERATION section.
Note 9: Maximum capacitive load, C
B
, for SCL and SDA is 400pF. Data and
clock risetime (t
r
) and falltime (t
f
) are: (20 + 0.1 C
B
) (ns) < t
r
< 300ns and
(20 + 0.1 C
B
) (ns) < t
f
< 300ns. C
B
= capacitance of one bus line in pF.
SCL and SDA external pull-up voltage, V
IO
, is 3.13V < V
IO
< 3.6V.
pMbus TiMing DiagraM
SDA
SCL
t
HD(STA)
t
HD(DAT)
t
SU(STA)
t
SU(STO)
t
SU(DAT)
t
LOW
t
HD(STA)
t
SP
t
BUF
START
CONDITION
STOP
CONDITION
REPEATED START
CONDITION
START
CONDITION
t
r
t
f
t
r
t
f
t
HIGH
2974 TD
LTC2974
10
2974f
Typical perForMance characTerisTics
ADC READ_IOUT Input Referred
Noise vs Temperature
Input Sampling Current vs
Differential Input Voltage:
Voltage Sense Inputs
Input Sampling Current vs
Differential Input Voltage: Current
Sense Inputs
ADC READ_VOUT-INL ADC READ_VOUT-DNL
ADC READ_IOUT Error
vs READ_IOUT
Reference Voltage vs
Temperature
ADC READ_VOUT ADC Total
Unadjusted Error vs Temperature
ADC READ_IOUT Input Referred
Offset Voltage vs Temperature
TEMPERATURE (C)
50
R
E
F
E
R
E
N
C
E

O
U
T
P
U
T

V
O
L
T
A
G
E

(
V
)
50 75
1.2322
1.2320
1.2318
1.2316
1.2314
1.2312
1.2310
1.2308
1.2306
1.2304
2974 G01
25 0 25 100
THREE TYPICAL PARTS
TEMPERATURE (C)
50
E
R
R
O
R

(
%
)
50 75
0.07
0.06
0.05
0.04
0.03
0.02
0.01
0.00
0.03
0.02
0.01
2974 G02
25 0 25 100
THREE TYPICAL PARTS
TEMPERATURE (C)
50
O
F
F
S
E
T

(
V
)
50 75
5
4
3
2
1
0
1
2
5
4
3
2974 G03
25 0 25 100
THREE TYPICAL PARTS
READ_VOUT (V)
0
E
R
R
O
R

(
L
S
B
s
)
6
5
4
3
2
0
1
1
2
3
4
5
2974 G04
1 2 3 4 5
122V/LSB
READ_VOUT (V)
0
E
R
R
O
R

(
L
S
B
s
)
6
5
4
3
2
0
1
1
2
3
4
5
2974 G05
1 2 3 4 5
122V/LSB
0.001 0.01 10 100 1 0.1
READ_IOUT (A)
R
E
A
D
_
I
O
U
T

E
R
R
O
R

(
m
A
)
75
50
25
0
25
50
75
2974 G06
IOUT_CAL_GAIN = 2.1875m
DIFFERENTIAL INPUT VOLTAGE (V)
0
D
I
F
F
E
R
E
N
T
I
A
L

I
N
P
U
T

C
U
R
R
E
N
T

(
m
A
)
4 5
7
6
5
4
3
2
1
0
2974 G08
1 2 3 6
TEMPERATURE (C)
50
N
O
I
S
E

(
V
R
M
S
)
50 75
4.50
4.25
4.00
3.75
3.50
3.25
3.00
2.75
2.50
2974 G07
25 0 25 100
DIFFERENTIAL INPUT VOLTAGE (mV)
0
D
I
F
F
E
R
E
N
T
I
A
L

I
N
P
U
T

C
U
R
R
E
N
T

(
n
A
)
100 150 125
400
350
300
250
200
150
50
100
0
2974 G09
25 50 75 175
V
CM
= 2.5V
LTC2974
11
2974f
Voltage Supervisor Total
Current Supervisor Total
DAC Full-Scale Voltage vs
Temperature, Gain = 0
DAC-INL DAC-DNL
V
DD33
Regulator Output Voltage
vs Temperature
DAC Full-Scale Voltage vs
DAC Offset Voltage vs
DAC Offset Voltage vs
TEMPERATURE (C)
50
S
U
P
E
R
V
I
S
O
R

E
R
R
O
R

(
%
)
50 75
0.25
0.20
0.15
0.10
0.05
0
0.05
0.10
0.15
0.20
2974 G10
25 0 25 100
THREE TYPICAL PARTS
HIGH RES MODE
V
IN
= 1.5V
TEMPERATURE (C)
50
D
A
C

O
U
T
P
U
T

V
O
L
T
A
G
E

(
V
)
50 75
1.405
1.400
1.395
1.390
1.385
1.380
1.375
1.370
1.365
1.360
2974 G12
25 0 25 100
THREE TYPICAL PARTS
GAIN SETTING = 0
TEMPERATURE (C)
50
O
U
T
P
U
T

V
O
L
T
A
G
E

(
V
)
50 75
3.285
3.280
3.275
3.270
3.265
3.260
3.255
3.250
3.245
3.240
2974 G18
25 0 25 100
THREE TYPICAL PARTS
TEMPERATURE (C)
50
D
A
C

O
U
T
P
U
T

V
O
L
T
A
G
E

(
V
)
50 75
2.70
2.69
2.68
2.67
2.66
2.65
2.64
2.63
2.62
2974 G13
25 0 25 100
THREE TYPICAL PARTS
GAIN SETTING = 1
DAC CODE
0
E
R
R
O
R

(
L
S
B
s
)
1.00
0.75
0.50
0.25
0
0.25
0.50
0.75
1.00
768
2974 G16
256 512 1024
DAC CODE
0
E
R
R
O
R

(
L
S
B
s
)
1.00
0.75
0.50
0.25
0
0.25
0.50
0.75
1.00
768
2974 G17
256 512 1024
TEMPERATURE (C)
50
D
A
C

O
U
T
P
U
T

V
O
L
T
A
G
E

(
V
)
50 75
0.0025
0.0020
0.0015
0.0010
0.0005
0
2974 G14
25 0 25 100
THREE TYPICAL PARTS
GAIN SETTING = 0
TEMPERATURE (C)
50
D
A
C

O
U
T
P
U
T

V
O
L
T
A
G
E

(
V
)
50 75
0.0040
0.0030
0.0025
0.0035
0.0020
0.0015
0.0010
0.0005
0
2974 G15
25 0 25 100
THREE TYPICAL PARTS
GAIN SETTING = 1
TEMPERATURE (C)
50
S
U
P
E
R
V
I
S
O
R

E
R
R
O
R

(
%
)
50 75
2974 G11
25 0 25 100
50mV
20mV
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
LTC2974
12
2974f
PWRGD and FAULTBn V
OL
vs
Current Sinking
External Temperature READ_
TEMPERATURE_1 Error vs
Temperature
ALERTB V
OL
vs Current Sinking
READ_TEMPERATURE_2 Error vs
Temperature
V
DD33
Regulator Load Regulation
V
VOUT_ENn
and V
AUXFAULTB
Output
V
OH
vs Current Sourcing
V
VOUT_ENn
and V
AUXFAULTB
Output
V
OL
vs Current Sinking
LOAD CURRENT SOURCING (mA)
0
O
U
T
P
U
T

V
O
L
T
A
G
E

D
E
L
T
A

(
p
p
m
)
30 40
0
1000
2000
3000
4000
2974 G19
10 20 50
CURRENT SOURCING (A)
0
O
U
T
P
U
T

H
I
G
H

V
O
L
T
A
G
E

(
V
)
4 5
14.0
13.5
13.0
12.5
12.0
11.5
11.0
10.5
10.0
9.5
9.0
2974 G20
1 2 3 8 7 6
25C
85C
40C
CURRENT SINKING (mA)
0
1.4
1.2
1.0
0.8
85C
40C
0.6
0.4
0.2
0
6 10
2974 G21
2 4 8 12
V
O
L

(
V
)
25C
0
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
15
2974 G22
5 10 20
V
O
L

(
V
)
85C
25C
40C
TEMPERATURE (C)
50
E
R
R
O
R

(
%
)
50 75
1.00
0.50
0.25
0.75
0
0.25
0.50
0.75
1.00
2974 G24
25 0 25 100
THREE TYPICAL PARTS
MMBT3906 DIODE CONNECTED BJTS
MFR_TEMP_1_GAIN_ADJ = 0.987
MFR_EXT_TEMP_1_ADC_OFF = 2C
TEMPERATURE (C)
50
E
R
R
O
R

(
%
)
50 75
1.00
0.50
0.25
0.75
0
0.25
0.50
0.75
1.00
2974 G25
25 0 25 100
THREE TYPICAL PARTS
V
DD33
= V
PWR
= 3.3V
0
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
2974 G23
5 10 15
V
O
L

(
V
)
85C
25C
40C
LTC2974
13
2974f
pin FuncTions
PIN NAME PIN NUMBER PIN TYPE DESCRIPTION
V
SENSEP0
1* In DC/DC Converter Differential (+) Output Voltage-0 Sensing Pin
V
SENSEM0
2* In DC/DC Converter Differential () Output Voltage-0 Sensing Pin
V
OUT_EN0
3 Out DC/DC Converter Enable-0 Pin. Output High Voltage Optionally Pulled-Up to 12V by 5A
V
OUT_EN1
V
OUT_EN2
V
OUT_EN3
AUXFAULTB 7 Out Auxillary Fault Output Pin. Output High Voltage Optionally Pulled-Up to 12V by 5A. Can Be
Configured to Pull Low When OV/UV/OC/UC Detected
DNC 8 Do Not Connect Do Not Connect to this Pin
V
IN_SNS
9 In V
IN
SENSE Input. This Voltage is Compared Against the V
IN
On and Off Voltage Thresholds In Order to
Determine When to Enable and Disable, Respectively, the Downstream DC/DC Converters
V
PWR
10 In V
PWR
Serves as the Unregulated Power Supply Input to the Chip (4.5 to 15V). If a 4.5V to 15V Supply
Voltage Is Unavailable, Short V
PWR
to V
DD33
and Power the Chip Directly from a 3.3V Supply. Bypass
to GND with 0.1F Capacitor.
V
DD33
11 In/Out If Shorted to V
PWR
, It Serves as 3.13 to 3.47V Supply Input Pin. Otherwise It Is a 3.3V Internally
Regulated Voltage Output (Use 100nF Decoupling Capacitor to GND)
V
DD33
12 In Input for Internal 2.5V Sub-Regulator. Short this Pin to Pin 11
V
DD25
13 In/Out 2.5V Internally Regulated Voltage Output. Bypass to GND with a 0.1F Capacitor
V
DD25
14 In 2.5V Supply Voltage Input. Short this Pin to Pin 13
T
SENSE0
15 In/Out External Temperature Current Output and Voltage Input for Channel 0. Maximum allowed capacitance
is 1F
T
SENSE1
is 1F
PWRGD 17 Out Power-Good Open Drain Output. Indicates When Selected Outputs Are Power Good. Can be Used as
System Power-on Reset
SHARE_CLK 18 In/Out Bidirectional Clock Sharing Pin. Connect a 5.49k Pull-Up Resistor to V
DD33
GND 19 Ground Chip Ground. Must Be Soldered to PCB
CONTROL2 22 In Control Pin 2 Input
WDI/RESETB 24 In Watchdog Timer Interrupt and Chip Reset Input. Connect a 10k Pull-Up Resistor to V
DD33
. Rising
Edge Resets Watchdog Counter. Holding this Pin Low for More than t
RESETB
Resets the Chip
FAULTB0 25 In/Out Open-Drain Output and Digital Input. Active Low Bidirectional Fault Indicator-0. Connect a 10k
Pull-Up Resistor to V
DD33
FAULTB1 26 In/Out Open-Drain Output and Digital Input. Active Low Bidirectional Fault Indicator-1. Connect a 10k
Pull-Up Resistor to V
DD33
T
SENSE2
is 1F
WP 28 In Digital Input. Write-Protect Input Pin, Active High
SDA 29 In/Out PMBus Bidirectional Serial Data Pin
SCL 30 In PMBus Serial Clock Input Pin (400kHz Maximum)
ALERTB 31 Out Open-Drain Output. Generates an Interrupt Request in a Fault/Warning Situation
LTC2974
14
2974f
PIN NAME PIN NUMBER PIN TYPE DESCRIPTION
T
SENSE3
is 1F
ASEL0 35 In Ternary Address Select Pin 0 Input. Connect to V
DD33
, GND or Float to Encode 1 of 3 Logic States
ASEL1 36 In Ternary Address Select Pin 1 Input. Connect to V
DD33
, GND or Float to Encode 1 of 3 Logic States
REFP 38 Out Reference Voltage Output. Needs 0.1F Decoupling Capacitor to REFM
REFM 40 Out Reference Return Pin. Needs 0.1F Decoupling Capacitor to REFP
I
SENSEP0
41* In DC/DC Converter Differential (+) Output Current-0 Sensing Pin
I
SENSEM0
42* In DC/DC Converter Differential () Output Current-0 Sensing Pin
I
SENSEP1
I
SENSEM1
I
SENSEP2
I
SENSEM2
I
SENSEP3
I
SENSEM3
V
SENSEP3
V
SENSEM3
NC 51 No Connect No Connect
V
DAC0
53 Out DAC0 Output
V
DAC1
54 Out DAC1 Output
V
DAC2
57 Out DAC2 Output
V
DAC3
58 Out DAC3 Output
V
SENSEP2
V
SENSEM2
V
SENSEP1
V
SENSEM1
GND 65 Ground Exposed Pad. Must Be Soldered to PCB
*Any unused V
SENSEPn
/I
SENSEPn
, V
SENSEMn
/I
SENSEMn
or T
SENSEn
pins must be tied to GND.
pin FuncTions
LTC2974
15
2974f
block DiagraM
10
3.3V REGULATOR
INTERNAL
TEMP
SENSOR
REFERENCE
1.232V
(TYP)
MASKING
CLOCK
GENERATION
OSCILLATOR
UVLO PORB
V
DD
EXTERNAL
TEMPERATURE
SENSOR
EEPROM
RAM
ADC_RESULTS
MONITOR LIMITS
SERVO TARGETS
PMBus
INTERFACE
(400kHz I
2
C
COMPATIBLE)
CONTROLLER
PMBus ALGORITHM
FAULT PROCESSOR
WATCHDOG
SEQUENCER
V
IN
V
DD33
V
SENSEM0
V
SENSEP0
V
OUT
V
PWR
12
2.5V REGULATOR
V
IN
V
OUT
V
DD33(IN)
1
2
V
DAC0
V
DAC1
V
DAC2
V
DAC3
NC
NC
NC
NC
NC
NC
PAGE 0
PAGE 1
PAGE 2
PAGE 3
3 V
OUT_EN0
4 V
OUT_EN1
5 V
OUT_EN2
6 V
OUT_EN3
15 T
SENSE0
16 T
SENSE1
27 T
SENSE2
34 T
SENSE3
2974 BD
7 AUXFAULTB
13 V
DD25(OUT)
14 V
DD25(IN)
V
DD25
19 GND
20 GND
21 GND
37 GND
39 GND
65 GND
31 ALERTB
30 SCL
29 SDA
35 ASEL0
36 ASEL1
28 WP
23 CONTROL3
17 PWRGD
SHARE_CLK 18
24 WDI/RESETB
25 FAULTB0
26 FAULTB1
32 CONTROL0
33
22 CONTROL2
CONTROL1
11 V
DD33(OUT)
9 V
IN_SNS
8 DNC
REFP
REFM
3R
R
20
I
SENSEP0
I
SENSEM0
V
SENSEM1
V
SENSEP1
I
SENSEP1
I
SENSEM1
V
SENSEM2
V
SENSEP2
I
SENSEP2
I
SENSEM2
V
SENSEM3
V
SENSEP3
I
SENSEP3
I
SENSEM3
16-BIT
ADC
ADC
CLOCKS
V
DD33
+
38
40
10-BIT
VDAC
+
+
+
SC
CMP0
VCMP0
VBUF0
DAC0
10 BITS
41
42
63
64
43
44
61
62
45
46
49
50
53
54
57
58
51
52
55
56
59
60
V
SENSEM0
V
SENSEP0
I
SENSEP0
I
SENSEM0
V
SENSEM1
V
SENSEP1
I
SENSEP1
I
SENSEM1
V
SENSEM2
V
SENSEP2
I
SENSEP2
I
SENSEM2
V
SENSEM3
V
SENSEP3
I
SENSEP3
48 I
SENSEM3
47
MUX
+
10-BIT
VDAC
+
+
ICMP0
LTC2974
16
2974f
operaTion
LTC2974 OPERATION OVERVIEW
The LTC2974 is a PMBus programmable power supply
controller, monitor, sequencer and voltage and current
supervisor that can perform the following operations:
Accept PMBus compatible programming commands.
Provide DC/DC converter input voltage, output voltage,
output current, output temperature, and internal junction
temperature read back through the PMBus interface.
Control the output of DC/DC converters that set the
output voltage with a trim pin or DC/DC converters
that set the output voltage using an external resistor
feedback network.
Sequence the startup of DC/DC converters via PMBus
programming and the CONTROL input pins. The LTC
2974 supports time-based sequencing and tracking
sequencing. Cascade sequence on with time based
sequence off is also supported.
Trim the DC/DC converter output voltage (typically in
0.02% steps), in closed-loop servo operating mode,
autonomously or through PMBus programming.
Margin the DC/DC converter output voltage to PMBus
programmed limits.
Allow the user to trim or margin the DC/DC converter
output voltage in a manual operating mode by providing
direct access to the margin DAC.
Supervise the DC/DC converter input voltage, output
voltage, load current and the inductor temperatures
for overvalue/undervalue conditions with respect to
PMBus programmed limits and generate appropriate
faults and warnings.
Accurately handle inductor self heating transients using
a proprietary algorithm. These self heating effects are
combined with external temperature sensor readings
to improve accuracy of current supervisors and ADC
current measurement.
Respond to a fault condition by continuing operation
indefinitely, latching-off after a programmable deglitch
period, latching-off immediately or sequencing off after
TOFF_DELAY. A retry mode may be used to automatically
recover from a latched-off condition. When enabled, the
number of retries (0 to 6 or infinite) is the same for all
pages and is programmed in MFR_RETRY_COUNT.
Optionally stop trimming the DC/DC converter output
voltage after it reaches the initial margin or nominal
target. Optionally allow servo to resume if target drifts
outside of V
OUT
warning limits.
Store command register contents with CRC to EEPROM
through PMBus programming.
Restore EEPROM contents through PMBus program-
ming or when V
CC
is applied on power-up.
Report the DC/DC converter output voltage status
through the power good output.
Generate interrupt requests by asserting the ALERTB pin
in response to supported PMBus faults and warnings.
Coordinate system wide fault responses for all DC/DC
converters connected to the LTC2974 FAULTB0 and
FAULTB1 pins.
Synchronize sequencing delays or shutdown for multiple
devices using the SHARE_CLK pin.
Software and hardware write protect the command
registers.
Disable the input voltage to the supervised DC/DC
converters in response to output OV, UV, OC and UC
faults.
Log telemetry and status data to EEPROM in response
to a faulted-off condition.
Supervise an external microcontrollers activity for a
stalled condition with a programmable watchdog timer
and reset it if necessary.
Prevent a DC/DC converter from re-entering the on
state after a power cycle until a programmable interval
(MFR_RESTART_DELAY) has elapsed and its output
has decayed below a programmable threshold voltage
(MFR_VOUT_DISCHARGE_THRESHOLD).
Record minimum and maximum observed values of
input voltage, output voltages, output currents and
output temperatures.
Access user EEPROM data directly, without alter-
ing RAM space (Mfr_ee_unlock, Mfr_ee_erase, and
Mfr_ee_data). Facilitates in house bulk programming.
LTC2974
17
2974f
operaTion
Figure 1: AUXFAULTB MUX
AUXFAULTB
2974 F01
FAST
PULL-DOWN
OV/UV/OC/UC
(MASKABLE)
OFF_THEN_ON
OR
FAULT_RETRY
FOR ANY CHANNEL
PMBUS
COMMAND
fault_seen
WEAK 12V PULL-UP
HI-Z
RESET
SET
Q
EEPROM
The LTC2974 contains internal EEPROM (Non-Volatile
Memory) to store configuration settings and fault log
information. EEPROM endurance, retention and mass
write operation time are specified over the operating tem-
perature range. See Electrical Characteristics and Absolute
Maximum Ratings sections.
Non destructive operation above T
J
= 85C is possible
although the Electrical Characteristics are not guaranteed
and the EEPROM will be degraded.
Operating the EEPROM above 85C may result in a deg-
radation of retention characteristics. The fault logging
function, which is useful in debugging system problems
that may occur at high temperatures, only writes to fault
log EEPROM locations. If occasional writes to these reg-
isters occur above 85C, a slight degradation in the data
retention characteristics of the fault log may occur.
It is recommended that the EEPROM not be written using
STORE_USER_ALL or bulk programming when T
J
> 85C.
The degradation in EEPROM retention for temperatures
>85C can be approximated by calculating the dimension-
less acceleration factor using the following equation.

AF e
Ea
k
j
(
,
\
,
(

1
T
USE
+273
1
T
STRESS
+273
j
(
,
\
,
(
,
,
,
]
]
]
]
Where:
AF = acceleration factor
Ea = activation energy = 1.4eV
k = 8.625 10
5
eV/K
T
USE
= 85C specified junction temperature
T
STRESS
= actual junction temperature C
Example: Calculate the effect on retention when operating
at a junction temperature of 95C for 10 hours.
T
STRESS
= 95C
T
USE
= 85C
AF = 3.4
Equivalent operating time at 85C = 34 hours.
So the overall rentention of the EEPROM was degraded by
34 hours as a result of operation at a junction temperature
of 95C for 10 hours. Note that the effect of this overstress
is negligible when compared to the overall EEPROM
rentention rating of 87,600 hours at a maximum junction
temperature of 85C.
AUXFAULTB
The AUXFAULTB pin can be commanded to one of two
output levels at any time via the PMBUS. If desired, the
AUXFAULTB pin can also be configured to indicate when
some fault conditions have been detected, using a third
output level. See Figure 1 for a conceptual view of this
multiplexing.
The MFR_CONFIG2_LTC2974 and MFR_CONFIG3_
LTC2974 commands can be used on a per channel basis
to select which, if any, fault conditions will cause the
AUXFAULTB pin to be driven to its third output level (fast
pull-down to GND). The only fault types which can be
propagated to the AUXFAULTB pin are over/under voltage
faults and over/under current faults.
Mfr_config_all_auxfaultb_wpu selects whether the
AUXFAULTB pin is in the hi-Z state, or weakly pulled-up
to approximately 12V, using a 5A current. As shown in
Figure 1, the pulldown to GND overrides if any enabled
faults are detected.
LTC2974
18
2974f
operaTion
RESETB
Holding the WDI/RESETB pin low for more than t
RESETB

will cause the LTC2974 to enter the power-on reset state.
Following the subsequent rising-edge of the WDI/RESETB
pin, the LTC2974 will execute its power-on sequence per
the user configuration stored in EEPROM.
PMBus SERIAL DIGITAL INTERFACE
The LTC2974 communicates with a host (master) using the
standard PMBus serial bus interface. The PMBus Timing
Diagram shows the timing relationship of the signals on
the bus. The two bus lines, SDA and SCL, must be high
when the bus is not in use. External pull-up resistors or
current sources are required on these lines.
The LTC2974 is a slave device. The master can communicate
with the LTC2974 using the following formats:
Master transmitter, slave receiver
Master receiver, slave transmitter
The following SMBus commands are supported:
Write Byte, Write Word, Send Byte
Read Byte, Read Word, Block Read
Alert Response Address
Figures 1 to 12 illustrate the aforementioned SMBus proto-
cols. All transactions support PEC (parity error check) and
GCP (group command protocol). The Block Read supports
255 bytes of returned data. For this reason, the SMBus
timeout may be extended using the Mfr_config_all_lon-
ger_pmbus_timeout setting.
PMBus
PMBus is an industry standard that defines a means
of communication with power conversion devices. It is
comprised of an industry standard SMBus serial interface
and the PMBus command language.
The PMBus two wire interface is an incremental extension
of the SMBus. SMBus is built upon I
2
C with some minor
differences in timing, DC parameters and protocol. The
SMBus protocols are more robust than simple I
2
C byte
commands because they provide timeouts to prevent
bus hangs and optional Packet Error Checking (PEC) to
ensure data integrity. In general, a master device that
can be configured for I
2
C communication can be used
for PMBus communication with little or no change to
hardware or firmware.
For a description of the minor extensions and exceptions
PMBus makes to SMBus, refer to PMBus Specification Part
1 Revision 1.1: Section 5: Transport. This can be found at:
www.pmbus.org
For a description of the differences between SMBus and I
2
C,
refer to System Management Bus (SMBus) Specification
Version 2.0: Appendix B Differences between SMBus
and I
2
C. This can be found at:
www.smbus.org
When using an I
2
C controller to communicate with a PMBus
part it is important that the controller be able to write a
byte of data without generating a stop. This will allow the
controller to properly form the repeated start of a PMBus
read command by concatenating a start command byte
write with an I
2
C read.
Device Address
The I
2
C/SMBus address of the LTC2974 equals the base
address + N where N is a number from 0 to 8. N can be
configured by setting the ASEL0 and ASEL1 pins to V
DD33
,
GND or FLOAT. See Table 1. Using one base address and
the nine values of N, nine LTC2974s can be connected
together to control thirty six outputs. The base address is
stored in the MFR_I2C_BASE_ADDRESS register. The base
address can be written to any value, but generally should
not be changed unless the desired range of addresses
overlap existing addresses. Watch that the address range
does not overlap with other I
2
C/SMBus device or global
addresses, including I
2
C/SMBus multiplexers and bus
buffers. This will bring you great happiness.
The LTC2974 always responds to its global address and the
SMBus Alert Response address regardless of the state of
its ASEL pins and the MFR_I2C_BASE_ADDRESS register.
LTC2974
19
2974f
operaTion
Processing Commands
The LTC2974 uses a dedicated processing block to ensure
quick response to all of its commands. There are a few
exceptions where the part will NACK a subsequent com-
mand because it is still processing the previous command.
EEPROM Related Commands
COMMAND TYPICAL DELAY* COMMENT
STORE_USER_ALL Mass_write See Electrical Characterization table. The LTC2974 will not accept any commands while it is transferring
register contents to the EEPROM. The command byte will be NACKed. Mfr_common may always be read.
RESTORE_USER_ALL 10ms The LTC2974 will not accept any commands while it is transferring EEPROM data to command registers.
The command byte will be NACKed. Mfr_common may always be read.
MFR_FAULT_LOG_CLEAR 150ms The LTC2974 will not accept any commands while it is initializing the fault log EEPROM space. The
command byte will be NACKed. Mfr_common may always be read.
MFR_FAULT_LOG_STORE 10ms The LTC2974 will not accept any commands while it is transferring fault log RAM buffer to EEPROM
space. The command byte will be NACKed. Mfr_common may always be read.
Internal Fault log 10ms An internal fault log event is a one time event that uploads the contents of the fault log to EEPROM in
response to a fault. Internal fault logging may be disabled. Commands received during this EEPROM
write are NACKed. Mfr_common may always be read.
MFR_FAULT_LOG_RESTORE 2ms The LTC2974 will not accept any commands while it is transferring EEPROM data to the fault log RAM
buffer. The command byte will be NACKed. Mfr_common may always be read.
*The typical delay is measured from the commands stop to the next commands start.
These are summarized in the following tables. Mfr_com-
mon is a special command that may always be read even
when the part is busy. This provides an alternate method
for a host to determine if the LTC2974 is busy.
Other Commands
COMMAND DELAY* COMMENT
MFR_CONFIG <50s The LTC2974 will not accept any commands while it is completing this command. The command byte
will be NACKed. Mfr_common may always be read.
IOUT_CAL_GAIN <500s The LTC2974 will not accept any commands while it is completing this command. The command byte
will be NACKed. Mfr_common may always be read.
*The delay is measured from the commands stop to the next commands start.
Other PMBus Timing Notes
COMMAND COMMENT
CLEAR_FAULTS The LTC2974 will accept commands while it is completing this command but the affected status flags will not be cleared for
up to 500s.
LTC2974
20
2974f
Table 1. LTC2974 Address Look-Up Table with MFR_I2C_BASE_ADDRESS Set to 7bit 0x5C
DESCRIPTION
HEX DEVICE
ADDRESS BINARY DEVICE ADDRESS ADDRESS PINS
7-Bit 8-Bit 6 5 4 3 2 1 0 R/W ASEL1 ASEL0
Alert Response 0C 19 0 0 0 1 1 0 0 1 X X
Global 5B B6 1 0 1 1 0 1 1 0 X X
N = 0 5C* B8 1 0 1 1 1 0 0 0 L L
N = 1 5D BA 1 0 1 1 1 0 1 0 L NC
N = 2 5E BC 1 0 1 1 1 1 0 0 L H
N = 3 5F BE 1 0 1 1 1 1 1 0 NC L
N = 4 60 C0 1 1 0 0 0 0 0 0 NC NC
N = 5 61 C2 1 1 0 0 0 0 1 0 NC H
N = 6 62 C4 1 1 0 0 0 1 0 0 H L
N = 7 63 C6 1 1 0 0 0 1 1 0 H NC
N = 8 64 C8 1 1 0 0 1 0 0 0 H H
H = Tie to V
DD33
, NC = No Connect = Open or Float, L = Tie to GND, X = Dont Care
*MFR_I2C_BASE_ADDRESS = 7bit 0x5C (Factory Default)
operaTion
SLAVE ADDRESS COMMAND CODE DATA BYTE Wr A A A P
2974 F03
S
7 8 8 1 1 1 1 1 1
SLAVE ADDRESS COMMAND CODE DATA BYTE LOW Wr A A A P
2974 F04
S
7 8 8 1
DATA BYTE HIGH
8 1 1 1 1 1 1
A
SLAVE ADDRESS COMMAND CODE DATA BYTE Wr A A A P
2974 F05
S
7 8 8 1
PEC
8 1 1 1 1 1 1
A
Figure 3. Write Byte Protocol
Figure 2. PMBus Packet Protocol Diagram Element Key
Figure 4. Write Word Protocol
Figure 5. Write Byte Protocol with PEC
SLAVE ADDRESS DATA BYTE Wr A A P
2974 F02
S
7
S START CONDITION
Sr REPEATED START CONDITION
Rd READ (BIT VALUE OF 1)
Wr WRITE (BIT VALUE OF 0)
x SHOWN UNDER A FIELD INDICATES THAT THAT
FIELD IS REQUIRED TO HAVE THE VALUE OF x
A ACKNOWLEDGE (THIS BIT POSITION MAY BE 0
FOR AN ACK OR 1 FOR A NACK)
P STOP CONDITION
PEC PACKET ERROR CODE
MASTER TO SLAVE
SLAVE TO MASTER
CONTINUATION OF PROTOCOL
8 1 1 1
x x
1 1
...
LTC2974
21
2974f
SLAVE ADDRESS COMMAND CODE DATA BYTE LOW Wr A A A P
2974 F06
S
7 8 8 1
DATA BYTE HIGH
8
PEC
8 1 1 1 1 1 1 1
A A
Figure 6. Write Word Protocol with PEC
SLAVE ADDRESS Wr A A P
2974 F07
S
7 8 1 1 1 1 1
COMMAND CODE
Figure 7. Send Byte Protocol
operaTion
SLAVE ADDRESS COMMAND CODE PEC Wr A A A P
2974 F08
S
7 8 8 1 1 1 1 1 1
Figure 8. Send Byte Protocol with PEC
SLAVE ADDRESS COMMAND CODE SLAVE ADDRESS Wr A A S
7 8 7 1
BYTE COUNT = N
8 1 1 1 1
Sr
1 1
A
1
Rd A
A P
2974 F13
DATA BYTE N
8 1 1
1
A DATA BYTE 1
8
DATA BYTE 2
8 1 1
A
SLAVE ADDRESS COMMAND CODE SLAVE ADDRESS Wr A A A P
2974 F09
S
7 8 7 1
DATA BYTE LOW
8
DATA BYTE HIGH
8 1 1 1 1
Sr
1 1 1 1
A
1
Rd A
1
SLAVE ADDRESS COMMAND CODE SLAVE ADDRESS Wr A A A P A
2974 F10
S
7 8 7 1
DATA BYTE LOW
8
DATA BYTE HIGH PEC
8 8 1 1 1 1 1
1
1 1 1
Sr
1
A
1
Rd A
SLAVE ADDRESS COMMAND CODE SLAVE ADDRESS Wr A A Sr P
2974 F11
S
7 8 7 1 1
DATA BYTE
8 1
1
1 1 1 1 1 1
A Rd A
SLAVE ADDRESS COMMAND CODE SLAVE ADDRESS Wr A A Sr P
2974 F12
S
7 8 7 1 1
DATA BYTE
8 1
1
1 1 1 1 1 1
A Rd A
1
A PEC
Figure 12. Read Byte Protocol with PEC
Figure 9. Read Word Protocol
Figure 10. Read Word Protocol with PEC
Figure 11. Read Byte Protocol
Figure 13. Block Read
A P
2974 F14
PEC
8 1 1
1
SLAVE ADDRESS COMMAND CODE SLAVE ADDRESS Wr A A S
7 8 7 1
BYTE COUNT = N
8 1 1 1 1
Sr
1 1
A
1
Rd A
A DATA BYTE N
8 1
A DATA BYTE 1
8
DATA BYTE 2
8 1 1
A
Figure 14. Block Read with PEC
LTC2974
22
2974f
Summary Table
COMMAND NAME
CMD
CODE DESCRIPTION TYPE PAGED
DATA
FORMAT UNITS NVM
DEFAULT
VALUE:
FLOAT
HEX
REF
PAGE
PAGE 0x00 Channel or page currently selected for any
command that supports paging.
R/W Byte N Reg 0x00 28
OPERATION 0x01 Operating mode control. On/Off, Margin High
and Margin Low.
R/W Byte Y Reg Y 0x00 30
ON_OFF_CONFIG 0x02 CONTROL pin and PMBus on/off command
setting.
CLEAR_FAULTS 0x03 Clear any fault bits that have been set. Send Byte Y NA 61
WRITE_PROTECT 0x10 Level of protection provided by the device
against accidental changes.
R/W Byte N Reg Y 0x00 28
STORE_USER_ALL 0x15 Store entire operating memory to EEPROM. Send Byte N NA 40
RESTORE_USER_ALL 0x16 Restore entire operating memory from
EEPROM.
Send Byte N NA 40
CAPABILITY 0x19 Summary of PMBus optional communication
protocols supported by this device.
R Byte N Reg 0xB0 78
VOUT_MODE 0x20 Output voltage data format and mantissa
exponent (2
13
).
R Byte Y Reg 0x13 44
VOUT_COMMAND 0x21 Servo target. Nominal DC/DC converter
output voltage setpoint.
R/W Word Y L16 V Y 1.0
0x2000
44
VOUT_MAX 0x24 Upper limit on the output voltage the unit
can command regardless of any other
commands.
0x8000
44
VOUT_MARGIN_HIGH 0x25 Margin high DC/DC converter output voltage
setting.
0x219A
44
VOUT_MARGIN_LOW 0x26 Margin low DC/DC converter output voltage
setting.
0x1E66
44
VIN_ON 0x35 Input voltage above which power conversion
can be enabled.
R/W Word N L11 V Y 10.0
0xD280
43
VIN_OFF 0x36 Input voltage below which power conversion
is disabled. All V
OUT_EN
pins go off
immediately or sequence off after TOFF_
DELAY (See Mfr_config_track_enn).
0xD240
43
IOUT_CAL_GAIN 0x38 The nominal resistance of the current sense
element in m.
R/W Word Y L11 m Y 1.0
0xBA00
46
VOUT_OV_FAULT_LIMIT 0x40 Output overvoltage fault limit. R/W Word Y L16 V Y 1.1
0x2333
44
VOUT_OV_FAULT_RESPONSE 0x41 Action to be taken by the device when an
output overvoltage fault is detected.
VOUT_OV_WARN_LIMIT 0x42 Output overvoltage warning limit. R/W Word Y L16 V Y 1.075
0x2266
44
VOUT_UV_WARN_LIMIT 0x43 Output undervoltage warning limit. R/W Word Y L16 V Y 0.925
0x1D9A
44
VOUT_UV_FAULT_LIMIT 0x44 Output undervoltage fault limit. Used for
Ton_max_fault and power good de-assertion.
0x1CCD
44
pMbus coMManD suMMary
Note: The data format abbreviations are detailed at the end of this table
LTC2974
23
2974f
Summary Table
COMMAND NAME
CMD
DATA
FORMAT UNITS NVM
DEFAULT
VALUE:
FLOAT
HEX
REF
PAGE
VOUT_UV_FAULT_RESPONSE 0x45 Action to be taken by the device when an
output undervoltage fault is detected.
R/W Byte Y Reg Y 0x7F 54
IOUT_OC_FAULT_LIMIT 0x46 Output overcurrent fault limit. R/W Word Y L11 A Y 10.0
0xD280
46
IOUT_OC_FAULT_RESPONSE 0x47 Action to be taken by the device when an
output overcurrent fault is detected.
IOUT_OC_WARN_LIMIT 0x4A Output overcurrent warning limit. R/W Word Y L11 A Y 5.0
0xCA80
46
IOUT_UC_FAULT_LIMIT 0x4B Output undercurrent fault limit. Used to
detect a reverse current and must be a
negative value.
R/W Word Y L11 A Y -1.0
0xBE00
46
IOUT_UC_FAULT_RESPONSE 0x4C Action to be taken by the device when an
output undercurrent fault is detected.
OT_FAULT_LIMIT 0x4F Overtemperature fault limit setting for the
external temperature sensor.
R/W Word Y L11 C Y 65.0
0xEA08
48
OT_FAULT_RESPONSE 0x50 Action to be taken by the device when an
overtemperature fault is detected on the
R/W Byte Y Reg Y 0xB8 54
OT_WARN_LIMIT 0x51 Overtemperature warning limit for the
external temperature sensor
0xE3C0
48
UT_WARN_LIMIT 0x52 Undertemperature warning limit for the
R/W Word Y L11 C Y 0
0x8000
48
UT_FAULT_LIMIT 0x53 Undertemperature fault limit for the external
temperature sensor.
0xCD80
48
UT_FAULT_RESPONSE 0x54 Action to be taken by the device when an
undertemperature fault is detected on the
VIN_OV_FAULT_LIMIT 0x55 Input overvoltage fault limit measured at
VIN_SNS pin.
0xD3C0
43
VIN_OV_FAULT_RESPONSE 0x56 Action to be taken by the device when an
input overvoltage fault is detected.
VIN_OV_WARN_LIMIT 0x57 Input overvoltage warning limit measured at
VIN_SNS pin.
0xD380
43
VIN_UV_WARN_LIMIT 0x58 Input undervoltage warning limit measured
at VIN_SNS pin.
R/W Word N L11 V Y 0
0x8000
43
VIN_UV_FAULT_LIMIT 0x59 Input undervoltage fault limit measured at
VIN_SNS pin.
0x8000
43
VIN_UV_FAULT_RESPONSE 0x5A Action to be taken by the device when an
input undervoltage fault is detected.
POWER_GOOD_ON 0x5E Output voltage at or above which a power
good should be asserted.
0x1EB8
44
POWER_GOOD_OFF 0x5F Output voltage at or below which a power
good should be de-asserted when Mfr_
config_all_pwrgd_off_uses_uv is clear.
0x1E14
44
LTC2974
24
2974f
Summary Table
COMMAND NAME
CMD
DATA
FORMAT UNITS NVM
DEFAULT
VALUE:
FLOAT
HEX
REF
PAGE
TON_DELAY 0x60 Time from CONTROL pin and/or OPERATION
command = ON to V
OUT_EN
pin = ON.
R/W Word Y L11 mS Y 1.0
0xBA00
51
TON_RISE 0x61 Time from when the output starts to rise
until the LTC2974 optionally soft-connects its
DAC and begins to servo the output voltage
to the desired value.
0xD280
51
TON_MAX_FAULT_LIMIT 0x62 Maximum time from V
OUT_EN
pin on
assertion that an UV condition will be
tolerated before a TON_MAX_FAULT
condition results.
0xD3C0
51
TON_MAX_FAULT_RESPONSE 0x63 Action to be taken by the device when a
TON_MAX_FAULT event is detected.
TOFF_DELAY 0x64 Time from CONTROL pin and/or OPERATION
command = OFF to V
OUT_EN
pin = OFF.
0xBA00
51
STATUS_BYTE 0x78 One byte summary of the units fault
condition.
R Byte Y Reg NA 61
STATUS_WORD 0x79 Two byte summary of the units fault
condition.
R Word Y Reg NA 61
STATUS_VOUT 0x7A Output voltage fault and warning status. R Byte Y Reg NA 61
STATUS_IOUT 0x7B Output current fault and warning status. R Byte Y Reg NA 61
STATUS_INPUT 0x7C Input supply fault and warning status. R Byte N Reg NA 61
STATUS_TEMPERATURE 0x7D External temperature fault and warning
status for READ_TEMPERATURE_1.
R Byte Y Reg NA 61
STATUS_CML 0x7E Communication and memory fault and
warning status.
R Byte N Reg NA 61
STATUS_MFR_SPECIFIC 0x80 Manufacturer specific fault and state
information.
R Byte Y Reg NA 61
READ_VIN 0x88 Input supply voltage. R Word N L11 V NA 66
READ_VOUT 0x8B DC/DC converter output voltage. R Word Y L16 V NA 66
READ_IOUT 0x8C DC/DC converter output current. R Word Y L11 A NA 66
READ_TEMPERATURE_1 0x8D External diode junction temperature. This
is the value used for all temperature related
processing, including IOUT_CAL_GAIN.
R Word Y L11 C NA 66
READ_TEMPERATURE_2 0x8E Internal junction temperature. R Word N L11 C NA 66
READ_POUT 0x96 DC/DC converter output power. R Word Y L11 W NA 66
PMBUS_REVISION 0x98 PMBus revision supported by this device.
Current revision is 1.1.
R Byte N Reg 0x11 78
USER_DATA_00 0xB0 Manufacturer reserved for LTpowerPlay. R/W Word N Reg Y N/A 79
USER_DATA_01 0xB1 Manufacturer reserved for LTpowerPlay. R/W Word Y Reg Y N/A 79
USER_DATA_02 0xB2 OEM Reserved. R/W Word N Reg Y N/A 79
LTC2974
25
2974f
Summary Table
COMMAND NAME
CMD
DATA
FORMAT UNITS NVM
DEFAULT
VALUE:
FLOAT
HEX
REF
PAGE
USER_DATA_03 0xB3 Scratchpad location. R/W Word Y Reg Y 0x00 79
USER_DATA_04 0xB4 Scratchpad location. R/W Word N Reg Y 0x00 79
MFR_LTC_RESERVED_1 0xB5 Manufacturer reserved. R/W Word Y Reg Y NA 79
MFR_T_SELF_HEAT 0xB8 Calculated temperature rise due to self
heating of output current sense device above
value measured by external temperature
sensor.
MFR_IOUT_CAL_GAIN_TAU_
INV
0xB9 Inverse of time constant for Mfr_t_self_heat
changes scaled by 4 t
CONV_SENSE
.
R/W Word Y L11 Y 0.0
0x8000
48
MFR_IOUT_CAL_GAIN_THETA 0xBA Thermal resistance from inductor core to
point measured by external temperature
sensor.
R/W Word Y L11 C/W Y 0.0
0x8000
48
MFR_READ_IOUT 0xBB Alternate data format for READ_IOUT. One
LSB = 2.5mA.
R Word Y CF 2.5mA NA 66
MFR_LTC_RESERVED_2 0xBC Manufacturer reserved. R/W Word Y Reg NA 79
MFR_EE_UNLOCK 0xBD Unlock user EEPROM for access by MFR_
EE_ERASE and MFR_EE_DATA commands.
R/W Byte N Reg NA 40
MFR_EE_ERASE 0xBE Initialize user EEPROM for bulk
programming by MFR_EE_DATA.
MFR_EE_DATA 0xBF Data transferred to and from EEPROM using
sequential PMBus word reads or writes.
Supports bulk programming.
R/W Word N Reg NA 40
MFR_CONFIG_LTC2974 0xD0 Configuration bits that are channel specific. R/W Word Y Reg Y 0x0080 30
MFR_CONFIG_ALL_LTC2974 0xD1 Configuration bits that are common to all
pages.
R/W Word N Reg Y 0x0F7B 30
MFR_FAULTB0_PROPAGATE 0xD2 Configuration that determines if a channels
faulted off state is propagated to the
FAULTB0 pin.
FAULTB1 pin.
MFR_PWRGD_EN 0xD4 Configuration that maps WDI/RESETB status
and individual channel power good to the
PWRGD pin.
R/W Word N Reg Y 0x0000 52
MFR_FAULTB0_RESPONSE 0xD5 Action to be taken by the device when the
FAULTB0 pin is asserted low.
MFR_IOUT_PEAK 0xD7 Maximum measured value of READ_IOUT. R Word Y L11 A NA 66
MFR_IOUT_MIN 0xD8 Minimum measured value of READ_IOUT. R Word Y L11 A NA 66
MFR_CONFIG2_LTC2974 0xD9 Configuration bits that are channel specific R/W Byte N Reg Y 0x00 30
LTC2974
26
2974f
Summary Table
COMMAND NAME
CMD
DATA
FORMAT UNITS NVM
DEFAULT
VALUE:
FLOAT
HEX
REF
PAGE
MFR_CONFIG3_LTC2974 0xDA Configuration bits that are channel specific R/W Byte N Reg Y 0x00 30
MFR_RETRY_DELAY 0xDB Retry interval during FAULT retry mode. R/W Word N L11 mS Y 200
0xF320
54
MFR_RESTART_DELAY 0xDC Delay from actual CONTROL active edge to
virtual CONTROL active edge.
R/W Word N L11 mS Y 400
0xFB20
51
MFR_VOUT_PEAK 0xDD Maximum measured value of READ_VOUT. R Word Y L16 V NA 66
MFR_VIN_PEAK 0xDE Maximum measured value of READ_VIN. R Word N L11 V NA 66
MFR_TEMPERATURE_1_PEAK 0xDF Maximum measured value of READ_
TEMPERATURE_1.
MFR_DAC 0xE0 Manufacturer register that contains the code
of the 10-bit DAC.
R/W Word Y U16 Y 0x0000 44
MFR_POWERGOOD_
ASSERTION_DELAY
0xE1 Power-good output assertion delay. R/W Word N L11 mS Y 100
0xEB20
52
MFR_WATCHDOG_T_FIRST 0xE2 First watchdog timer interval. R/W Word N L11 mS Y 0
0x8000
52
MFR_WATCHDOG_T 0xE3 Watchdog timer interval. R/W Word N L11 mS Y 0
0x8000
52
MFR_PAGE_FF_MASK 0xE4 Configuration defining which channels
respond to global page commands
(PAGE=0xFF).
R/W Byte N Reg Y 0xF 28
MFR_PADS 0xE5 Current state of selected digital I/O pads. R/W Word N Reg NA 61
MFR_I2C_BASE_ADDRESS 0xE6 Base value of the I
2
C/SMBus address byte. R/W Byte N U16 Y 0x5C 28
MFR_SPECIAL_ID 0xE7 Manufacturer code for identifying the
LTC2974.
R Word N Reg Y 0x0212 78
MFR_SPECIAL_LOT 0xE8 Customer dependent codes that identify
the factory programmed user configuration
stored in EEPROM. Contact factory for
default value.
R Byte Y Reg Y 78
MFR_VOUT_DISCHARGE_
THRESHOLD
0xE9 Coefficient used to multiply VOUT_
COMMAND in order to determine V
OUT
off
threshold voltage.
0xC200
44
MFR_FAULT_LOG_STORE 0xEA Command a transfer of the fault log from
RAM to EEPROM.
Send Byte N NA 70
MFR_FAULT_LOG_RESTORE 0xEB Command a transfer of the fault log
previously stored in EEPROM back to RAM.
Send Byte N NA 70
MFR_FAULT_LOG_CLEAR 0xEC Initialize the EEPROM block reserved for fault
logging and clear any previous fault logging
locks.
Send Byte N NA 70
MFR_FAULT_LOG_STATUS 0xED Fault logging status. R Byte N Reg Y NA 70
MFR_FAULT_LOG 0xEE Fault log data bytes. This sequentially
retrieved data is used to assemble a
complete fault log.
R Block N Reg Y NA 70
MFR_COMMON 0xEF Manufacturer status bits that are common
across multiple LTC chips.
R Byte N Reg NA 61
LTC2974
27
2974f
Summary Table
COMMAND NAME
CMD
DATA
FORMAT UNITS NVM
DEFAULT
VALUE:
FLOAT
HEX
REF
PAGE
MFR_IOUT_CAL_GAIN_TC 0xF6 Temperature coefficient applied to IOUT_
CAL_GAIN.
R/W Word Y CF ppm Y 0x0 46
MFR_RETRY_COUNT 0xF7 Retry count for all faulted off conditions that
enable retry.
R/W Byte N U16 Y 0x00 54
MFR_TEMP_1_GAIN 0xF8 Inverse of external diode temperature non
ideality factor. One LSB = 2
14
.
R/W Word Y CF Y 1
0x4000
48
MFR_TEMP_1_OFFSET 0xF9 Offset value for the external temperature. R/W Word Y L11 C Y 0
0x8000
48
MFR_IOUT_SENSE_VOLTAGE 0xFA Absolute value of V
ISENSEP
V
ISENSEM
. One
LSB = 3.05V.
R Word Y CF 3.05V NA 66
MFR_VOUT_MIN 0xFB Minimum measured value of READ_VOUT. R Word Y L16 V NA 66
MFR_VIN_MIN 0xFC Minimum measured value of READ_VIN. R Word N L11 V NA 66
MFR_TEMPERATURE_1_MIN 0xFD Minimum measured value of READ_
TEMPERATURE_1.
Data Formats
L11 Linear_5s_11s PMBus data field b[15:0]
Value = Y 2
N

where N = b[15:11] is a 5-bit twos complement integer and Y = b[10:0] is an 11-bit twos complement integer
Example:
READ_VIN = 10V
For b[15:0] = 0xD280 = 1101_0010_1000_0000b
Value = 640 2
6
= 10
See PMBus Spec Part II: Paragraph 7.1
L16 Linear_16u PMBus data field b[15:0]
Value = Y 2
N
where Y = b[15:0] is an unsigned integer and N = Vout_mode_parameter is a 5-bit twos complement exponent
that is hardwired to 13 decimal.
Example:
VOUT_COMMAND = 4.75V
For b[15:0] = 0x9800 = 1001_1000_0000_0000b
Value = 38912 2
13
= 4.75
See PMBus Spec Part II: Paragraph 8.3.1
Reg Register PMBus data field b[15:0] or b[7:0].
Bit field meaning is defined in detailed PMBus Command Register Description.
U16 Integer Word PMBus data field b[15:0]
Value = Y where Y = b[15:0] is a 16-bit unsigned integer
Example:
For b[15:0] = 0x9807 = 1001_1000_0000_0111b
Value = 38919
CF Custom Format PMBus data field b[15:0]
Value is defined in detailed PMBus Command Register Description. This is often an unsigned or twos complement integer
scaled by an MFR specific constant.
LTC2974
28
2974f
ADDRESSING AND WRITE PROTECT
COMMAND NAME
CMD
CODE DESCRIPTION TYPE PAGED FORMAT UNITS NVM
DEFAULT
VALUE
REF
PAGE
PAGE 0x00 Channel or page currently selected for any
command that supports paging.
R/W Byte N Reg 0x00 28
WRITE_PROTECT 0x10 Level of protection provided by the device
against accidental changes.
MFR_I2C_BASE_ADDRESS 0xE6 Base value of the I
2
C/SMBus address byte. R/W Byte N U16 Y 0x5C 29
MFR_PAGE_FF_MASK 0xE4 Configuration defining which channels
respond to global page commands
(PAGE=0xFF).
R/W Byte N Reg Y 0xF 29
pMbus coMManD DescripTion
PAGE
The LTC2974 has four pages that correspond to the four DC/DC converter channels that can be managed. Each DC/DC
converter channel can be uniquely programmed by first setting the appropriate page.
Setting PAGE = 0xFF allows a simultaneous write to all pages for PMBus commands that support global page pro-
gramming. The only commands that support PAGE = 0xFF are CLEAR_FAULTS, OPERATION and ON_OFF_CONFIG.
See MFR_PAGE_FF_MASK for additional options. Reading any paged PMBus register with PAGE = 0xFF returns un-
predictable data and will trigger a CML fault. Writes to pages that do not support PAGE = 0xFF with PAGE = 0xFF will
be ignored and generate a CML fault.
PAGE Data Contents
BIT(S) SYMBOL OPERATION
b[7:0] Page Page operation.
0x00: All PMBus commands address channel/page 0.
0xXX: All non specified values reserved.
0xFF: A single PMBus write/send to commands that support this mode will simultaneously address all channel/pages with
MFR_PAGE_FF_MASK enabled.
WRITE_PROTECT
The WRITE_PROTECT command provides protection against accidental programming of the LTC2974 command reg-
isters. All supported commands may have their parameters read, regardless of the WRITE_PROTECT setting, and the
EEPROM contents can also be read regardless of the WRITE_PROTECT settings.
There are two levels of protection:
Level 1: Nothing can be changed except the level of write protection itself. Values can be read from all pages. This
setting can be stored to EEPROM.
Level 2: Nothing can be changed except for the level of protection, channel on/off state, and clearing of faults. Values
can be read from all pages. This setting can be stored to EEPROM.
LTC2974
29
2974f
WRITE_PROTECT Data Contents
b[7:0] Write_protect[7:0] 1000_0000b: Level 1 Protection - Disable all writes except to the WRITE_PROTECT, PAGE, MFR_EE_UNLOCK, and STORE_
USER_ALL commands.
0100_0000b: Level 2 Protection Disable all writes except to the WRITE_PROTECT, PAGE, MFR_EE_UNLOCK, STORE_
USER_ALL, OPERATION, MFR_PAGE_FF_MASK and CLEAR_FAULTS commands.
0000_0000b: Enable writes to all commands.
xxxx_xxxxb: All other values reserved.
WRITE-PROTECT Pin
The WP pin allows the user to write-protect the LTC2974s configuration registers. The WP pin is active high, and when
asserted it provides Level 2 protection: all writes are disabled except to the WRITE_PROTECT, PAGE, MFR_EE_UNLOCK,
STORE_USER_ALL, OPERATION, MFR_PAGE_FF_MASK and CLEAR_FAULTS commands. The most restrictive setting
between the WP pin and WRITE_PROTECT command will override. For example if WP = 1 and WRITE_PROTECT =
0x80, then the WRITE_PROTECT command overrides, since it is the most restrictive.
MFR_PAGE_FF_MASK
The MFR_PAGE_FF_MASK command is used to select which channels respond when the global page command
(PAGE=0xFF) is in use.
MFR_PAGE_FF_MASK Data Contents
b[7:4] Reserved Always returns 0000b
b[3] Mfr_page_ff_mask_chan3 Channel 3 masking of global page command (PAGE=0xFF) accesses
0 = ignore global page command accesses
1 = fully respond to global page command accesses
MFR_I2C_BASE_ADDRESS
The MFR_I2C_BASE_ADDRESS command determines the base value for the I
2
C/SMBus address byte. Offsets of 0 to
9 are added to this base address to generate the device I
2
C/SMBus address. The part responds to the device address.
MFR_I2C_BASE_ADDRESS Data Contents
b[7] Reserved Read only, always returns 0.
b[6:0] i2c_base_address This 7-bit value determines the base value of the 7-bit I
2
C/SMBus address. See Operation Section: Device Address.
LTC2974
30
2974f
OPERATION
The OPERATION command is used to turn the unit on and off in conjunction with the CONTROL pin and ON_OFF_CON-
FIG. This command register responds to the global page command (PAGE=0xFF). The contents and functions of the
data byte are shown in the following tables.
OPERATION Data Contents (On_off_config_use_pmbus=1)
SYMBOL Action Operation_control[1:0] Operation_margin[1:0] Operation_fault[1:0] Reserved (read only)
BITS b[7:6] b[5:4] b[3:2] b[1:0]
FUNCTION
Turn off immediately 00 XX XX 00
Sequence on 10 00 XX 00
Margin low (ignore faults and
warnings)
10 01 01 00
Margin low 10 01 10 00
Margin high (ignore faults and
warnings
10 10 01 00
Margin high 10 10 10 00
Sequence off with margin to
nominal
01 00 XX 00
Sequence off with margin low
(ignore faults and warnings)
01 01 01 00
Sequence off with margin low 01 01 10 00
Sequence off with margin high
(ignore faults and warnings)
01 10 01 00
Sequence off with margin high 01 10 10 00
Reserved All remaining combinations
ON/OFF CONTROL, MARGINING AND CONFIGURATION
COMMAND NAME
CMD
DEFAULT
VALUE
REF
PAGE
OPERATION 0x01 Operating mode control. On/Off, Margin High
and Margin Low.
ON_OFF_CONFIG 0x02 CONTROL pin and PMBus on/off command
setting.
MFR_CONFIG_LTC2974 0xD0 Configuration bits that are channel specific. R/W Word Y Reg Y 0x0080 32
MFR_CONFIG2_LTC2974 0xD9 Configuration bits that are channel specific R/W Byte N Reg Y 0x00 35
MFR_CONFIG3_LTC2974 0xDA Configuration bits that are channel specific R/W Byte N Reg Y 0x00 35
MFR_CONFIG_ALL_LTC2974 0xD1 Configuration bits that are common to all
pages.
R/W Word N Reg Y 0x0F7B 39
LTC2974
31
2974f
OPERATION Data Contents (On_off_config_use_pmbus=0)
On or Off
SYMBOL Action Operation_control[1:0] Operation_margin[1:0] Operation_fault[1:0] Reserved (read only)
BITS b[7:6] b[5:4] b[3:2] b[1:0]
FUNCTION
Output at nominal 00, 01 or 10 00 XX 00
Margin low (ignore faults and
warnings)
00, 01 or 10 01 01 00
Margin low 00, 01 or 10 01 10 00
Margin high (ignore faults and
warnings
00, 01 or 10 10 01 00
Margin high 00, 01 or 10 10 10 00
Reserved All remaining combinations
ON_OFF_CONFIG
The ON_OFF_CONFIG command configures the combination of CONTROL pin input and PMBus commands needed
to turn the LTC2974 on/off, including the power-on behavior, as shown in the following table. This command register
responds to the global page command (PAGE=0xFF). After the part has initialized, an additional comparator monitors
VIN_SNS. The VIN_ON threshold must be exceeded before the output power sequencing can begin. After V
IN
is initially
applied, the part will typically require 30ms to initialize and begin the TON_DELAY timer. The readback of voltages and
currents may require an additional 180ms.
ON_OFF_CONFIG Data Contents
b[7:5] Reserved Dont care. Always returns 0.
b[4] On_off_config_controlled_on Control default autonomous power up operation.
0: Unit powers up regardless of the CONTROL pin or OPERATION value. Unit always powers up with
sequencing. To turn unit on without sequencing, set TON_DELAY = 0.
1: Unit does not power up unless commanded by the CONTROL pin and/or the OPERATION command on the
serial bus. If On_off_config[3:2] = 00, the unit never powers up.
b[3] On_off_config_use_pmbus Controls how the unit responds to commands received via the serial bus.
0: Unit ignores the Operation_control[1:0].
1: Unit responds to Operation_control[1:0]. Depending on On_off_config_use_control, the unit may also
require the CONTROL pin to be asserted for the unit to start.
b[2] On_off_config_use_control Controls how unit responds to the CONTROL pin.
0: Unit ignores the CONTROL pin.
1: Unit requires the CONTROL pin to be asserted to start the unit. Depending on On_off_config_use_pmbus
the OPERATION command may also be required to instruct the device to start.
b[1] Reserved Not supported. Always returns 1.
b[0] On_off_config_control_fast_off CONTROL pin turn off action when commanding the unit to turn off
0: Use the programmed TOFF_DELAY.
1: Turn off the output and stop transferring energy as quickly as possible. The device does not sink current in
order to decrease the output voltage fall time.
LTC2974
32
2974f
MFR_CONFIG_LTC2974
This command is used to configure various manufacturer specific operating parameters for each channel.
MFR_CONFIG_LTC2974 Data Contents
b[15] Reserved Dont care. Always returns 0.
b[14] Mfr_config_cascade_on Configures channels control pin for cascade sequence ON. There is no provision for cascade sequence
OFF. See description for time based sequence OFF options.
b[13:12] Mfr_config_controln_sel[1:0] Selects the active control pin input (CONTROL0 , CONTROL1, CONTROL2 or CONTROL3) for this channel.
0: Select CONTROL0 pin.
b[11] Mfr_config_fast_servo_off Disables fast servo when margining or trimming output voltages:
0: fast-servo enabled.
1: fast-servo disabled.
b[10] Mfr_config_supervisor_resolution Selects voltage supervisor resolution:
0: high resolution = 4mV / LSB, range for V
VSENSEPn
V
VSENSEMn
is 0 to 3.8V
1: low resolution = 8mV / LSB, range for V
VSENSEPn
V
VSENSEMn
is 0 to 6.0V
b[9:8] Reserved Always returns 0.
b[7] Mfr_config_servo_continuous Select whether the UNIT should continuously servo VOUT after it has reached a new margin or nominal
target. Only applies when Mfr_ config _dac_mode = 00b.
0: Do not continuously servo VOUT after reaching initial target.
1: Continuously servo VOUT to target.
b[6] Mfr_config_servo_on_warn Control re-servo on warning feature. Only applies when Mfr_config_dac_mode = 00b and Mfr_config_
servo_continuous = 0.
0: Do not allow the unit to re-servo when a VOUT warning threshold is met or exceeded.
1: Allow the unit to re-servo VOUT to nominal target if
VOUT V(Vout_ov_warn_limit) or
VOUT V(Vout_uv_warn_limit).
b[5:4] Mfr_config_dac_mode Determines how DAC is used when channel is in the ON state and TON_RISE has elapsed.
00: Soft connect (if needed) and servo to target.
01: DAC not connected.
10: DAC hard connected immediately using value from MFR_DAC command.
11: DAC is soft connected. After soft connect is complete MFR_DAC may be written.
b[3] Mfr_config_vo_en_wpu_en V
OUT_EN
pin charge pumped, current-limited pull-up enable.
0: Disable weak pull-up. V
OUT_EN
pin driver is three-stated when channel is on.
1: Use weak current-limited pull-up on V
OUT_EN
pin when the channel is on.
b[2] Mfr_config_vo_en_wpd_en V
OUT_EN
pin current-limited pull-down enable.
0: Use a fast N-channel device to pull down V
OUT_EN
pin when the channel is off for any reason.
1: Use weak current-limited pull-down to discharge V
OUT_EN
pin when channel is off due to soft stop by
the CONTROL pin and/or OPERATION command. If the channel is off due to a fault, use the fast pull-down
on the V
OUT_EN
pin.
LTC2974
33
2974f
MFR_CONFIG_LTC2974 Data Contents
b[1] Mfr_config_dac_gain DAC buffer gain.
0: Select DAC buffer gain dac_gain_0 (1.38V full-scale)
1: Select DAC buffer gain dac_gain_1 (2.65V full-scale)
b[0] Mfr_config_ dac_pol DAC output polarity.
0: Encodes negative (inverting) DC/DC converter trim input.
1: Encodes positive (non-inverting) DC/DC converter trim input.
Cascade Sequence ON with Time-Based Sequence OFF
Cascade sequence ON allows a master power supply to sequence on a series of slave supplies by connecting each
power supplys power good output to the control pin of the next power supply in the chain. Please note that the power
good signal is that of the power supply and not derived from the LTC2974s internal power good processing. Power
good based cascade sequence OFF is not supported, OFF sequencing must be managed using immediate or time based
sequence OFF. See also Tracking Based Sequencing.
Cascade sequence ON is illustrated in Figure 15. For each slave channel Mfr_config_cascade_on is asserted high and
the associated control input is connected to the power good output of the previous power supply. In this configuration
each slave channels startup is delayed until the previous supply has powered up.
Cascade sequence OFF is not directly supported. Options for reversing the sequence when turning the supplies off
include:
Using the OPERATION command to turn off all the channels with an appropriate off delay.
Using the FAULT pin to bring all the channels down immediately or in sequence with an appropriate off delay.
When asserted, Mfr_config_cascade_on enables a slave channel to honor fault retries even when its control pin is
low. Additionally, if the system has faulted off after zero or a finite number of retries, an OPERATION command may
Figure 15. LTC2974 Configured to Cascade Sequence ON and Time-Base Sequence OFF
V
OUTP
RUN
V
OUTM
V
SENSEP0
V
SENSEM0
POWERGOOD0
FAULTB0 FAULTB0
LTC2974
SLAVES
MASTER
CONTROL0
RECOMMENDED CONNECTION
WHEN HARDWARE ON/OFF
CONTROL IS REQUIRED
V
OUT_EN0
CONTROL1
CONTROL0
DC/DC LOAD
V
OUTP
RUN
V
OUTM
V
SENSEP1
V
SENSEM1
POWERGOOD1
V
OUT_EN1
CONTROL2
DC/DC LOAD
V
OUTP
RUN
V
OUTM
V
SENSEP2
V
SENSEM2
POWERGOOD2
V
OUT_EN2
CONTROL3
DC/DC LOAD
TO NEXT CONTROL PIN
V
OUTP
RUN
V
OUTM
V
SENSEP3
V
SENSEM3
POWERGOOD3
V
OUT_EN3
DC/DC LOAD
2974 F15
LTC2974
34
2974f
Figure 16. Cascade Sequence ON with Time Based Sequence Down on FAULT0
be used to turn all cascade channels off then on to clear the faulted off state when the slaves control pin is low. For
this reason we refer to the control pin as being redefined as a sequence pin.
The waveform of Figure 16 illustrates cascade sequence ON and time based sequence OFF using the configuration
illustrated in Figure 15. In this example the FAULTB0 pin is used as a broadcast off signal. Turning the system off with
the FAULTB0 requires all slave channels to be configured with Mfr_faultb0_response_chann asserted high. After the
system is turned off, the LTC2974 will assert ALERTB with all slave channels indicating a Status_mfr_fault0_in event.
V
OUT2
V
OUT3
POWERGOOD3
2974 F16
POWERGOOD2
POWERGOOD1
POWERGOOD0
CONTROL-FAULT0
V
OUT1
V
OUT0
TOFF_DELAY3
TOFF_DELAY2
TOFF_DELAY1
TOFF_DELAY0
LTC2974
35
2974f
MFR_CONFIG2_LTC2974
This command register determines whether V
OUT
overvoltage or overcurrent faults from a given channel cause the
AUXFAULTB pin to be forced low.
MFR_CONFIG2_LTC2974 Data Contents
b[7] Mfr_auxfaultb_oc_fault_response_
chan3
Response to channel 3 IOUT_OC_FAULT.
1 = Pull AUXFAULTB low via fast pull-down.
0 = Leave AUXFAULTB as-is.
chan2
chan1
chan0
b[3] Mfr_auxfaultb_ov_fault_response_
chan3
Response to channel 3 VOUT_OV_FAULT.
chan2
chan1
chan0
MFR_CONFIG3_LTC2974
This command register determines whether V
OUT
undercurrent faults from a given channel cause the AUXFAULTB pin
to be forced low. This command also allows tracking to be enabled on any channel.
MFR_CONFIG3_LTC2974 Data Contents
b[7] Mfr_auxfaultb_uc_fault_response_
chan3
Response to channel 3 IOUT_UC_FAULT.
chan2
LTC2974
36
2974f
chan1
chan0
b[3] Mfr_track_en_chan3 Select if channel 3 is a slave in a tracked power supply system.
0: Channel is not a slave in a tracked power supply system.
1: Channel is a slave in a tracked power supply system.
Figure 17. LTC2974 Configured to Control, Supervise and Monitor Power Supplies Equipped with Tracking Pin
V
OUTP
RUN
V
OUTM
V
SENSEP0
V
SENSEM0
TRACK
FAULTB0 FAULTB0
LTC2974
CONTROL0
V
OUT_EN0
CONTROL0
DC/DC LOAD
V
OUTP
RUN
V
OUTM
V
SENSEP1
V
SENSEM1
TRACK
V
OUT_EN1
DC/DC LOAD
V
OUTP
RUN
V
OUTM
V
SENSEP2
V
SENSEM2
TRACK
V
OUT_EN2
DC/DC LOAD
V
OUTP
RUN
V
OUTM
V
SENSEP3
V
SENSEM3
TRACK
V
FB
V
DAC0
V
FB
V
DAC1
V
DAC3
V
FB
V
DAC2
V
FB
V
OUT_EN3
V
SENSEP0
V
SENSEP1
V
SENSEP2
V
SENSEM0
V
SENSEM1
V
SENSEM3
V
SENSEM2
V
SENSEP3
DC/DC LOAD
2974 F17
R2_3
R1_3
R2_2
R1_2
R2_1
R1_1
PWRGD
LTC2974
37
2974f
Figure 18. Control Pin Tracking All Supplies Up And Down
Figure 19. Fault on Channel 1 Tracking All Supplies Down
Tracking Supplies On and Off
The LTC2974 supports tracking power supplies that are equipped with a tracking pin and configured for tracking.
A tracking power supply uses a secondary feedback terminal (TRACK) to allow its output voltage to be scaled to
an external master voltage. Typically the external voltage is generated by the supply with the highest voltage in the
system, which is fed to the slave track pins (see Figure 17). Any supplies that track a master supply must be enabled
before the master supply comes up and disabled after the master supply comes down. Enabling the slave supplies
when the master is down requires supervisors monitoring the slaves to disable UV detection. Slave UC detection must
V
OUT2
V
OUT3
VOUT_EN(3:1)
2974 F19
VOUT_EN0
FAULTB0
CONTROL
UV FAULT ON CHANNEL 1 BRINGS DOWN MASTER
VIA FAULTB0. ALL SLAVE CHANNELS INCLUDING
THE ONE WITH THE UV FAULT ENTER TOFF_DELAY
SLAVE OUTPUT ENABLES TURN ON FIRST SLAVE OUTPUT ENABLES TURN OFF LAST
MASTER BRINGS DOWN
NEXT HIGHEST SLAVE
TON_RISE EXPIRES
FOR ALL CHANNELS.
UV AND UC DETECT ENABLED
ON ALL CHANNELS
TOFF_DELAY ENTERED
FOR ALL CHANNELS.
UV AND UC DETECT DISABLED
ON ALL CHANNELS
V
OUT1
V
OUT0
V
OUT2
V
OUT3
VOUT_EN(3:1)
2974 F18
VOUT_EN0
CONTROL
MASTER BRINGS DOWN
NEXT HIGHEST SLAVE
TON_RISE EXPIRES
FOR ALL CHANNELS.
ON ALL CHANNELS
TOFF_DELAY ENTERED
FOR ALL CHANNELS.
ON ALL CHANNELS
V
OUT1
V
OUT0
LTC2974
38
2974f
also be disabled when the slaves are tracking the master down to prevent false UC events. All channels configured
for tracking must track off together in response to a fault on any channel or any other condition that can bring one
or more of the channels down. Prematurely disabling a slave channel via its run pin may cause that channel to shut
down out of sequence (see Figure 20)
An important feature of the LTC2974 is the ability to control, monitor and supervise DC/DC converters that are config-
ured to track a master supply on and off.
The LTC2974 supports the following tracking features:
Track channels on and off without issuing false UV/UC events when the slave channels are tracking up or down.
Track all channels down in response to a fault from a slave or master.
Track all channels down when VIN_SNS drops below VIN_OFF, share clock is held low or Restore_user_all is issued.
Ability to to reconfigure selected channels that are part of a tracking group to sequence up after the group has
tracked up or sequence down before the group has tracked down.
Tracking Implementation
The LTC2974 supports tracking through the coordinated programing of Ton_delay, Ton_rise,Toff_delay and Mfr_track_
en_chann. The master channel must be configured to turn on after all the slave channels have turned on and to turn
off before all the slave channels turn off. Slaves that are enabled before the master will remain off until the tracking pin
allows them to turn on. Slaves will be turned off via the tracking pin even though their run pin is still asserted. Ton_rise
must be extended on the slaves so that it ends relative to the rise of the TRACK pin and not the rise of the V
OUT_EN
pin.
When Mfr_track_en_chann is enabled the channel is reconfigured to:
Sequence down on fault, VIN_OFF, SHARE_CLK low or RESTORE_USER_ALL.
Ignore UV and UC during TOFF_DELAY. Note that ignoring UV and UC during TON_RISE and TON_MAX_FAULT
always happens regardless of how this bit is set.
Figure 20. Improperly Configured Fault Response on Faulting Channel Disrupts Tracking
V
OUT2
V
OUT3
VOUT_EN(3:2)
2974 F20
VOUT_EN1
VOUT_EN0
FAULTB0
CONTROL
UV FAULT ON CHANNEL 1 BRINGS DOWN MASTER
VIA FAULTB0. ALL SLAVES WITH ENABLED RUN
PINS TRACK DOWN CORRECTLY
DISABLING VOUT_EN1
IMMEDIATELY IN RESPONSE
TO THE UV FAULT CAUSES
VOUT1 TO SHUT DOWN
OUT OF SEQUENCE
TON_RISE EXPIRES
FOR ALL CHANNELS.
ON ALL CHANNELS
TOFF_DELAY ENTERED
FOR ALL CHANNELS.
ON ALL CHANNELS
V
OUT1
V
OUT0
LTC2974
39
2974f
The following example illustrates configuring an LTC2974 with one master channel and three slaves.
Master channel 0
TON_DELAY = Ton_delay_master
TON_RISE = Ton_rise_master
TOFF_DELAY = Toff_delay_master
Mfr_track_en_chan0 = 0
Slave channel n
TON_DELAY = Ton_delay_slave
TON_RISE = Ton_delay_master + Ton_rise_slave
TOFF_DELAY = Toff_delay_master + T_off_delay_slave
Mfr_track_en_chan0 = 1
Where:
Ton_delay_master Ton_delay_slave > RUN to TRACK setup time
Toff_delay_slave > time for master supply to fall.
The system response to a control pin toggle is illustrated in Figure 18.
The system response to a UV fault on a slave channel is illustrated in Figure 19.
MFR_CONFIG_ALL_LTC2974
This command is used to configure parameters that are common to all channels on the IC. They may be set or reviewed
from any PAGE setting.
MFR_CONFIG_ALL_LTC2974 Data Contents
b[11] Mfr_config_all_pwrgd_off_uses_uv Selects PWRGD de-assertion source for all channels.
0: PWRGD is de-asserted based on V
OUT
being below or equal to POWER_GOOD_OFF. This option
uses the ADC. Response time is approx 100ms to 200ms.
1: PWRGD is de-asserted based on V
OUT
being below or equal to VOUT_UV_LIMIT. This option uses
the high speed supervisor. Response time is approximately 12s.
b[10] Mfr_config_all_fast_fault_log Controls number of ADC readings completed before transferring fault log memory to EEPROM.
0: All ADC telemetry values will be updated before transferring fault log to EEPROM. Slower.
1: Telemetry values will be transferred from fault log to EEPROM within 24ms after detecting fault.
Faster.
b[9] Mfr_config_all_control3_pol Selects active polarity of Control3 pin
0: Active low (pull pin low to start unit).
1: Active high (pull pin high to start unit).
LTC2974
40
2974f
MFR_CONFIG_ALL_LTC2974 Data Contents
b[7] Mfr_config_all_fault_log_enable Enable fault logging to NVM in response to Fault.
0: Fault logging to NVM (EEPROM) is disabled.
1: Fault logging to NVM is enabled.
b[6] Mfr_config_all_vin_on_clr_faults_en Allow VIN_ON rising edge to clear all latched faults.
0: VIN_ON clear faults feature is disabled.
1: VIN_ON clear faults feature is enabled.
b[3] Mfr_config_all_vin_share_enable Allow this unit to hold Share-clock pin low when V
IN
has not risen above VIN_ON or has fallen below
VIN_OFF. When enabled this unit will also turn all channels off in response to Share-clock being held
low.
0: Share-clock inhibit is disabled.
1: Share-clock inhibit is enabled.
b[2] Mfr_config_all_pec_en PMBus packet error checking enable.
0: PEC is disabled.
1: PEC is enabled.
b[1] Mfr_config_all_longer_pmbus_timeout Increase PMBus timeout interval by a factor of 8. Recommended for fault logging.
0: PMBus timeout is multiplied by a factor of 8.
1: PMBus timeout is not multiplied by a factor of 8.
b[0] Mfr_config_all_auxfaultb_wpu_dis AUXFAULTB charge pumped, current-limited pull-up disable.
0: Use weak current-limited pull-up on AUXFAULTB after power-up, as long as no faults have forced
AUXFAULTB off.
1: Disable weak pull-up. AUXFAULTB driver is tri-stated after power-up as long as no faults have
forced AUXFAULTB off.
PROGRAMMING USER EEPROM SPACE
COMMAND NAME
CMD
DEFAULT
VALUE
REF
PAGE
STORE_USER_ALL 0x15 Store entire operating memory to EEPROM. Send Byte N NA 41
RESTORE_USER_ALL 0x16 Restore entire operating memory from
EEPROM.
Send Byte N NA 41
MFR_EE_UNLOCK 0xBD Unlock user EEPROM for access by MFR_
EE_ERASE and MFR_EE_DATA commands.
MFR_EE_ERASE 0xBE Initialize user EEPROM for bulk
programming by MFR_EE_DATA.
MFR_EE_DATA 0xBF Data transferred to and from EEPROM using
sequential PMBus word reads or writes.
Supports bulk programming.
R/W Word N Reg NA 42
LTC2974
41
2974f
STORE_USER_ALL and RESTORE_USER_ALL
STORE_USER_ALL, RESTORE_USER_ALL commands provide access to User EEPROM space. Once a command is
stored in User EEPROM, it will be restored with explicit restore command or when the part emerges from power-on
reset after power is applied. While either of these commands is being processed, the part will indicate it is busy, see
Response When Part Is Busy on page 43.
STORE_USER_ALL. Issuing this command will store all operating memory commands with a corresponding EEPROM
memory location. It is recommended that this command not be executed while a unit is enabled since all monitoring
is suspended while the operating memory is transferred to EEPROM.
RESTORE_USER_ALL. Issuing this command will restore all commands from EEPROM Memory. It is recommended
that this command not be executed while a unit is enabled since all monitoring is suspended while the EEPROM is
transferred to operating memory, and intermediate values from EEPROM may not be compatible with the values initially
stored in operating memory.
Bulk Programming the User EEPROM Space
The MFR_EE_UNLOCK, MFR_EE_ERASE and MFR_EE_DATA commands provide a method for 3rd party EEPROM
programming houses and end users to easily program the LTC2974 independent of any order dependencies or delays
between PMBus commands. All data transfers are directly to and from the EEPROM and do not affect the volatile RAM
space currently configuring the device.
The first step is to program a master reference part with the desired configuration. MFR_EE_UNLOCK and MFR_EE_DATA
are then used to read back all the data in User EEPROM space as sequential words. This information is stored to the
master programming HEX file. Subsequent parts may be cloned to match the master part using MFR_EE_UNLOCK,
MFR_EE_ERASE and MFR_EE_DATA to transfer data from the master HEX file. These commands operate directly on
the EEPROM independent of the part configurations stored in RAM space. During EEPROM access the part will indicate
that it is busy as described below.
In order to support simple programming fixtures the bulk programming features only uses PMBus word and byte com-
mands. The MFR_UNLOCK configures the appropriate access mode and resets an internal address pointer allowing
a series of word commands to behave as a block read or write with the address pointer being incremented after each
operation. PEC use is optional and is configured by the MFR_EE_UNLOCK operation.
MFR_EE_UNLOCK
The MFR_EE_UNLOCK command prevents accidental EEPROM access in normal operation and configures the required
EEPROM bulk programming mode for bulk initialization, sequential writes, or reads. MFR_EE_UNLOCK augments the
protection provided by write protect. Upon unlocking the part for the required operation, an internal address pointer is
reset allowing a series of MFR_EE_DATA reads or writes to sequentially transfer data, similar to a block read or block
write. The MFR_EE_UNLOCK command can clear or set PEC mode based on the desired level of error protection. An
MFR_EE_UNLOCK sequence consists of writing two unlock codes using two byte write commands. The following
table documents the allowed sequences. Writing a non supported sequence locks the part. Reading MFR_EE_UNLOCK
returns the last byte written or zero if the part is locked.
LTC2974
42
2974f
MFR_EE_UNLOCK Data Contents
b[7:0] Mfr_ee_unlock[7:0] To unlock user EEPROM space for Mfr_ee_erase and Mfr_ee_data read or write operations with PEC allowed:
Write 0x2b followed by 0xd4.
To unlock user EEPROM space for Mfr_ee_erase and Mfr_ee_data read or write operations with PEC required:
Write 0x2b followed by 0xd5.
To unlock user and manufacturer EEPROM space for Mfr_ee_data read only operations with PEC allowed:
Write 0x2b, followed by 0x91 followed by 0xe4.
To unlock user and manufacturer EEPROM space for Mfr_ee_data read only operations with PEC required:
Write 0x2b, followed by 0x91 followed by 0xe5.
MFR_EE_ERASE
The MFR_EE_ERASE command is used to erase the entire contents of the user EEPROM space and configures this
space to accept new program data. Writing values other than 0x2B will lock the part. Reads return the last value written.
MFR_EE_ERASE Data contents
b[7:0] Mfr_ee_erase[7:0] To erase the user EEPROM space and configure to accept new data:
1) Use the appropriate Mfr_ee_unlock sequence to configure for Mfr_ee_erase commands with or without PEC.
2) Write 0x2B to Mfr_ee_erase.
The part will indicate it is busy erasing the EEPROM by the mechanism detailed below.
MFR_EE_DATA
The MFR_EE_DATA command allows the user to transfer data directly to or from the EEPROM without affecting RAM
space.
To read the user EEPROM space issue the appropriate Mfr_ee_unlock command and perform Mfr_ee_data reads until
the EEPROM has been completely read. Extra reads will lock the part and return zero. The first read returns the 16-bit
EEPROM packing revision ID that is stored in ROM. The second read returns the number of 16-bit words available;
this is the number of reads or writes to access all memory locations. Subsequent reads return EEPROM data starting
with lowest address.
To write to the user EEPROM space issue the appropriate Mfr_ee_unlock and Mfr_ee_erase commands followed by
successive Mfr_ee_data word writes until the EEPROM is full. Extra writes will lock the part. The first write is to the
lowest address.
Mfr_ee_data reads and writes must not be mixed.
LTC2974
43
2974f
MFR_EE_DATA Data Contents
b[7:0] Mfr_ee_data[7:0] To read user space
1) Use the appropriate Mfr_ee_unlock sequence to configure for Mfr_ee_data commands with or without PEC.
2) Read Mfr_ee_data[0] = PackingId (MFR Specific ID).
3) Read Mfr_ee_data[1] = NumberOfUserWords (total number of 16-bit word available).
4) Read Mfr_ee_data[2] through Mfr_ee_data[NumberOfWord+1] (User EEPROM data contents)
To write user space
1) Initialize the user memory using the sequence described for the MFR_EE_ERASE command.
2) Use the appropriate Mfr_ee_unlock sequence to configure for Mfr_ee_data commands with or without PEC.
3) Write Mfr_ee_data[0] through Mfr_ee_data[NumberOfWord-1] (User EEPROM data content to be wriiten)
The part will indicate it is busy erasing the EEPROM by the mechanism detailed below.
Response When Part Is Busy
The part will indicate it is busy accessing the EEPROM by the following mechanism:
1) Clearing Mfr_common_busyb of the MFR_COMMON register. This byte can always be read and will never NACK a
byte read request even if the part is busy.
2) NACKing commands other than Mfr_common.
MFR_EE Erase and Write Programming Time
The program time per word is typically 0.17ms and will require spacing the I
2
C/SMBus writes at greater than 0.17ms
to guarantee the write has completed. The Mfr_ee_erase command takes approximately 400ms. We recommend using
Mfr_common for handshaking.
VIN_ON, VIN_OFF, VIN_OV_FAULT_LIMIT, VIN_OV_WARN_LIMIT, VIN_UV_WARN_LIMIT and
VIN_UV_FAULT_LIMIT
These commands provide voltage supervising limits for V
IN
.
INPUT VOLTAGE COMMANDS AND LIMITS
COMMAND NAME
CMD
DEFAULT
VALUE
REF
PAGE
VIN_ON 0x35 Input voltage above which power conversion can
be enabled.
0xD280
43
VIN_OFF 0x36 Input voltage below which power conversion is
disabled. All VOUT_EN pins go off immediately or
sequence off after TOFF_DELAY (See Mfr_config_
track_enn).
0xD240
43
VIN_OV_FAULT_LIMIT 0x55 Input overvoltage fault limit measured at VIN_
SNS pin.
0xD3C0
43
VIN_OV_WARN_LIMIT 0x57 Input overvoltage warning limit measured at
VIN_SNS pin.
0xD380
43
VIN_UV_WARN_LIMIT 0x58 Input undervoltage warning limit measured at
VIN_SNS pin.
0x8000
43
VIN_UV_FAULT_LIMIT 0x59 Input undervoltage fault limit measured at
VIN_SNS pin.
0x8000
43
LTC2974
44
2974f
VOUT_MODE
This command is read only and specifies the mode and exponent for all commands with a L16 data format. See
Data Formats on page 27.
VOUT_MODE Data Contents
b[7:5] Vout_mode_type Reports linear mode. Hard-wired to 000b.
b[4:0] Vout_mode_parameter Linear mode exponent. 5-bit twos complement integer. Hardwired to 0x13 (13 decimal).
OUTPUT VOLTAGE COMMANDS AND LIMITS
COMMAND NAME
CMD
DEFAULT
VALUE
REF
PAGE
VOUT_MODE 0x20 Output voltage data format and mantissa
exponent (2
13)
.
R Byte Y Reg 0x13 44
VOUT_COMMAND 0x21 Servo target. Nominal DC/DC converter output
voltage setpoint.
0x2000
45
VOUT_MAX 0x24 Upper limit on the output voltage the unit can
command regardless of any other commands.
0x8000
45
VOUT_MARGIN_HIGH 0x25 Margin high DC/DC converter output voltage
setting.
0x219A
45
VOUT_MARGIN_LOW 0x26 Margin low DC/DC converter output voltage
setting.
0x1E66
45
VOUT_OV_FAULT_LIMIT 0x40 Output overvoltage fault limit. R/W Word Y L16 V Y 1.1
0x2333
45
VOUT_OV_WARN_LIMIT 0x42 Output overvoltage warning limit. R/W Word Y L16 V Y 1.075
0x2266
45
VOUT_UV_WARN_LIMIT 0x43 Output undervoltage warning limit. R/W Word Y L16 V Y 0.925
0x1D9A
45
VOUT_UV_FAULT_LIMIT 0x44 Output undervoltage fault limit. Used for Ton_
max_fault and power good de-assertion.
0x1CCD
45
POWER_GOOD_ON 0x5E Output voltage at or above which a power good
should be asserted.
0x1EB8
45
POWER_GOOD_OFF 0x5F Output voltage at or below which a power good
should be de-asserted when Mfr_config_all_
pwrgd_off_uses_uv is clear.
0x1E14
45
MFR_VOUT_DISCHARGE_
THRESHOLD
0xE9 Coefficient used to multiply VOUT_COMMAND in
order to determine V
OUT
off threshold voltage.
0xC200
45
MFR_DAC 0xE0 Manufacturer register that contains the code of
the 10-bit DAC.
R/W Word Y U16 Y 0x0000 45
LTC2974
45
2974f
VOUT_COMMAND, VOUT_MAX, VOUT_MARGIN_HIGH, VOUT_MARGIN_LOW, VOUT_OV_FAULT_LIMIT,
VOUT_OV_WARN_LIMIT, VOUT_UV_WARN_LIMIT, VOUT_UV_FAULT_LIMIT, POWER_GOOD_ON and
POWER_GOOD_OFF
These commands provide various servo, margining and supervising limits for a channels output voltage.
MFR_VOUT_DISCHARGE_THRESHOLD
This register contains the coefficient that multiplies VOUT_COMMAND in order to determine the OFF threshold volt-
age for the associated output. If the output voltage has not decayed below MFR_VOUT_DISCHARGE_THRESHOLD
VOUT_COMMAND prior to the channel being commanded to enter/re-enter the ON state, the Status_mfr_discharge bit
in the STATUS_MFR_SPECIFIC register will be set and the ALERTB pin will be asserted low. In addition, the channel
will not enter the ON state until the output has decayed below its off-threshold voltage. Setting this to a value greater
than 1.0 effectively disables DISCHARGE_THRESHOLD checking, allowing the channel to turn back on even if it has
not decayed at all.
Other channels can be held-off if a particular output has failed to discharge by using the bidirectional FAULTBn pins
(refer to the MFR_FAULTBn_RESPONSE and MFR_FAULTBn_PROPOGATE registers).
MFR_DAC
This command register allows the user to directly program the 10-bit DAC. Manual DAC writes require the channel
to be in the ON state,TON_RISE to have expired and MFR_CONFIG_LTC2974 b[5:4] = 10b or 11b. Writing MFR_
CONFIG_LTC2974 b[5:4] = 10b commands the DAC to hard connect with the value in Mfr_dac_direct_val. Writing
b[5:4] = 11b commands the DAC to soft connect. Once the DAC has soft connected, Mfr_dac_direct_val returns the
value that allowed the DAC to be connected without perturbing the power supply. MFR_DAC writes are ignored when
MFR_CONFIG_LTC2974 b[5:4] = 00b or 01b.
MFR_DAC Data Contents
b[15:10] Reserved Read only, always returns 0.
b[9:0] Mfr_dac_direct_val DAC code value.
LTC2974
46
2974f
IOUT_CAL_GAIN
The IOUT_CAL_GAIN command is used to set the ratio of the voltage at the current sense pins to the sensed current.
For devices using a fixed current sense resistor, it is the same value as the resistance of the resistor (units are expressed
in m). IOUT_CAL_GAIN is internally limited to values between 0.01m to 1,000m. The register readback value
always returns what was last written and does not reflect internal limiting.
Calculations using IOUT_CAL_GAIN are:
V
IOUT_OC_FAULT_LIMIT
= IOUT_OC_FAULT_LIMIT IOUT_CAL_GAIN T
CORRECTION
V
IOUT_UC_FAULT_LIMIT
= IOUT_UC_FAULT_LIMIT IOUT_CAL_GAIN T
CORRECTION
Where:
T
CORRECTION
= (1 + MFR_IOUT_CAL_GAIN_TC 1E-6 (READ_TEMPERATURE_1 + MFR_T_SELF_HEAT 25.0))

READ_IOUT
V
IOUT _ SNSPn
V
IOUT _ SNSMn
(IOUT_CAL_GAIN) T
CORRECTION
Note:
T
CORRECTION
is limited by hardware to a value between 0.25 and 4.0.
READ_TEMPERATURE_2 is substituted for READ_TEMPERATURE_1 if the associated T
SENSE
network fails to detect
a valid temperature. See READ_TEMPERATURE_1 for more information.
OUTPUT CURRENT COMMANDS AND LIMITS
COMMAND NAME
CMD
DEFAULT
VALUE
REF
PAGE
IOUT_CAL_GAIN 0x38 The nominal resistance of the current sense
element in m.
R/W Word Y L11 m Y 1.0
0xBA00
46
IOUT_OC_FAULT_LIMIT 0x46 Output overcurrent fault limit. R/W Word Y L11 A Y 10.0
0xD280
47
IOUT_OC_WARN_LIMIT 0x4A Output overcurrent warning limit. R/W Word Y L11 A Y 5.0
0xCA80
47
IOUT_UC_FAULT_LIMIT 0x4B Output undercurrent fault limit. Used to detect a
reverse current and must be a negative value.
R/W Word Y L11 A Y -1.0
0xBE00
47
MFR_IOUT_CAL_GAIN_TC 0xF6 Temperature coefficient applied to IOUT_CAL_
GAIN.
R/W Word Y CF ppm Y 0x0 47
LTC2974
47
2974f
IOUT_OC_FAULT_LIMIT, IOUT_OC_WARN_LIMIT and IOUT_UC_FAULT_LIMIT
I
OUT
supervisor fault and warning limits.
IOUT_OC_FAULT_LIMITED is internally limited to values greater or equal to zero. The register readback value always
returns what was last written and does not reflect internal limiting.
IOUT_UC_FAULT_LIMITED is internally limited to values less than zero. The register readback value always returns
what was last written and does not reflect internal limiting.
MFR_IOUT_CAL_GAIN_TC
The MFR_IOUT_CAL_GAIN_TC is a paged command that sets the temperature coefficient of the IOUT_CAL_GAIN
register value in ppm/C. This command uses the temperature measured by the external temperature diode for the
associated page.
Refer to IOUT_CAL_GAIN for details on proper usage.
MFR_IOUT_CAL_GAIN_TC Data Contents
b[15:0] Mfr_iout_cal_gain_tc 16-bit twos complement integer representing the temperature coefficient.
Value = Y where Y = b[15:0] is a twos complement.
Example:
Mfr_iout_cal_gain_tc = 3900ppm
For b[15:0] = 0x0F3C
Value = 3900
LTC2974
48
2974f
OT_FAULT_LIMIT, OT_WARN_LIMIT, UT_WARN_LIMIT and UT_FAULT_LIMIT
These commands provide supervising limits for temperature as measured by the external diode.
MFR_TEMP_1_GAIN and MFR_TEMP_1_OFFSET
The MFR_TEMP_1_GAIN command specifies the inverse of the temperature sensor ideality factor. The MFR_TEMP_1_
OFFSET allows an offset to be applied to the measured temperature.
Calculations using these paged commands are:
READ_TEMPERATURE_1 = T
EXT
MFR_TEMP_1_GAIN 273.15 + MFR_TEMP_1_OFFSET
Where:
T
EXT
= Measured external temperature in degrees Kelvin.
SENSE
a valid temperature. Under these conditions MFR_TEMP1_GAIN and MFR_TEMP1_OFFSET will have no effect. See
READ_TEMPERATURE_1 for more information.
MFR_TEMP_1_GAIN Data Contents
b[15:0] Mfr_temp_1_gain[15:0] 16-bit integer representing inverse of temperature non-ideality factor. Value = Y 2
14
where Y = b[15:0] is an
unsigned integer. Example:
MFR_TEMP_1_GAIN = 1.0
For b[15:0] = 0x4000
Value = 16384 2
14
= 1.0
EXTERNAL TEMPERATURE COMMANDS AND LIMITS
COMMAND NAME
CMD
DEFAULT
VALUE
REF
PAGE
OT_FAULT_LIMIT 0x4F Overtemperature fault limit setting for
the external temperature sensor.
0xEA08
48
OT_WARN_LIMIT 0x51 Overtemperature warning limit for the
external temperature sensor
0xE3C0
48
UT_WARN_LIMIT 0x52 Undertemperature warning limit for
the external temperature sensor.
0x8000
48
UT_FAULT_LIMIT 0x53 Undertemperature fault limit for the
0xCD80
48
MFR_TEMP_1_GAIN 0xF8 Inverse of external diode temperature
non ideality factor. One LSB = 2
14
.
R/W Word Y CF Y 1
0x4000
48
MFR_TEMP_1_OFFSET 0xF9 Offset value for the external
temperature.
0x8000
48
MFR_T_SELF_HEAT 0xB8 Calculated temperature rise due to
self heating of output current sense
device above value measured by
MFR_IOUT_CAL_GAIN_TAU_INV 0xB9 Inverse of time constant for Mfr_t_
self_heat changes scaled by 4
tCONV_SENSE.
0x8000
49
MFR_IOUT_CAL_GAIN_THETA 0xBA Thermal resistance from inductor
core to point measured by external
temperature sensor.
R/W Word Y L11 C/W Y 0.0
0x8000
49
LTC2974
49
2974f
MFR_T_SELF_HEAT, MFR_IOUT_CAL_GAIN_TAU_INV and MFR_IOUT_CAL_GAIN_THETA
The LTC2974 uses an innovative (patent pending) algorithm to dynamically model the temperature rise from the external
temperature sensor to the inductor core. This temperature rise is called MFR_T_SELF_HEAT and is used to calculate the
final temperature correction required by IOUT_CAL_GAIN. The temperature rise is a function of the power dissipated
in the inductor DCR, the thermal resistance from the inductor core to the remote temperature sensor and the thermal
time constant of the inductor to board system. The algorithm simplifies the placement requirements for the external
temperature sensor and compensates for the significant steady state and transient temperature error from the inductor
core to the primary inductor heat sink.
The best way to understand the self heating effect inside the inductor is to model the system using the circuit analogy
of Figure 21. The 1st order differential equation for the above model may be approximated by the following difference
equation:
P
I
T
I
/
IS
= C
T
I
/t (Eq1) (when T
S
= 0)
from which:
T
I
= t (P
I

IS
T
I
)/(
IS
C
) (Eq2) or
T
I
= (P
I

IS
T
I
)
INV
(Eq3)
where

INV
= t/(
IS
C
) (Eq4)
and t is the sample period of the external temperature ADC.
The LTC2974 implements the self heating algorithm using Eq3 and Eq4 where:
T
I
=MFR_T_SELF_HEAT
P
I
= READ_IOUT (V
ISENSEP
V
ISENSEM
)
T
S
= READ_TEMPERATURE_1
T
I
= MFR_T_SELF_HEAT + T
S
t = 4 t
CONV_SENSE
. (One complete external temperature loop period)

INV
= MFR_IOUT_CAL_GAIN_TAU_INV

IS
= MFR_IOUT_CAL_GAIN_THETA
Figure 21. Electronic Analogy for Inductor Temperature Model
I = P
I
P
I
= CURRENT REPRESENTING THE POWER DISSIPATED BY THE INDUCTOR
(V
DCR
READ_IOUT WHERE V
DCR
= (V
ISENSEP
V
ISENSM
))
C
= CAPACITANCE REPRESENTING THERMAL HEAT CAPACITY OF THE INDUCTOR

(INCLUDED IN MFR_IOUT_CAL_GAIN_TAU_INV)
T
I
= VOLTAGE REPRESENTING THE TEMPERATURE OF THE INDUCTOR
IS
= RESISTANCE REPRESENTING THE THERMAL RESISTANCE FROM THE DCR
TO THE REMOTE TEMPERATURE SENSOR (MFR_IOUT_CAL_GAIN_THETA)
T
S
= VOLTAGE REPRESENTING THE TEMPERATURE AT THE REMOTE
TEMPERATURE SENSOR
2974 F21
C = C
R =
IS
V
S
= T
S
V
I
= T
I
LTC2974
50
2974f
Initially self heat is set to zero. After each temperature measurement self heat is updated to be the previous value of
self heat incremented or decremented by MFR_T_SELF_HEAT.
The actual value of C
is not required. The important quantity is the thermal time constant

INV
= (
IS
C
). For example,
if an inductor has a thermal time constant
INV
= 5 seconds then:
MFR_IOUT_CAL_GAIN_TAU_INV = (4 t
CONV_SENSE
)/5 = 4 66ms/5s = 0.0528
Refer to the application section for more information on calibrating
IS
and
INV
.
SENSE
a valid temperature. Under these conditions T
S
= READ_TEMPERATURE_2 and the self heating correction is applied
using the internal die temperature. See READ_TEMPERATURE_1 for more information.
MFR_T_SELF_HEAT Data Content
Bit(s) Symbol Operation
b[15:0] Mfr_t_self_heat Values are limited to the range 0C to 50C.
MFR_IOUT_CAL_GAIN_THETA Data Content
b[15:0] Mfr_iout_cal_gain_theta Values 0 set MFR_T_SELF_HEAT to zero.
MFR_IOUT_CAL_GAIN_TAU_INV Data Content
b[15:0] Mfr_iout_cal_gain_tau_inv Values 0 set MFR_T_SELF_HEAT to zero.
Values 1 set MFR_T_SELF_HEAT to MFR_IOUT_CAL_GAIN_THETA READ_IOUT (V
ISENSEP
V
ISENSEM
).
LTC2974
51
2974f
TON_DELAY, TON_RISE, TON_MAX_FAULT_LIMIT and TOFF_DELAY
These commands share the same format and provide sequencing and timer fault and warning delays in ms.
TON_DELAY is the amount time in ms that elapses after the channel has been allowed on (usually due to CONTROL pin
or OPERATION command) until the channel enables the power supply. This delay is counted using SHARE_CLK only.
TON_RISE is the amount of time in ms that elapses after the power supply has been enabled until the LTC2974s DAC
soft connects and servos the output voltage to the desired level if Mfr_dac_mode = 00b. This delay is counted using
SHARE_CLK only.
TON_MAX_FAULT_LIMIT is the maximum amount of time that the power supply being controlled by the LTC2974 can
attempt to power up the output without reaching the VOUT_UV_FAULT_LIMIT. If it does not, then a TON_MAX_FAULT
is declared. If the output reaches VOUT_UV_FAULT_LIMIT prior to TON_MAX_FAULT_LIMIT, the LTC2974 unmasks the
VOUT_UV_FAULT_LIMIT threshold. (Note that a value of zero means there is no limit to how long the power supply
can attempt to bring up its output voltage.) This delay is counted using SHARE_CLK only.
TOFF_DELAY is the amount of time that elapses after the CONTROL pin and/or OPERATION command is de-asserted
until the channel is disabled (soft-off). This delay is counted using SHARE_CLK if available, otherwise the internal
oscillator is used.
All of the above TON and TOFF delays are internally limited to 655ms, and rounded to the nearest 10s. The read value
of these commands always returns what was last written and does not reflect internal limiting.
MFR_RESTART_DELAY
This command essentially sets the off time of a CONTROL pin initiated restart. If the CONTROL pin is toggled off for at
least 10s then on, all dependent channels are disabled, held off for a time = Mfr_restart_delay, then sequenced back
on. CONTROL pin transitions whose OFF time exceeds Mfr_restart_delay are not affected by this command. A value
of all zeros disables this feature. This delay is counted using SHARE_CLK only.
This delay is internally limited to 13.1 seconds, and rounded to the nearest 200s. The read value of this command
always returns what was last written and does not reflect internal limiting.
SEQUENCING TIMING LIMITS AND CLOCK SHARING
COMMAND NAME
CMD
DEFAULT
VALUE
REF
PAGE
TON_DELAY 0x60 Time from CONTROL pin and/or OPERATION
command = ON to VOUT_EN pin = ON.
0xBA00
51
TON_RISE 0x61 Time from when the output starts to rise until the
LTC2974 optionally soft-connects its DAC and
begins to servo the output voltage to the desired
value.
0xD280
51
TON_MAX_FAULT_LIMIT 0x62 Maximum time from V
OUT_EN
pin on assertion
that an UV condition will be tolerated before a
TON_MAX_FAULT condition results.
0xD3C0
51
TOFF_DELAY 0x64 Time from CONTROL pin and/or OPERATION
command = OFF to VOUT_EN pin = OFF.
0xBA00
51
MFR_RESTART_DELAY 0xDC Delay from actual CONTROL active edge to virtual
CONTROL active edge.
R/W Word N L11 mS Y 400
0xFB20
51
LTC2974
52
2974f
Clock Sharing
Multiple LTC PMBus devices can synchronize their clocks in an application by connecting together the open-drain
SHARE_CLK input/outputs to a pull-up resistor as a wired OR. In this case the fastest clock will take over and syn-
chronize all other chips to its falling edge.
SHARE_CLK can optionally be used to synchronize ON/OFF dependency on V
IN
across multiple chips by setting the
Mfr_config_all_vin_share_enable bit of the MFR_CONFIG_ALL register. When configured this way the chip will hold
SHARE_CLK low when the unit is off for insufficient input voltage, and upon detecting that SHARE_CLK is held low
the chip will disable all channels after a brief deglitch period. When the SHARE_CLK pin is allowed to rise, the chip
will respond by beginning a start sequence. In this case the slowest VIN_ON detection will take over and synchronize
other chips to its start sequence.
WATCHDOG TIMER AND POWER GOOD
COMMAND NAME
CMD
DEFAULT
VALUE
REF
PAGE
MFR_PWRGD_EN 0xD4 Configuration that maps WDI/
RESETB status and individual
channel power good to the PWRGD
pin.
R/W Word N Reg Y 0x0000 52
MFR_POWERGOOD_ASSERTION_DELAY 0xE1 Power-good output assertion delay. R/W Word N L11 mS Y 100
0xEB20
53
MFR_WATCHDOG_T_FIRST 0xE2 First watchdog timer interval. R/W Word N L11 mS Y 0
0x8000
53
MFR_WATCHDOG_T 0xE3 Watchdog timer interval. R/W Word N L11 mS Y 0
0x8000
53
MFR_PWRGD_EN
This command register controls the mapping of the watchdog and channel power good status to the PWRGD pin.
MFR_PWRGD_EN Data Contents
b[15:9] Reserved Read only, always returns 0s.
b[8] Mfr_pwrgd_en_wdog Watchdog.
1 = Watchdog timer not-expired status is ANDed with PWRGD status for any similarly enabled channels to determine
when the PWRGD pin gets asserted.
0 = Watchdog timer does not affect the PWRGD pin.
b[7:4] Reserved Always returns 0000b.
b[3] Mfr_pwrgd_en_chan3 Channel 3.
1 = PWRGD status for this channel is ANDed with PWRGD status for any similarly enabled channels to determine when
the PWRGD pin gets asserted.
0 = PWRGD status for this channel does not affect the PWRGD pin.
LTC2974
53
2974f
MFR_POWERGOOD_ASSERTION_DELAY
This command register allows the user to program the delay from when the internal power-good signal becomes valid
until the power-good output is asserted. This delay is counted using SHARE_CLK if available, otherwise the internal
oscillator is used. This delay is internally limited to 13.1 seconds, and rounded to the nearest 200s. The read value
of this command always returns what was last written and does not reflect internal limiting.
The power good de-assertion delay and threshold source is controlled by Mfr_config_all_pwrgd_off_uses_uv. Sys-
tems that require a fast power good de-assertion should set Mfr_config_all_pwrgd_off_uses_uv=1. This uses the
VOUT_UV_FAULT_LIMIT and the high speed comparator to de-assert the PWRGD pin. Systems that require a separate
power good off threshold should set Mfr_config_all_pwrgd_off_uses_uv=0. This uses the slower ADC polling loop
and POWER_GOOD_OFF to de-assert the PWRGD pin.
Watchdog Operation
A non-zero write to the MFR_WATCHDOG_T register will reset the watchdog timer. Low-to-high transitions on the
WDI/RESETB pin also reset the watchdog timer. If the timer expires, ALERTB is asserted and the PWRGD output
is optionally de-asserted and then reasserted after MFR_PWRGD_ASSERTION_DELAY ms. Writing 0 to either the
MFR_WATCH_DOG_T or MFR_WATCHDOG_T_FIRST registers will disable the timer.
MFR_WATCHDOG_T_FIRST and MFR_WATCHDOG_T
The MFR_WATCHDOG_T_FIRST register allows the user to program the duration of the first watchdog timer interval
following assertion of the PWRGD signal, assuming the PWRGD signal reflects the status of the watchdog timer. If
assertion of PWRGD is not conditioned by the watchdog timers status, then MFR_WATCHDOG_T_FIRST applies to
the first timing interval after the timer is enabled. Writing a value of 0ms to the MFR_WATCHDOG_T_FIRST register
disables the watchdog timer. This delay is internally limited to 65 seconds and rounded to the nearest 1ms.
The MFR_WATCHDOG_T register allows the user to program watchdog timer intervals subsequent to the MFR_WATCH-
DOG_T_FIRST timing interval. Writing a value of 0ms to the MFR_WATCHDOG_T register disables the watchdog timer.
This delay is internally limited to 655ms and rounded to the nearest 10s.
Both timers operate on an internal clock independent of SHARE_CLK. The read value of both commands always returns
what was last written and does not reflect internal limiting.
LTC2974
54
2974f
Clearing Latched Faults
Latched faults are reset by toggling the CONTROL pin, using the OPERATION command, or removing and reapplying
the bias voltage to the V
IN_SNS
pin. All fault and warning conditions result in the ALERTB pin being asserted low and
the corresponding bits being set in the status registers. The CLEAR_FAULTS command resets the contents of the
status registers and de-asserts the ALERTB output. The CLEAR_FAULTS does not clear a faulted off state nor allow a
channel to turn back on.
FAULT RESPONSES
COMMAND NAME
CMD
DEFAULT
VALUE
REF
PAGE
VOUT_OV_FAULT_RESPONSE 0x41 Action to be taken by the device when an
output overvoltage fault is detected.
VOUT_UV_FAULT_RESPONSE 0x45 Action to be taken by the device when an
output undervoltage fault is detected.
R/W Byte Y Reg Y 0x7F 55
IOUT_OC_FAULT_RESPONSE 0x47 Action to be taken by the device when an
output overcurrent fault is detected.
IOUT_UC_FAULT_RESPONSE 0x4C Action to be taken by the device when an
output undercurrent fault is detected.
OT_FAULT_RESPONSE 0x50 Action to be taken by the device when an
overtemperature fault is detected on the
UT_FAULT_RESPONSE 0x54 Action to be taken by the device when an
undertemperature fault is detected on the
VIN_OV_FAULT_RESPONSE 0x56 Action to be taken by the device when an
input overvoltage fault is detected.
VIN_UV_FAULT_RESPONSE 0x5A Action to be taken by the device when an
input undervoltage fault is detected.
TON_MAX_FAULT_RESPONSE 0x63 Action to be taken by the device when a
TON_MAX_FAULT event is detected.
MFR_RETRY_DELAY 0xDB Retry interval during FAULT retry mode. R/W Word N L11 mS Y 200
0xF320
58
MFR_RETRY_COUNT 0xF7 Retry count for all faulted off conditions
that enable retry.
R/W Byte N U16 Y 0x00 58
LTC2974
55
2974f
VOUT_OV_FAULT_RESPONSE and VOUT_UV_FAULT_RESPONSE
The fault response documented here is for voltages that are measured by the high speed supervisor. These voltages
are measured over a short period of time and may require a deglitch period. Note that in addition to the response
described by these commands, the LTC2974 will also:
Set the appropriate bit(s) in the STATUS_BYTE.
Set the appropriate bit(s) in the STATUS_WORD.
Set the appropriate bit in the corresponding STATUS_VOUT register, and
Notify the host by pulling the ALERTB pin low.
VOUT_OV_FAULT_RESPONSE and VOUT_UV_FAULT_RESPONSE Data Contents
b[7:6] Vout_ov_fault_response_action,
Vout_uv_fault_response_action
Response action:
00b: The unit continues operation without interruption.
01b: The unit continues operating for the delay time specified by bits[2:0] in increments of t
S_VS
. See
Electrical Characteristics Table. If the fault is still present at the end of the delay time, the unit shuts down
immediately or sequences off after TOFF_DELAY (See Mfr_config_track_enn). After shutting down, the device
responds according to the retry settings in bits [5:3].
10b-11b: The unit shuts down immediately or sequences off after TOFF_DELAY (See Mfr_config_track_enn).
After shutting down, the device responds according to the retry settings in bits [5:3].
b[5:3] Vout_ov_fault_response_retry,
Vout_uv_fault_response_retry
Response retry behavior:
000b: A zero value for the retry setting means that the unit does not attempt to restart. The output remains
disabled until the fault is cleared.
001b-111b: The PMBus device attempts to restart the number of times specified by the global Mfr_retry_
count[2:0] until it is commanded OFF (by the CONTROL pin or OPERATION command or both), bias power is
removed, or another fault condition causes the unit to shut down.
b[2:0] Vout_ov_fault_response_delay,
Vout_uv_fault_response_delay
This sample count determines the amount of time a unit is to ignore a fault after it is first detected. Use this
delay to deglitch fast faults.
000b: There is no additional deglitch delay applied to fault detection.
001b-111b: The fault is deglitched for deglitch period of b[2:0] samples at a sampling period of tS_VS
(12.2s typical).
LTC2974
56
2974f
IOUT_OC_FAULT_RESPONSE and IOUT_UC_FAULT_RESPONSE
The fault response documented here is for currents that are measured by the high speed supervisor. These currents
are measured over a short period of time and may require a deglitch period. Note that in addition to the response
Set the appropriate bit in the STATUS_BYTE.
Set the appropriate bit in the STATUS_WORD.
Set the appropriate bit in the corresponding STATUS_IOUT register, and
IOUT_OC_FAULT_RESONSE and IOUT_UC_FAULT_RESPONSE Data Contents
b[7:6] Iout_oc_fault_response_action,
Iout_uc_fault_response_action
Response action:
00b and 01b: The unit continues operation without interruption. Note that the current will not be limited to the
value of Iout_oc_fault_limit or Iout_uc_fault_limit.
10b: The unit continues operating for the delay time specified by bits [2:0]. If the fault is still present at the
end of the delay time, the unit shuts down immediately or sequences off after TOFF_DELAY (See Mfr_config_
track_enn). After shutting down, the device responds according to the retry settings in bits [5:3]. Note that
the current will not be limited to the value of Iout_oc_fault_limit or Iout_uc_fault_limit.
11b: The unit shuts down immediately or sequences off after TOFF_DELAY (See Mfr_config_track_enn). After
shutting down, the device responds according to the retry settings in bits [5:3].
b[5:3] Iout_oc_fault_response_retry,
Iout_uc_fault_response_retry
001-111b: The PMBus device attempts to restart the number of times specified by the global Mfr_retry_
count[2:0] until it is commanded off (by the control pin or operation command or both), bias power is
b[2:0] Iout_oc_fault_response_delay,
Iout_uc_fault_response_delay
This sample count determines the amount of time a unit is to ignore a fault after it is first detected. Use this
delay to deglitch fast faults.
000b: There is no additional deglitch delay applied to fault detection.
001b-111b: The fault is deglitched for the interval selected by b[2:0] as follows.
b[2:0] Deglitch interval
001b 100s
010b 1ms
011b 5ms
100b 10ms
101b 20ms
110b 50ms
111b 100ms
LTC2974
57
2974f
OT_FAULT_RESPONSE, UT_FAULT_RESPONSE, VIN_OV_FAULT_RESPONSE and VIN_UV_FAULT_RESPONSE
The fault response documented here is for values that are measured by the ADC. Note that in addition to the response
Set the appropriate bit(s) in the STATUS_BYTE.
Set the appropriate bit(s) in the STATUS_WORD.
Set the appropriate bit in the corresponding STATUS_VIN or STATUS_TEMPERATURE register, and
OT_FAULT_RESPONSE, UT_FAULT_RESPONSE, VIN_OV_FAULT_RESPONSE, VIN_UV_FAULT_RESPONSE Data Contents
b[7:6] Ot_fault_response_action,
Ut_fault_response_action,
Vin_ov_fault_response_action,
Vin_uv_fault_response_action
Response action:
b[5:3] Ot_fault_response_retry,
Ut_fault_response_retry,
Vin_ov_fault_response_retry,
Vin_uv_fault_response_retry
b[2:0] Ot_fault_response_delay,
Ut_fault_response_delay,
Vin_ov_fault_response_delay,
Vin_uv_fault_response_delay
Hard coded to 000b: There is no additional deglitch delay applied to fault detection.
LTC2974
58
2974f
TON_MAX_FAULT_RESPONSE
This command defines the LTC2974 response to a TON_MAX_FAULT. It may be used to protect against a short-circuited
output at startup. After startup use VOUT_UV_FAULT_RESPONSE to protect against a short-circuited output.
The device also:
Sets the HIGH_BYTE bit in the STATUS_BYTE,
Sets the VOUT bit in the STATUS_WORD,
Sets the TON_MAX_FAULT bit in the STATUS_VOUT register, and
Notifies the host by asserting ALERTB.
TON_MAX_FAULT_RESPONSE Data Contents
b[7:6] Ton_max_fault_response_action Response action:
b[5:3] Ton_max_fault_response_retry Response retry behavior:
b[2:0] Ton_max_fault_response_delay Hard coded to 000b: There is no additional deglitch delay applied to fault detection.
MFR_RETRY_DELAY
This command determines the retry interval when the LTC2974 is in retry mode in response to a fault condition. This
delay is counted using SHARE_CLK only. This delay is internally limited to 13.1 seconds, and rounded to the nearest
200s. The read value of this command always returns what was last written and does not reflect internal limiting.
MFR_RETRY_COUNT
The MFR_RETRY_COUNT is a global command that sets the number of retries attempted when any channel faults off
with its fault response retry field set to a non zero value.
In the event of multiple or recurring retry faults on the same channel the total number of retries equals MFR_RETRY_
COUNT. If a channel has not been faulted off for at least 16 seconds, its retry counter is cleared. Toggling a channels
CONTROL pin off then on or issuing OPERATION off then on commands will synchronously clear the retry count.
MFR_RETRY_COUNT Data Contents
b[7:3] Reserved Always returns zero.
b[2:0] Mfr_retry_count [2:0] 0: No retries:
1-6: Number of retries.
7: Infinite retries.
LTC2974
59
2974f
MFR_FAULTB0_PROPAGATE and MFR_FAULTB1_PROPAGATE
These manufacturer specific commands enable channels that have faulted off to propagate that state to the appro-
priate fault pin. MFR_FAULTB0_PROPAGATE allows any channels faulted off state to propagate to the FAULTB0 pin.
MFR_FAULTB1_PROPAGATE allows any channels faulted off state to propagate to the FAULTB1 pin.
Note that pulling a fault pin low will have no affect for channels that have MFR_FAULTBn_RESPONSE set to 0. The
channel continues operation without interruption. This fault response is called Action->Ignore in LTpowerPlay.
MFR_FAULT0_PROPAGATE Data Contents
b[0] Mfr_faultb0_propagate Enable fault propagation.
0: Channels faulted off state does not assert FAULTB0 low.
1 :Channels faulted off state asserts FAULTB0 low.
MFR_FAULT1_PROPAGATE Data Contents
b[0] Mfr_faultb1_propagate Enable fault propagation.
0: Channels faulted off state does not assert FAULTB1 low.
1: Channels faulted off state asserts FAULTB1 low.
SHARED EXTERNAL FAULTS
COMMAND NAME
CMD
DEFAULT
VALUE
REF
PAGE
FAULTB0 pin.
FAULTB1 pin.
LTC2974
60
2974f
MFR_FAULTB0_RESPONSE and MFR_FAULTB1_RESPONSE
These manufacturer specific commands share the same format and specify the response to assertions of the FAULTB
pins. MFR_FAULTB0_RESPONSE determines which channels shut off when the FAULTB0 pin is asserted low and
MFR_FAULTB1_RESPONSE determines which channels shut off when the FAULTB1 pin is asserted low.When a chan-
nel shuts off in response to a FAULTBn pin, the ALERTB pin is asserted low and the appropriate bit is set in the STA-
TUS_MFR_SPECIFIC register. For a graphical explanation, see the switches on the left hand side of Figure 28: Channel
Fault Management Block Diagram.
Faults will not propagate for channels that have MFR_FAULTBn_RESPONSE set to 0: The channel continues operation
without interruption. Note that this fault response is called No Action in LTpowerPlay.
MFR_FAULTB0_RESPONSE and MFR_FAULTB1_RESPONSE Data Contents
b[7:4] Reserved Read only, always returns 0000b.
b[3] Mfr_faultb0_response_chan3,
Mfr_faultb1_response_chan3
Channel 3 response.
0: The channel continues operation without interruption
1: The channel shuts down if the corresponding FAULTB pin is still asserted after 10s. When the FAULTB pin
subsequently de-asserts, the channel turns back on, honoring TON_DELAY and TON_RISE settings.
Channel 2 response.
Channel 1 response.
Channel 0 response.
LTC2974
61
2974f
CLEAR_FAULTS
The CLEAR_FAULTS command is used to clear status bits that have been set. This command clears all fault and warn-
ing bits in all unpaged status registers, and paged status registers selected by the current PAGE setting. At the same
time, the device negates (clears, releases) its contribution to ALERTB.
The CLEAR_FAULTS command does not cause a unit that has latched off for a fault condition to restart. See Clearing
Latched Faults for more information.
If the fault is present after the fault is cleared, the fault status bit shall be set again and the host notified by the usual
means.
Note: this command responds to the global page command. (PAGE=0xFF)
STATUS_BYTE
The STATUS_BYTE command returns the summary of the most critical faults or warnings which have occurred, as
shown in the following table. STATUS_BYTE is a subset of STATUS_WORD and duplicates the same information.
STATUS_BYTE Data Contents
b[7] Status_byte_busy Same as Status_word_busy.
b[6] Status_byte_off Same as Status_word_off.
b[5] Status_byte_vout_ov Same as Status_word_vout_ov.
b[4] Status_byte_iout_oc Same as Status_word_iout_oc.
b[3] Status_byte_vin_uv Same as Status_word_vin_uv.
b[2] Status_byte_temp Same as Status_word_temp.
b[1] Status_byte_cml Same as Status_word_cml.
b[0] Status_byte_high_byte Same as Status_word_high_byte.
FAULT WARNING AND STATUS
COMMAND NAME
CMD
DEFAULT
VALUE
REF
PAGE
CLEAR_FAULTS 0x03 Clear any fault bits that have been set. Send Byte Y NA 61
STATUS_BYTE 0x78 One byte summary of the units fault condition. R Byte Y Reg NA 61
STATUS_WORD 0x79 Two byte summary of the units fault condition. R Word Y Reg NA 62
STATUS_VOUT 0x7A Output voltage fault and warning status. R Byte Y Reg NA 62
STATUS_IOUT 0x7B Output current fault and warning status. R Byte Y Reg NA 63
STATUS_INPUT 0x7C Input supply fault and warning status. R Byte N Reg NA 63
STATUS_TEMPERATURE 0x7D External temperature fault and warning status for
READ_TEMPERATURE_1.
R Byte Y Reg NA 63
STATUS_CML 0x7E Communication and memory fault and warning
status.
R Byte N Reg NA 64
STATUS_MFR_SPECIFIC 0x80 Manufacturer specific fault and state information. R Byte Y Reg NA 64
MFR_PADS 0xE5 Current state of selected digital I/O pads. R/W Word N Reg NA 65
MFR_COMMON 0xEF Manufacturer status bits that are common across
multiple LTC chips.
R Byte N Reg NA 65
LTC2974
62
2974f
STATUS_WORD
The STATUS_WORD command returns two bytes of information with a summary of the units fault condition. Based on
the information in these bytes, the host can get more information by reading the appropriate detailed status register.
The low byte of the STATUS_WORD is the same register as the STATUS_BYTE command.
STATUS_WORD Data Contents
b[15] Status_word_vout An output voltage fault or warning has occurred. See STATUS_VOUT.
b[14] Status_word_iout An output current fault or warning has occurred. See STATUS_IOUT.
b[13] Status_word_input An input voltage fault or warning has occurred. See STATUS_INPUT.
b[12] Status_word_mfr A manufacturer specific fault has occurred. See STATUS_MFR._SPECIFIC.
b[11] Status_word_power_not_good The PWRGD signal is negated. Power is not good.
b[10] Status_word_fans Not supported. Always
returns 0.
b[9] Status_word_other Not supported. Always
returns 0.
b[8] Status_word_unknown Not supported. Always
returns 0.
b[7] Status_word_busy Device busy when PMBus command received. See OPERATION: Processing Commands.
b[6] Status_word_off This bit is asserted if the unit is not providing power to the output, regardless of the reason, including simply
not being enabled. The off-bit is clear if unit is allowed to provide power to the output.
b[5] Status_word_vout_ov An output overvoltage fault has occurred.
b[4] Status_word_iout_oc An output overcurrent fault has occurred.
b[3] Status_word_vin_uv A V
IN
undervoltage fault has occurred.
b[2] Status_word_temp A temperature fault or warning has occurred. See STATUS_TEMPERATURE.
b[1] Status_word_cml A communication, memory or logic fault has occurred. See STATUS_CML.
b[0] Status_word_high_byte A fault/warning not listed in b[7:1] has occurred.
STATUS_VOUT
The STATUS_VOUT command returns the summary of the output voltage faults or warnings which have occurred, as
shown in the following table:
STATUS_VOUT Data Contents
b[7] Status_vout_ov_fault Overvoltage fault.
b[6] Status_vout_ov_warn Overvoltage warning.
b[5] Status_vout_uv_warn Undervoltage warning
b[4] Status_vout_uv_fault Undervoltage fault.
b[3] Status_vout_max_fault VOUT_MAX fault. An attempt has been made to set the output voltage to a value higher than allowed by the
VOUT_MAX command.
b[2] Status_vout_ton_max_fault TON_MAX_FAULT sequencing fault.
b[1] Status_vout_toff_max_warn Not supported. Always returns 0.
b[0] Status_vout_tracking_error Not supported. Always returns 0.
LTC2974
63
2974f
STATUS_IOUT
The STATUS_IOUT command returns the summary of the output current faults or warnings which have occurred, as
shown in the following table:
STATUS_IOUT Data Contents
b[7] Status_iout_oc_fault Overcurrent fault.
b[6] Status_iout_oc_uv_fault Not Supported. Always returns 0.
b[5] Status_iout_oc_warn Overcurrent warning
b[4] Status_iout_uc_fault Undercurrent fault.
b[3] Status_iout_curr_share_fault Not Supported. Always returns 0.
b[2] Status_pout_power_limiting Not Supported. Always returns 0.
b[1] Status_pout_overpower_fault Not Supported. Always returns 0.
b[0] Status_pout_overpower_warn Not Supported. Always returns 0.
STATUS_INPUT
The STATUS_INPUT command returns the summary of the V
IN
faults or warnings which have occurred, as shown in
the following table:
STATUS_INPUT Data Contents
b[7] Status_input_ov_fault V
IN
overvoltage fault
b[6] Status_input_ov_warn V
IN
overvoltage warning
b[5] Status_input_uv_warn V
IN
undervoltage warning
b[4] Status_input_uv_fault V
IN
undervoltage fault
b[3] Status_input_off Unit is off for insufficient input voltage.
b[2] IIN overcurrent fault Not supported. Always returns 0.
b[1] IIN overcurrent warn Not supported. Always returns 0.
b[0] PIN overpower warn Not supported. Always returns 0.
STATUS_TEMPERATURE
The STATUS_TEMPERATURE command returns the summary of the temperature faults or warnings which have oc-
curred, as shown in the following table. Note that this information is paged and refers to the temperature of the as-
sociated external diode.
STATUS_TEMPERATURE Data Contents
b[7] Status_temperature_ot_fault Overtemperature fault.
b[6] Status_temperature_ot_warn Overtemperature warning.
b[5] Status_temperature_ut_warn Undertemperature warning.
b[4] Status_temperature_ut_fault Undertemperature fault.
b[3] Reserved Reserved. Always returns 0.
LTC2974
64
2974f
STATUS_CML
The STATUS_CML command returns the summary of the communication, memory and logic faults or warnings which
have occurred, as shown in the following table:
STATUS_CML Data Contents
b[7] Status_cml_cmd_fault 1 = An illegal or unsupported command fault has occurred.
0 = No fault has occurred.
b[6] Status_cml_data_fault 1 = Illegal or unsupported data received.
b[5] Status_cml_pec_fault 1 = A packet error check fault has occurred. Note: PEC checking is always active in the LTC2974. Any extra byte
received before a STOP will set Status_cml_pec_fault unless the extra byte is a matching PEC byte.
b[4] Status_cml_memory_fault 1 = A fault has occurred in the EEPROM.
b[3] Status_cml_processor_fault Not supported, always returns 0.
b[2] Reserved Reserved, always returns 0.
b[1] Status_cml_pmbus_fault 1 = A communication fault other than ones listed in this table has occurred. This is a catch all category for illegally
formed I
2
C/SMBus commands (Example: An address byte with read =1 received immediately after a START).
b[0] Status_cml_unknown_fault Not supported, always returns 0.
STATUS_MFR_SPECIFIC
The STATUS_MFR_SPECIFIC command returns manufacturer specific status flags. Bits marked FAULT = No are intended
to support polled handshaking; these are not latched nor do they assert ALERTB. Bits marked FAULT = Yes assert
ALERTB low and are cleared by CLEAR_FAULTS. Bits marked Channel = All can be read from any page.
STATUS_MFR_SPECIFIC Data Contents
BIT(S) SYMBOL OPERATION CHANNEL FAULT
b[7] Status_mfr_discharge 1 = A V
OUT
discharge fault occurred while attempting to enter the ON state.
0 = No V
OUT
discharge fault has occurred.
Current Page Yes
b[6] Status_mfr_fault1_in This channel attempted to turn on while the FAULTB1 pin was asserted low, or
this channel has shut down at least once in response to a FAULTB1 pin asserting
low since the last CONTROL pin toggle, OPERATION command ON/OFF cycle or
CLEAR_FAULTS command.
Current Page Yes
b[5] Status_mfr_fault0_in This channel attempted to turn on while the FAULTB0 pin was asserted low, or
this channel has shut down at least once in response to a FAULTB0 pin asserting
low since the last CONTROL pin toggle, OPERATION command ON/OFF cycle or
CLEAR_FAULTS command.
Current Page Yes
b[4] Status_mfr_servo_target_reached Servo target has been reached. Current Page No
b[3] Status_mfr_dac_connected DAC is connected and driving V
DAC
pin. Current Page No
b[2] Status_mfr_dac_saturated A previous servo operation terminated with maximum or minimum DAC value. Current Page Yes
b[1] Status_mfr_auxfaultb_faulted_off AUXFAULTB has been de-asserted due to a V
OUT
or I
OUT
fault. All No
b[0] Status_mfr_watchdog_fault 1 = A watchdog fault has occurred.
0 = No watchdog fault has occurred.
All Yes
LTC2974
65
2974f
MFR_PADS
The MFR_PADS command provides read-only access of digital pads. The input values are before any deglitching logic.
MFR_PADS Data Contents
b[15] Mfr_pads_pwrgd_drive 0 = PWRGD pad is being driven low by this chip.
1 = PWRGD pad is not being driven low by this chip.
b[14] Mfr_pads_alertb_drive 0 = ALERTB pad is being driven low by this chip.
1 = ALERTB pad is not being driven low by this chip.
b[13:12] Mfr_pads_faultb_drive[1:0] bit[1] used for FAULTB0 pad, bit[0] used for FAULTB1 pad as follows:
0 = FAULTB pad is being driven low by this chip.
1 = FAULTB pad is not being driven low by this chip.
b[11:10] Reserved[1:0] Always returns 00b.
b[9:8] Mfr_pads_asel1[1:0] 11: Logic high detected on ASEL1 input pad.
10: ASEL1 input pad is floating.
01: Reserved.
00: Logic low detected on ASEL1 input pad.
b[7:6] Mfr_pads_asel0[1:0] 11: Logic high detected on ASEL0 input pad.
10: ASEL0 input pad is floating.
01: Reserved.
00: Logic low detected on ASEL0 input pad.
b[5] Mfr_pads_control1 1: Logic high detected on CONTROL1 pad.
0: Logic low detected on CONTROL1 pad.
b[3:2] Mfr_pads_faultb[1:0] bit[1] used for FAULTB0 pad, bit[0] used for FAULTB1 pad as follows:
1: Logic high detected on FAULTB pad.
0: Logic low detected on FAULTB pad.
MFR_COMMON
This command returns status information for the alert, device busy, share-clock pin (SHARE_CLK) and the write-protect
pin (WP).
This is the only command that may still be read when the LTC2974 is busy processing an EEPROM or other command.
It may be polled by the host to determine when the LTC2974 is available to process a PMBus command. A busy device
will always acknowledge its address but will NACK the command byte and set Status_byte_busy and Status_word_busy
when it receives a command that it cannot immediately process.
LTC2974
66
2974f
MFR_COMMON Data Contents
b[7] Mfr_common_alertb Returns alert status.
1: ALERTB is de-asserted high.
0: ALERTB is asserted low.
b[6] Mfr_common_busyb Returns device busy status.
1: The device is available to process PMBus commands.
0: The device is busy and will NACK PMBus commands.
b[1] Mfr_common_share_clk Returns the status of the share-clock pin.
1: Share-clock pin is being held low.
0: Share-clock pin is active.
b[0] Mfr_common_write_protect Returns the status of the write-protect pin.
1: Write-protect pin is high.
0: Write-protect pin is low.
TELEMETRY
COMMAND NAME
CMD
DEFAULT
VALUE
REF
PAGE
READ_VIN 0x88 Input supply voltage. R Word N L11 V NA 67
READ_VOUT 0x8B DC/DC converter output voltage. R Word Y L16 V NA 67
READ_IOUT 0x8C DC/DC converter output current. R Word Y L11 A NA 67
READ_TEMPERATURE_1 0x8D External diode junction temperature. This
is the value used for all temperature related
processing, including IOUT_CAL_GAIN.
READ_TEMPERATURE_2 0x8E Internal junction temperature. R Word N L11 C NA 67
READ_POUT 0x96 DC/DC converter output power. R Word Y L11 W NA 67
MFR_READ_IOUT 0xBB Alternate data format for READ_IOUT. One
LSB = 2.5mA.
R Word Y CF 2.5mA NA 67
MFR_IOUT_SENSE_VOLTAGE 0xFA Absolute value of VISENSEP VISENSEM.
One LSB = 3.05V.
R Word Y CF 3.05V NA 68
MFR_VIN_PEAK 0xDE Maximum measured value of READ_VIN. R Word N L11 V NA 69
MFR_VOUT_PEAK 0xDD Maximum measured value of READ_VOUT. R Word Y L16 V NA 69
MFR_IOUT_PEAK 0xD7 Maximum measured value of READ_IOUT. R Word Y L11 A NA 69
MFR_TEMPERATURE_1_PEAK 0xDF Maximum measured value of READ_
TEMPERATURE_1.
MFR_VIN_MIN 0xFC Minimum measured value of READ_VIN. R Word N L11 V NA 69
MFR_VOUT_MIN 0xFB Minimum measured value of READ_VOUT. R Word Y L16 V NA 69
MFR_IOUT_MIN 0xD8 Minimum measured value of READ_IOUT. R Word Y L11 A NA 69
MFR_TEMPERATURE_1_MIN 0xFD Minimum measured value of READ_
TEMPERATURE_1.
LTC2974
67
2974f
READ_VIN
This command returns the most recent ADC measured value of the input voltage at the V
IN_SNS
pin.
READ_VOUT
This command returns the most recent ADC measured value of the channels output voltage.
READ_IOUT
This command returns the most recent ADC measured value of the channels output current.
READ_TEMPERATURE_1
This command returns the most recent measured value of the external diode temperature in C. This value is used for
all temperature related operations and calculations. This command is paged. READ_TEMPERATURE_2 is substituted
for READ_TEMPERATURE_1 if the associated T
SENSE
network fails to detect a valid temperature.
The T
SENSE
network will fail to detect a valid temperature under the following conditions:
The T
SENSE
pin is shorted to a constant voltage.
The sense diode has an ideality factor greater than N_TS max.
Floating the T
SENSE
pin is not recommended and may return unpredictable temperature values.
READ_TEMPERATURE_2
This command returns the most recent ADC measured value of junction temperature in C as determined by the
LTC2974s internal temperature sensor. This register is for information purposes and does not generate any faults,
warnings, or affect any other registers or internal calculations unless it is used as READ_TEMPERATURE_1. This
command is not paged.
READ_TEMPERATURE_2 is substituted for READ_TEMPERATURE_1 if a channels T
SENSE
network fails to detect a
valid temperature.
READ_POUT
This command returns the most recent ADC measured value of the channels output power in watts.
MFR_READ_IOUT
This command returns the most recent ADC measured value of the channels output current, using a custom format
that provides better numeric representation granularity than the READ_IOUT command for currents whose absolute
value is between 2A and 82A.
LTC2974
68
2974f
MFR_READ_IOUT Data Contents
b[15:0] Mfr_read_iout[15:0] Channel output current expressed in custom format for improved resolution at high currents.
Value = Y 2.5 where Y = b[15:0] is a signed twos-complement number.
Example:
MFR_READ_IOUT = 5mA
For b[15:0] = 0x0002
Value = 2 2.5 = 5mA
The granularity of the returned value is always 2.5mA, and the return value is limited to 81.92A. Use the READ_IOUT
command for larger currents. Note that the accuracy of the returned value is always limited by the ADC Characteristics
listed in the Electrical Characteristics section.
Comparison of Granularity Due to Numeric Format
CURRENT RANGE
READ_IOUT
GRANULARITY
MFR_READ_IOUT
GRANULARITY
31.25mA I
OUT
< 62.5mA 61A 2.5mA
62.5mA I
OUT
< 125mA 122A 2.5mA
125mA I
OUT
< 250mA 244A 2.5mA
250mA I
OUT
< 500mA 488A 2.5mA
0.5A I
OUT
< 1A 977A 2.5mA
1A I
OUT
< 2A 1.95mA 2.5mA
2A I
OUT
< 4A 3.9mA 2.5mA
4A I
OUT
< 8A 7.8mA 2.5mA
8A I
OUT
< 16A 15.6mA 2.5mA
16A I
OUT
< 32A 31.3mA 2.5mA
32A I
OUT
< 64A 62.5mA 2.5mA
64A I
OUT
< 82A 125mA 2.5mA
82A I
OUT
< 128A 125mA Saturated
128A I
OUT
< 256A 250mA Saturated
MFR_IOUT_SENSE_VOLTAGE
This command returns the absolute value of the voltage measured between I
SENSEPn
and I
SENSEMn
during the last
READ_IOUT ADC conversion without any temperature correction.
MFR_IOUT_SENSE_VOLTAGE Data Contents
b[15:0] Mfr_iout_sense_voltage Absolute value of raw voltage conversion measured between I
SENSEPn
and I
SENSEMn
.
Value = Y 0.025 2
13
where Y = b[15:0] is an unsigned integer.
Example:
MFR_IOUT_SENSE_VOLTAGE = 1.544mV
For b[15:0] = 0x1FA=506
Value = 506 0.025 2
13
= 1.544mV
LTC2974
69
2974f
MFR_VIN_PEAK
This command returns the maximum ADC measured value of the input voltage. This register is reset to 0x7C00
(2
25
) when the LTC2974 emerges from power-on reset or when a CLEAR_FAULTS command is executed.
MFR_VOUT_PEAK
This command returns the maximum ADC measured value of the channels output voltage. This register is reset to
0xF800 (0.0) when the LTC2974 emerges from power-on reset or when a CLEAR_FAULTS command is executed.
MFR_IOUT_PEAK
This commands returns the maximum ADC measured value of the channels output current. This register is reset to
0x7C00 (2
25
MFR_TEMPERATURE_1_PEAK
This command returns the maximum measured value of the external diode temperature in C. This register is reset
to 0x7C00 (2
25
MFR_VIN_MIN
This command returns the minimum ADC measured value of the input voltage. This register is reset to 0x7BFF (ap-
proximately 2
25
MFR_VOUT_MIN
This command returns the minimum ADC measured value of the channels output voltage. This register is reset to
0xFFFF (7.9999) when the LTC2974 emerges from power-on reset or when a CLEAR_FAULTS command is executed.
MFR_IOUT_MIN
This command returns the minimum ADC measured values of the channels output current. This register is reset to
0x7BFF (approximately 2
25
) when the LTC2974 emerges from power-on reset or when a CLEAR_FAULTS command
is executed.
MFR_TEMPERATURE_1_MIN
This command returns the minimum measured value of the external diode temperature in C. This register is reset to
0x7BFF (approximately 2
25
) when the LTC2974 emerges from power-on reset or when a CLEAR_FAULTS command
is executed.
LTC2974
70
2974f
Fault Log Operation
A conceptual diagram of the fault log is shown in Figure 22. The fault log provides black box capability for the LTC2974.
During normal operation the contents of the status registers, the output voltage/current/temperature readings, the
input voltage readings, as well as peak and min values of these quantities, are stored in a continuously updated buffer
in RAM. You can think of the operation as being similar to a strip chart recorder. When a fault occurs, the contents are
written into EEPROM for non volatile storage. The EEPROM fault log is then locked. The part can be powered down
with the fault log available for reading at a later time.
Figure 22: Fault Logging
TIME OF FAULT
TRANSFER TO EEPROM
AND LOCK
ADC READINGS
CONTINUOUSLY
FILL BUFFER
EEPROM
255 BYTES
2974 F22
RAM
255 BYTES
AFTER FAULT
READ FROM EEPROM
AND LOCK BUFFER
MFR_FAULT_LOG_STORE
This command allows the user to transfer data from the RAM buffer to EEPROM.
MFR_FAULT_LOG_RESTORE
This command allows the user to transfer a copy of the fault-log data from the EEPROM to the RAM buffer. After a
restore the RAM buffer is locked until a successful Mfr_fault_log read.
FAULT LOGGING
COMMAND NAME
CMD
DEFAULT
VALUE
REF
PAGE
MFR_FAULT_LOG_STORE 0xEA Command a transfer of the fault log from RAM
to EEPROM.
Send Byte N NA 70
MFR_FAULT_LOG_RESTORE 0xEB Command a transfer of the fault log previously
stored in EEPROM back to RAM.
Send Byte N NA 70
MFR_FAULT_LOG_CLEAR 0xEC Initialize the EEPROM block reserved for fault
logging and clear any previous fault logging
locks.
Send Byte N NA 71
MFR_FAULT_LOG_STATUS 0xED Fault logging status. R Byte N Reg Y NA 71
MFR_FAULT_LOG 0xEE Fault log data bytes. This sequentially retrieved
data is used to assemble a complete fault log.
R Block N Reg Y NA 71
LTC2974
71
2974f
MFR_FAULT_LOG_CLEAR
This command initializes the EEPROM block reserved for fault logging. Any previous fault log stored in EEPROM will
be erased by this operation.
MFR_FAULT_LOG_STATUS
This register is used to manage fault log events. The Mfr_fault_log_status_eeprom bit is set after a MFR_FAULT_LOG_
STORE command or a faulted-off event triggers a transfer of the fault log from RAM to EEPROM. This bit is cleared
by a MFR_FAULT_LOG_CLEAR command.
Mfr_fault_log_Status_ram is set after a MFR_FAULT_ LOG_RESTORE to indicate that the data in the RAM has been
restored from EEPROM and not yet read using a MFR_FAULT_LOG command. This bit is cleared only by a successful
execution of an MFR_FAULT_LOG command.
MFR_FAULT_LOG_STATUS Data Contents
b[1] Mfr_fault_log_Status_ram Fault log RAM status:
0: The fault log RAM allows updates.
1: The fault log RAM is locked until the next Mfr_fault_log read.
b[0] Mfr_fault_log_Status_eeprom Fault log EEPROM status:
0: The transfer of the fault log RAM to the EEPROM is enabled.
1: The transfer of the fault log RAM to the EEPROM is inhibited.
MFR_FAULT_LOG
Read only. This 2040-bit (255 byte) data block contains a copy of the RAM buffer fault log. The RAM buffer is continu-
ously updated after each ADC conversion as long as Mfr_fault_log_Status_ram is clear.
With Mfr_config_fault_log_en = 1 and Mfr_fault_log_Status_eeprom = 0, the RAM buffer is transferred to EEPROM
whenever an LTC2974 fault causes a channel to latch off or a MFR_FAULT_LOG_STORE command is received. This
transfer is delayed until the ADC has updated its READ values for all channels when Mfr_config_all_fast_fault_log is
clear, otherwise it happens within 24ms. This optional delay can be used to ensure that the slower ADC monitored
values are all updated for the case where a fast supervisor detected fault initiates the transfer to EEPROM.
Mfr_fault_log_Status_eeprom is set high after the RAM buffer is transferred to EEPROM and not cleared until a
Mfr_fault_log_clear is received, even if the LTC2974 is reset or powered down. Fault log EEPROM transfers are not
initiated as a result of Status_mfr_discharge events.
During a Mfr_fault_log read, data is returned one byte at a time as defined in Table 2. The fault log data is partitioned
into two sections. The first section is referred to as the preamble and contains the Position_last pointer, time information
and peak and min values. The second section contains a chronological record of telemetry and requires Position_last
for proper interpretation. The fault log stores approximately 300ms seconds of telemetry. To prevent timeouts during
block reads, it is recommended that Mfr_config_all_longer_pmbus_timeout be set to 1.
LTC2974
72
2974f
Table 2. Data Block Contents
DATA BYTE* DESCRIPTION
Position_last[7:0] 0 Position of fault log pointer when
fault occurred.
SharedTime[7:0] 1 41-bit share-clock counter value
when fault occurred. Counter
LSB is in 200s increments.
SharedTime[15:8] 2
SharedTime[23:16] 3
SharedTime[31:24] 4
SharedTime[39:32] 5
SharedTime[40] 6
Mfr_vout_peak0[7:0] 7
Mfr_vout_min0[7:0] 9
Mfr_temperature_peak0[7:0] 11
Mfr_temperature_min0[7:0] 13
Mfr_iout_peak0[7:0] 15
Mfr_iout_min0[7:0] 17
Mfr_vin_peak[7:0] 19
Mfr_vin_peak[15:8] 20
Mfr_vin_min[7:0] 21
Mfr_vin_min[15:8] 22
Status_vout0[7:0] 59
Status_iout0[7:0] 60
Status_mfr_specific0[7:0] 61
71 bytes for preamble
Fault_log [Position_last] 71
Fault_log [Position_last-1] 72
.
.
.
Fault_log [Position_last-170] 237
Reserved 238-
254
LTC2974
73
2974f
Number of loops: (238 67)/54
= 3.2
*Note that PMBus data byte numbers start at 1 rather than 0.
See Figure 13 Block Read.
The data returned between bytes 71 and 237 of the
previous table is interpreted using Position_last and the
following table. The key to identifying the data located in
byte 71 is to locate the DATA corresponding to POSITION
= Position_last in the next table. Subsequent bytes are
identified by decrementing the value of POSITION. For
example: If Position_last = 8 then the first data returned
in a block read is Status_temperature of page 0 followed
by Read_temperature_1[15:8] of page 0 followed by
Read_temperature_1[7:0] of page 0 and so on. See Table 3.
Table 3. Interpreting Cyclical Loop Data
POSITION DATA
0 Read_temperature_2[7:0]
1 Read_temperature_2[15:8]
2 Read_vout0[7:0]
3 Read_vout0[15:8]
4 Status_vout0[7:0]
5 Status_mfr_specific0[7:0]
6 Read_temperature_1_0[7:0]
8 Status_temperature0[7:0]
9 Status_iout0[7:0]
10 Read_iout0[7:0]
11 Read_iout0[15:8]
12 Read_pout0[7:0]
13 Read_pout0[15:8]
14 Read_vin[7:0]
15 Read_vin[15:8]
16 Status_input[7:0]
17 0x0
18 Read_vout1[7:0]
POSITION DATA
19 Read_vout1[15:8]
20 Status_vout1[7:0]
25 Status_iout1[7:0]
26 Read_iout1[7:0]
27 Read_iout1[15:8]
28 Read_pout1[7:0]
29 Read_pout1[15:8]
30 Read_vout2[7:0]
31 Read_vout2[15:8]
38 Read_iout2[7:0]
39 Read_iout2[15:8]
40 Read_pout2[7:0]
41 Read_pout2[15:8]
42 Read_vout3[7:0]
43 Read_vout3[15:8]
50 Read_iout3[7:0]
51 Read_iout3[15:8]
52 Read_pout3[7:0]
53 Read_pout3[15:8]
Total Bytes = 54
LTC2974
74
2974f
Data Block Contents
PREAMBLE INFORMATION
BYTE
NUMBER
DECIMAL
BYTE
NUMBER
HEX DATA DESCRIPTION
0 00 Position_last[7:0] = 13 Position of fault-
log pointer when
fault occurred.
1 01 SharedTime[7:0] 41-bit share-
clock counter
value when fault
occurred. Counter
LSB is in 200s
increments.
2 02 SharedTime[15:8]
6 06 SharedTime[40]
7 07 Mfr_vout_peak0[7:0]
9 09 Mfr_vout_min0[7:0]
10 0A Mfr_vout_min0[15:8]
11 0B Mfr_temperature_
peak0[7:0]

12 0C Mfr_temperature_
peak0[15:8]

13 0D Mfr_temperature_
min0[7:0]

14 0E Mfr_temperature_
min0[15:8]

15 0F Mfr_iout_peak0[7:0]
16 10 Mfr_iout_peak0[15:8]
17 11 Mfr_iout_min0[7:0]
19 13 Mfr_vin_peak_[7:0]
20 14 Mfr_vin_peak_[15:8]
21 15 Mfr_vin_min_[7:0]
22 16 Mfr_vin_min_[15:8]
26 1A Mfr_vout_min1[15:8]
27 1B Mfr_temperature_
peak1[7:0]

MFR_FAULT_LOG Read Example
The following table fully decodes a sample fault log read
with Position_last = 13 to help clarify the cyclical nature
of the operation.
BYTE
NUMBER
DECIMAL
BYTE
NUMBER
28 1C Mfr_temperature_
peak1[15:8]

29 1D Mfr_temperature_
min1[7:0]

30 1E Mfr_temperature_
min1[15:8]

31 1F Mfr_iout_peak1[7:0]
39 27 Mfr_temperature_
peak2[7:0]

peak2[15:8]

min2[7:0]

42 2A Mfr_temperature_
min2[15:8]

43 2B Mfr_iout_peak2[7:0]
44 2C Mfr_iout_peak2[15:8]
45 2D Mfr_iout_min2[7:0]
46 2E Mfr_iout_min2[15:8]
47 2F Mfr_vout_peak3[7:0]
peak3[7:0]
peak3[15:8]
min3[7:0]
min3[15:8]
58 3A Mfr_iout_min3[15:8]
59 3B Status_vout0[7:0]
LTC2974
75
2974f
BYTE
NUMBER
DECIMAL
BYTE
NUMBER
60 3C Status_iout0[7:0]
61 3D Status_
temperature0[7:0]
62 3E Status_vout1[7:0]
63 3F Status_iout1[7:0]
64 40 Status_
temperature1[7:0]
65 41 Status_vout2[7:0]
66 42 Status_iout2[7:0]
67 43 Status_
temperature2[7:0]
68 44 Status_vout3[7:0]
69 45 Status_iout3[7:0]
70 46 Status_
temperature3[7:0]
End of Preamble
CYCLICAL MUX LOOP DATA
BYTE
NUMBER
DECIMAL
BYTE
NUMBER
HEX
LOOP
BYTE
NUMBER
DECIMAL MUX LOOP 0
54 BYTES PER
LOOP
71 47 13 Read_pout0[15:8] Position_last
72 48 12 Read_pout0[7:0]
73 49 11 Read_iout0[15:8]
74 4A 10 Read_iout0[7:0]
75 4B 9 Status_iout0[7:0]
76 4C 8 Status_
temperature0[7:0]

77 4D 7 Read_
temperature_1_0[15:8]

78 4E 6 Read_

79 4F 5 Status_mfr_
specific0[7:0]

80 50 4 Status_vout0[7:0]
81 51 3 Read_vout0[15:8]
82 52 2 Read_vout0[7:0]
83 53 1 Read_
temperature_2[15:8]

84 54 0 Read_
temperature_2[7:0]

BYTE
NUMBER
DECIMAL
BYTE
NUMBER
HEX
LOOP
BYTE
NUMBER
DECIMAL MUX LOOP 1
54 BYTES PER
LOOP
85 55 53 Read_pout3[15:8]
86 56 52 Read_pout3[7:0]
87 57 51 Read_iout3[15:8]
88 58 50 Read_iout3[7:0]
89 59 49 Status_iout3[7:0]
90 5A 48 Status_
temperature3[7:0]

91 5B 47 Read_

92 5C 46 Read_

93 5D 45 Status_mfr_
specific3[7:0]

94 5E 44 Status_vout3[7:0]
95 5F 43 Read_vout3[15:8]
96 60 42 Read_vout3[7:0]
97 61 41 Read_pout2[15:8]
98 62 40 Read_pout2[7:0]
99 63 39 Read_iout2[15:8]
100 64 38 Read_iout2[7:0]
101 65 37 Status_iout2[7:0]
102 66 36 Status_
temperature2[7:0]

103 67 35 Read_

104 78 34 Read_

105 69 33 Status_mfr_
specific2[7:0]

106 6A 32 Status_vout2[7:0]
107 6B 31 Read_vout2[15:8]
108 6C 30 Read_vout2[7:0]
109 6D 29 Read_pout1[15:8]
110 6E 28 Read_pout1[7:0]
111 6F 27 Read_iout1[15:8]
112 70 26 Read_iout1[7:0]
113 71 25 Status_iout1[7:0]
114 72 24 Status_
temperature2[7:0]
115 73 23 Read_
LTC2974
76
2974f
BYTE
NUMBER
DECIMAL
BYTE
NUMBER
HEX
LOOP
BYTE
NUMBER
DECIMAL MUX LOOP 1
54 BYTES PER
LOOP
116 74 22 Read_
specific1[7:0]
118 76 20 Status_vout1[7:0]
119 77 19 Read_vout1[15:8]
120 78 18 Read_vout1[7:0]
121 79 17 0x0
122 7A 16 Status_input[7:0]
123 7B 15 Read_vin[15:8]
124 7C 14 Read_vin[7:0]
125 7D 13 Read_pout0[15:8]
126 7E 12 Read_pout0[7:0]
127 7F 11 Read_iout0[15:8]
128 80 10 Read_iout0[7:0]
129 81 9 Status_iout0[7:0]
130 82 8 Status_
temperature0[7:0]

131 83 7 Read_

132 84 6 Read_

specific0[7:0]

134 86 4 Status_vout0[7:0]
135 87 3 Read_vout0[15:8]
136 88 2 Read_vout0[7:0]
137 89 1 Read_
temperature_2[15:8]

138 8A 0 Read_
temperature_2[7:0]

BYTE
NUMBER
DECIMAL
BYTE
NUMBER
HEX
LOOP
BYTE
NUMBER
DECIMAL MUX LOOP 2
54 BYTES PER
LOOP
139 8B 53 Read_pout3[15:8]
140 8C 52 Read_pout3[7:0]
141 8D 51 Read_iout3[15:8]
142 8E 50 Read_iout3[7:0]
143 8F 49 Status_iout3[7:0]
BYTE
NUMBER
DECIMAL
BYTE
NUMBER
HEX
LOOP
BYTE
NUMBER
DECIMAL MUX LOOP 2
54 BYTES PER
LOOP
144 90 48 Status_
temperature3[7:0]

145 91 47 Read_

146 92 46 Read_

specific3[7:0]

148 94 44 Status_vout3[7:0]
149 95 43 Read_vout3[15:8]
150 96 42 Read_vout3[7:0]
151 97 41 Read_pout2[15:8]
152 98 40 Read_pout2[7:0]
153 99 39 Read_iout2[15:8]
154 9A 38 Read_iout2[7:0]
155 9B 37 Status_iout2[7:0]
156 9C 36 Status_
temperature2[7:0]

157 9D 35 Read_

158 9E 34 Read_

159 9F 33 Status_mfr_
specific2[7:0]

160 A0 32 Status_vout2[7:0]
161 A1 31 Read_vout2[15:8]
162 A2 30 Read_vout2[7:0]
163 A3 29 Read_pout1[15:8]
164 A4 28 Read_pout1[7:0]
165 A5 27 Read_iout1[15:8]
166 A6 26 Read_iout1[7:0]
167 A7 25 Status_iout1[7:0]
168 A8 24 Status_
temperature2[7:0]
169 A9 23 Read_
170 AA 22 Read_
171 AB 21 Status_mfr_
specific1[7:0]
172 AC 20 Status_vout1[7:0]
173 AD 19 Read_vout1[15:8]
LTC2974
77
2974f
BYTE
NUMBER
DECIMAL
BYTE
NUMBER
HEX
LOOP
BYTE
NUMBER
DECIMAL MUX LOOP 2
54 BYTES PER
LOOP
174 AE 18 Read_vout1[7:0]
175 AF 17 0x0
176 B0 16 Status_input[7:0]
177 B1 15 Read_vin[15:8]
178 B2 14 Read_vin[7:0]
179 B3 13 Read_pout0[15:8]
180 B4 12 Read_pout0[7:0]
181 B5 11 Read_iout0[15:8]
182 B6 10 Read_iout0[7:0]
183 B7 9 Status_iout0[7:0]
184 B8 8 Status_
temperature0[7:0]

185 B9 7 Read_

186 BA 6 Read_

187 BB 5 Status_mfr_
specific0[7:0]

188 BC 4 Status_vout0[7:0]
189 BD 3 Read_vout0[15:8]
190 BE 2 Read_vout0[7:0]
191 BF 1 Read_
temperature_2[15:8]

192 C0 0 Read_
temperature_2[7:0]

BYTE
NUMBER
DECIMAL
BYTE
NUMBER
HEX
LOOP
BYTE
NUMBER
DECIMAL MUX LOOP 3
54 BYTES PER
LOOP
193 C1 53 Read_pout3[15:8]
194 C2 52 Read_pout3[7:0]
195 C3 51 Read_iout3[15:8]
196 C4 50 Read_iout3[7:0]
197 C5 49 Status_iout3[7:0]
198 C6 48 Status_
temperature_3[7:0]

199 C7 47 Read_

200 C8 46 Read_

BYTE
NUMBER
DECIMAL
BYTE
NUMBER
HEX
LOOP
BYTE
NUMBER
DECIMAL MUX LOOP 3
54 BYTES PER
LOOP
201 C9 45 Status_mfr_
specific3[7:0]

202 CA 44 Status_vout3[7:0]
203 CB 43 Read_vout3[15:8]
204 CC 42 Read_vout3[7:0]
205 CD 41 Read_pout2[15:8]
206 CE 40 Read_pout2[7:0]
207 CF 39 Read_iout2[15:8]
208 D0 38 Read_iout2[7:0]
209 D1 37 Status_iout2[7:0]
210 D2 36 Status_
temperature2[7:0]

211 D3 35 Read_

212 D4 34 Read_

213 D5 33 Status_mfr_
specific2[7:0]

214 D6 32 Status_vout2[7:0]
215 D7 31 Read_vout2[15:8]
216 D8 30 Read_vout2[7:0]
217 D9 29 Read_pout1[15:8]
218 DA 28 Read_pout1[7:0]
219 DB 27 Read_iout1[15:8]
220 DC 26 Read_iout1[7:0]
221 DD 25 Status_iout1[7:0]
222 DE 24 Status_
temperature2[7:0]
223 DF 23 Read_
224 E0 22 Read_
225 E1 21 Status_mfr_
specific1[7:0]
226 E2 20 Status_vout1[7:0]
227 E3 19 Read_vout1[15:8]
228 E4 18 Read_vout1[7:0]
229 E5 17 0x0
230 E6 16 Status_input[7:0]
231 E7 15 Read_vin[15:8]
232 E8 14 Read_vin[7:0]
LTC2974
78
2974f
BYTE
NUMBER
DECIMAL
BYTE
NUMBER
HEX
LOOP
BYTE
NUMBER
DECIMAL MUX LOOP 3
54 BYTES PER
LOOP
233 E9 13 Read_pout0[15:8]
234 EA 12 Read_pout0[7:0]
235 EB 11 Read_iout0[15:8]
236 EC 10 Read_iout0[7:0]
237 ED 9 Status_iout0[7:0] Last valid fault
log byte
238 EE 0x00 Bytes EE - FE
return 0x00
239 EF 0x00
240 F0 0x00
241 F1 0x00
242 F2 0x00
243 F3 0x00
244 F4 0x00
245 F5 0x00
246 F6 0x00
247 F7 0x00
248 F8 0x00
249 F9 0x00
250 FA 0x00
251 FB 0x00
252 FC 0x00
253 FD 0x00
254 FE 0x00 This is PMBUS
byte 255. It must
be read to clear
Mfr_fault_log_
status_ram.
IDENTIFICATION/INFORMATION
COMMAND NAME
CMD
DEFAULT
VALUE
REF
PAGE
CAPABILITY 0x19 Summary of PMBus optional communication
protocols supported by this device.
R Byte N Reg 0xB0 79
PMBUS_REVISION 0x98 PMBus revision supported by this device.
Current revision is 1.1.
R Byte N Reg 0x11 79
MFR_SPECIAL_ID 0xE7 Manufacturer code for identifying the LTC2974. R Word N Reg Y 0x0212 79
MFR_SPECIAL_LOT 0xE8 Customer dependent codes that identify the
factory programmed user configuration stored
in EEPROM. Contact factory for default value.
R Byte Y Reg Y 79
LTC2974
79
2974f
CAPABILITY
The CAPABILITY command provides a way for a host system to determine some key capabilities of the LTC2974.
CAPABILITY Data Contents
b[7] Capability_pec Hard coded to 1 indicating Packet Error Checking is supported. Reading the Mfr_config_all_pec_en bit will indicate
whether PEC is currently required.
b[6:5] Capability_scl_max Hard coded to 01b indicating the maximum supported bus speed is 400kHz.
b[4] Capability_smb_alert Hard coded to 1 indicating this device does have an ALERTB pin and does support the SMBus Alert Response Protocol.
b[3:0] Reserved Always returns 0.
PMBus_REVISION
PMBus_REVISION Data Contents
b[7:0] PMBus_rev Reports the PMBus standard revision compliance. This is hard-coded to 0x11 for revision 1.1.
MFR_SPECIAL_ID
This register contains the manufacturer ID for the LTC2974. Always returns 0x0210.
MFR_SPECIAL_LOT
These paged registers contain information that identifies the user configuration that was programmed at the factory.
Contact the factory to request a custom factory programmed user configuration and special lot number.
USER_DATA_00, USER_DATA_01, USER_DATA_02, USER_DATA_03, USER_DATA_04, MFR_LTC_RESERVED_1
and MFR_LTC_RESERVED_2
These registers are provided as user scratchpad and additional manufacturer reserved locations.
USER SCRATCHPAD
COMMAND NAME
CMD
DEFAULT
VALUE
REF
PAGE
USER_DATA_00 0xB0 Manufacturer reserved for LTpowerPlay. R/W Word N Reg Y N/A 79
USER_DATA_01 0xB1 Manufacturer reserved for LTpowerPlay. R/W Word Y Reg Y N/A 79
USER_DATA_02 0xB2 OEM Reserved. R/W Word N Reg Y N/A 79
USER_DATA_03 0xB3 Scratchpad location. R/W Word Y Reg Y 0x00 79
USER_DATA_04 0xB4 Scratchpad location. R/W Word N Reg Y 0x00 79
MFR_LTC_RESERVED_1 0xB5 Manufacturer reserved. R/W Word Y Reg Y NA 79
MFR_LTC_RESERVED_2 0xBC Manufacturer reserved. R/W Word Y Reg NA 79
LTC2974
80
2974f
V
PWR
V
DD33
V
DD33
V
DD25
V
DD25
V
IN_SNS
LTC2974*
0.1F
0.1F
4.5V < V
PWR
< 15V
GND
0.1F
*SOME DETAILS
OMITTED FOR CLARITY
2978 F23
applicaTions inForMaTion
OVERVIEW
The LTC2974 is a power management IC that is capable
of sequencing, margining, trimming, supervising output
voltage for OV/UV conditions, supervising output current
for OC/UC conditions, fault management, and voltage/
current/temperature read back for four DC/DC converter
channels. Input voltage and LTC2974 junction temperature
read back are also available. Multiple LTC2974s can be
synchronized to operate in unison using the SHARE_CLK,
FAULTB, and CONTROL pins. The LTC2974 utilizes a PMBus
compliant interface and command set.
POWERING THE LTC2974
The LTC2974 can be powered two ways. The first method
requires that a voltage between 4.5V and 15V be applied
to the V
PWR
pin. See Figure 23. An internal linear regula-
tor converts V
PWR
down to 3.3V which drives all of the
internal circuitry of the LTC2974.
Alternatively, power from an external 3.3V supply may be
applied directly to the V
DD33
pins 11 and 12 using a voltage
between 3.13V and 3.47V. See Figure 24. Tie V
PWR
to the
V
DD33
pins. All functionality is available when using this
Figure 23. Powering LTC2974 Directly from an Intermediate Bus
alternate power method. The higher voltages needed for
the V
OUT_EN
pins and bias for the V
SENSE
pins are charge
pumped from V
DD33
.
SETTING COMMAND REGISTER VALUES
The command register settings described herein are for
the purpose of understanding and software development
in a host processor. In actual practice, the LTC2974 can
be completely configured for stand-alone operation with
the LTC USB to I
2
C/SMBus/PMBus controller and software
GUI using intuitive menu driven objects.
SEQUENCE, SERVO, MARGIN AND RESTART
OPERATIONS
Command Units On or Off
Three control parameters determine how a particular chan-
nel is turned on and off: The CONTROL pins, the OPERATION
command and the value of the input voltage measured at
the V
IN_SNS
pin (V
IN
). In all cases, V
IN
must exceed VIN_ON
in order to enable a start. When V
IN
drops below VIN_OFF
an immediate OFF or sequence off after TOFF_DELAY of
all channels will result (See Mfr_config_track_enn). Refer
to the OPERATION section in the data sheet for a detailed
description of the ON_OFF_CONFIG command.
Some examples of typical ON/OFF configurations are:
1. A DC/DC converter may be configured to turn on any
time V
IN
exceeds VIN_ON.
2. A DC/DC converter may be configured to turn on only
when it receives an OPERATION command.
via the CONTROL pin.
when it receives an OPERATION command and the
CONTROL pin is asserted.
On Sequencing
The TON_DELAY command sets the amount of time that
a channel will wait following the start of an ON sequence
before its V
OUT_EN
pin will enable a DC/DC converter. Once
the DC/DC converter has been enabled, the TON_RISE
V
DD33
V
DD33
V
DD25
V
DD25
V
PWR
LTC2974*
0.1F
0.1F
GND
*SOME DETAILS
OMITTED FOR CLARITY
2978 F24
EXTERNAL 3.3V
Figure 24. Powering LTC2974 from External 3.3V Supply
LTC2974
81
2974f
command determines the amount of time the LTC2974
waits before soft-connecting the V
DACn
output and ser-
voing the DC/DC converter output to VOUT_COMMAND.
The TON_MAX_FAULT_LIMIT command determines the
amount of time after the DC/DC converter has been enabled
that an under voltage condition will be tolerated before a
fault occurs. If a TON_MAX_FAULT occurs, the channel
can be configured to disable the DC/DC converter and
propagate the fault to other channels using the bidirectional
FAULTB pins. Figure 25 shows a typical on-sequence using
the CONTROL pin.
On State Operation
Once a channel has reached the ON state, the OPERA-
TION command can be used to command the DC/DC
converters output to margin high, margin low, or return to
a nominal output voltage indicated by VOUT_COMMAND.
The user also has the option of configuring a channel to
continuously trim the output of the DC/DC converter to the
VOUT_COMMAND voltage, or the channels V
DACn
output
can be placed in a high impedance state thus allowing the
DC/DC converter output voltage to go to its nominal value,
V
DCn(NOM)
. Refer to the MFR_CONFIG_LTC2974 command
for details on how to configure the output voltage servo.
Servo Modes
The ADC, DAC and internal processor comprise a digital
servo loop that can be configured to operate in several
Figure 25. Typical ON Sequence Using Control Pin
VOUT_OV_FAULT_LIMIT
VOUT_UV_FAULT_LIMIT
V
CONTROL
V
OUT_EN
V
OUT
TON_DELAY TON_RISE
2974 F25
V
DC(NOM)
V
OUT_COMMAND
TON_MAX_FAULT_LIMIT
useful modes. The servo target refers to the desired output
voltage.
Continuous/non-continuous trim mode: MFR_CON-
FIG_LTC2974 b[7]. In continuous trim mode, the servo
will update the DAC in a closed loop fashion each time it
takes a V
OUT
reading. The update rate is determined by
the time it takes to step through the ADC MUX which is
typically 170ms. See Electrical Characteristics table Note5.
In non-continuous trim mode, the servo will drive the DAC
until the ADC measures the output voltage desired and
then stop updating the DAC.
Non-continuous servo on warn mode: MFR_CONFIG_
LTC2974 b[7] = 0, b[6] = 1. When in non-continuous
mode, the LTC2974 will re-trim (re-servo) the output if
the output drifts beyond the OV or UV warn limits.
DAC Modes
The DACs that drive the V
DACn
pins can operate in several
useful modes. See MFR_CONFIG_LTC2974.
Soft connect. Using the LTC patented soft connect
feature, the DAC output is driven to within 1 LSB of
the voltage at the DC/DCs feedback node before con-
necting, to avoid introducing transients on the output.
This mode is used when servoing the output voltage.
During startup, the LTC2974 waits until TON_RISE has
expired before connecting the DAC. This is the most
common operating mode.
LTC2974
82
2974f
Disconnected. DAC output is high Z.
DAC manual with soft connect. Non servo mode. The
DAC soft connects to the feedback node. Soft connect
drives the DAC code to match the voltage at the feedback
node. After connection, the DAC is moved by writing
DAC codes to the MFR_DAC.
DAC manual with hard connect. Non servo mode. The
DAC hard connects to the feedback node using the
current value in MFR_DAC. After connection, the DAC
is moved by writing DAC codes to the MFR_DAC.
Margining
The LTC2974 margins and trims the output of a DC/DC
converter by forcing a voltage across an external resistor
connected between the DAC output and the feedback node
or the trim pin. Preset limits for margining are stored in
the VOUT_MARGIN_HIGH/LOW registers. Margining is
actuated by writing the appropriate bits to the OPERA-
TION register.
Margining requires the DAC to be connected. Margin
requests that occur when the DAC is disconnected will
be ignored.
Off Sequencing
An off sequence is initiated using the CONTROL pin or
the OPERATION command. The TOFF_DELAY command
determines the amount of time that elapses from the be-
ginning of the off sequence until each channels V
OUT_EN
pin is pulled low thus disabling its DC/DC converter.
V
OUT
Off Threshold Voltage
The MFR_VOUT_DISCHARGE_THRESHOLD command
register allows the user to specify the OFF threshold that
the output voltage must decay below before the channel
can enter/re-enter the ON state. The OFF threshold voltage
is specified by multiplying MFR_VOUT_DISCHARGE_
THRESHOLD and VOUT_COMMAND. In the event that an
output voltage has not decayed below its OFF threshold
before attempting to enter the ON state, the channel will
continue to be held off, the appropriate bit is set in the
STATUS_MFR_SPECIFIC register, and the ALERTB pin will
be asserted low. When the output voltage has decayed
below its OFF threshold, the channel can enter the ON state.
Automatic Restart via MFR_RESTART_DELAY
Command and CONTROL pin
An automatic restart sequence can be initiated by driving
the CONTROL pin to the off state for >10s and then re-
leasing it. The automatic restart disables all V
OUT_EN
pins
that are mapped to a particular CONTROL pin for a time
period = MFR_RESTART_DELAY and then starts all DC/
DC Converters according to their respective TON_DELAYs.
(see Figure 26). V
OUT_EN
pins are mapped to one of the
CONTROL pins by the MFR_CONFIG_LTC2974 command.
This feature allows a host that is about to reset to restart
the power in a controlled manner after it has recovered.
FAULT MANAGEMENT
Output Overvoltage, Undervoltage, Overcurrent, and
Undercurrent Faults
The high-speed voltage supervisor OV and UV fault thresh-
olds are configured using the VOUT_OV_FAULT_LIMIT and
VOUT_UV_FAULT_LIMIT commands, respectively. The
VOUT_OV_FAULT_RESPONSE and VOUT_UV_FAULT_RE-
SPONSE commands determine the responses to OV/UV
faults. In addition, the high-speed current supervisor
OC and UC fault thresholds are configured using the
IOUT_OC_FAULT_LIMIT and IOUT_UC_FAULT_LIMIT com-
mands, respectively. The IOUT_OC_FAULT_RESPONSE
and IOUT_UC_FAULT_RESPONSE commands determine
the responses to OC/UC faults. Fault responses can range
from disabling the DC/DC converter immediately, waiting
to see if the fault condition persists for some interval be-
fore disabling the DC/DC converter, or allowing the DC/DC
converter to continue operating in spite of the fault. If a
DC/DC converter is disabled, the LTC2974 can be config-
ured to retry one to six times, retry continuously without
limitation, or latch-off. The retry interval is specified using
Figure 26. Off Sequence with Automatic Restart
V
CONTROL
V
OUT_EN0
CONTROL
PIN BOUNCE
TOFF_DELAY0 TON_DELAY0
2974 F26
MFR_RESTART_DELAY
LTC2974
83
2974f
the MFR_RETRY_DELAY command. Latched faults are
reset by toggling the CONTROL pin, using the OPERATION
command, or removing and reapplying the bias voltage to
the V
IN_SNS
pin. All fault and warning conditions result in
the ALERTB pin being asserted low and the corresponding
bits being set in the status registers. The CLEAR_FAULTS
command resets the contents of the status registers and
de-asserts the ALERTB output.
Output Overvoltage, Undervoltage, and Overcurrent
Warnings
OV, UV, and OC warning thresholds are processed by
the LTC2974s ADC. These thresholds are set by the
VOUT_OV_WARN_LIMIT, VOUT_UV_WARN_LIMIT, and
IOUT_OC_WARN_LIMIT commands, respectively. Note
that there is no I
OUT
UC warning threshold. If a warning
occurs, the corresponding bits are set in the status reg-
isters and the ALERTB output is asserted low. Note that a
warning will never cause a V
OUT_EN
output pin to disable
a DC/DC converter.
Configuring the AUXFAULTB Output
The AUXFAULTB output may be used to indicate an output
OV, OC, or UC fault. Use the MFR_CONFIG2_LTC2974
and MFR_CONFIG3_LTC2974 registers to configure the
AUXFAULTB pin to assert low in response to VOUT_OV,
IOUT_OC or IOUT_UC fault conditions. The AUXFAULTB
output will stop pulling low when the LTC2974 is com-
manded to re-enter the ON state following a faulted-off
condition.
A charge-pumped 5A pull-up to 12V is also available on
the AUXFAULTB output. Refer to the MFR_CONFIG_ALL_
LTC2974 register description in the PMBUS COMMAND
DESCRIPTION section for more information.
Figure 27 shows an application circuit where the AUX-
FAULTB output is used to trigger a SCR crowbar on the
intermediate bus in order to protect the DC/DC converters
load from a catastrophic fault such as a stuck top-gate.
Multi-Channel Fault Management
Multi-channel fault management is handled using the
bidirectional FAULTB pins. Figure 28 illustrates the con-
nections between channels and the FAULTB pins.
The MFR_FAULTBn_PROPAGATE command acts like
a programmable switch that allows faulted_off condi-
tions from a particular channel (PAGE) to propagate to
either FAULTB output. The MFR_FAULTBn_RESPONSE
Figure 27. Application Circuit with Crowbar Protection on Intermediate Bus
0.1F
V
PWR
AUXFAULTB
V
IN_SNS
V
DAC0
V
SENSEP0
V
SENSEM0
V
OUT_EN0
REFP
REFM
GND
LTC2974*
4.5V < V
IBUS
< 15V
V
DD33
V
DD33
V
IN
C
BYPASS
0.1F
0.01F
0.22F
0.01F
220
MCR12DC
0.1F
V
DD25
V
DD25
V
OUT
2974 F27
RUN/SS
SGND
V
FB
GND
DC/DC
CONVERTER
LOAD
4.99k
10k
100
68
V
CC
SENSE
R
SENSE
0.007
Q1
Si4894BDY
LTC4210-1
TIMER GND
GATE
24.3k
10k
ON
0.01F
MMBT2907
LTC2974
84
2974f
command controls similar switches on the inputs to
each channel that allow any channel to shut down
in response to any combination of the FAULTB pins.
Channels responding to a FAULTB pin pulling low will
attempt a new start sequence when the FAULTB pin in
question is released by the faulted channel.
A FAULTB pin can also be asserted low by an external
driver in order to initiate an immediate off-sequence
after a 10s deglitch delay.
INTERCONNECT BETWEEN MULTIPLE LTC2974S
Figure 29 shows how to interconnect the pins in a typical
multi-LTC2974 array.
All V
IN_SNS
lines should be tied together in a star
type connection at the point where V
IN
is to be sensed.
This will minimize timing errors for the case where the
ON_OFF_CONFIG is configured to start the LTC2974 based
on V
IN
and ignore the CONTROL line and the OPERATION
command. In multi-part applications that are sensitive to
timing differences, it is recommended that the Vin_share_
enable bit of the MFR_CONFIG_ALL_LTC2974 register be
set high in order to allow SHARE_CLK to synchronize on/
Figure 28. Channel Fault Management Block Diagram
off sequencing in response to the VIN_ON and VIN_OFF
thresholds.
Connecting all AUXFAULTB lines together will allow
selected faults on any DC/DC converters output in the
array to shut off a common input switch.
ALERTB is typically one line in an array of PMBus con-
verters. The LTC2974 allows a rich combination of faults
and warnings to be propagated to the ALERTB pin.
WDI/RESETB can be used to put the LTC2974 in the
power-on reset state. Pull WDI/RESETB low for at least
t
RESETB
to enter this state.
The FAULTB lines can be connected together to create
fault dependencies. Figure 29 shows a configuration
where a fault on any FAULTB will pull all others low.
This is useful for arrays where it is desired to abort
a startup sequence in the event any channel does not
come up (see Figure 30).
PWRGD reflects the status of the outputs that are
mapped to it by the MFR_PWRGD_EN command. Fig-
ure 29 shows all the PWRGD pins connected together,
but any combination may be used.
CHANNEL 0
EVENT PROCESSOR
PAGE = 0
Mfr_faultb0_response, page = 0
Mfr_faultb0_propagate_chan0
FAULTB0
FAULTED_OFF
FAULTED_OFF
FAULTED_OFF
FAULTED_OFF
CHANNEL 1
EVENT PROCESSOR
PAGE = 1
CHANNEL 2
EVENT PROCESSOR
PAGE = 2
CHANNEL 3
EVENT PROCESSOR
PAGE = 3
FAULTB1
2974 F28
LTC2974
85
2974f
Figure 29. Typical Connections between Multiple LTC2974s
Figure 30. Aborted On-Sequence Due to Channel 1 Short
VIN_SNS
AUXFAULTB
SDA
SCL
ALERTB
CONTROL0
WDI/RESETB
FAULTB0
SHARE_CLK
PWRGD
GND
LTC2974 #1
VIN_SNS
AUXFAULTB
SDA
SCL
ALERTB
CONTROL0
WDI/RESETB
FAULTB0
SHARE_CLK
PWRGD
GND
2974 F29
LTC2974 #n
TO V
IN
OF
DC/DCs
TO INPUT
SWITCH
TO HOST CONTROLLER
TO OTHER LTC2974s10k EQUIVALENT PULL-UP RECOMMENDED
ON EACH LINE EXCEPT SHARE_CLK (USE 5.49k)
V
CONTROL
V
OUT0
TON_DELAY0
V
OUT1
V
OUT2
V
OUTn
BUSSED
V
FAULTBn
PINS
TON_MAX_FAULT1
2974 F30
TON_DELAY1
TON_DELAY2
TON_DELAYn
APPLICATION CIRCUITS
Trimming and Margining DC/DC Converters with
External Feedback Resistors
Figure 31 shows a typical application circuit for trimming/
margining a power supply with an external feedback
network. The V
SENSEP0
and V
SENSEM0
differential inputs
sense the load voltage directly, and a correction voltage
is developed on the V
DAC0
pin by the closed-loop servo
algorithm. The V
DAC0
output is connected to the DC/DC
converters feedback node through resistor R30. For this
configuration, set Mfr_config_dac_pol to 0.
Four-Step Resistor Selection Procedure for DC/DC
Converters with External Feedback Resistors
The following four-step procedure should be used to
calculate the resistor values required for the application
circuit shown in Figure 31.
1. Assume values for feedback resistor R20 and the nominal
DC/DC converter output voltage V
DC(NOM)
, and solve
for R10.
V
DC(NOM)
is the output voltage of the DC/DC converter
when the LTC2974s V
DAC0
pin is in a high impedance
LTC2974
86
2974f
Figure 31. Application Circuit for DC/DC Converters with External Feedback Resistors
V
PWR
V
DD33
V
DD33
V
DD25
V
IN_SNS
V
DAC0
V
SENSEP0
V
SENSEM0
V
OUT_EN0
LTC2974*
0.1F
0.1F
4.5V < V
IBUS
< 15V
GND
V
IN
V
OUT
R20
R30
R10
2974 F31
RUN/SS
SGND
V
FB
GND
DC/DC
CONVERTER
LOAD
state. R10 is a function of R20, V
DC(NOM)
, the voltage at
the feedback node (V
FB
) when the loop is in regulation,
and the feedback nodes input current (I
FB
).

R10
R20 V
FB
V
DC(NOM)
I
FB
R20 V
FB
(1)
2. Solve for the value of R30 that yields the maximum
required DC/DC converter output voltage V
DC(MAX)
.
When V
DAC0
is at 0V, the output of the DC/DC converter
is at its maximum voltage.

R30
R20 V
FB
V
DC(MAX)
V
DC(NOM)
(2)
3. Solve for the minimum value of V
DAC0
thats needed to
yield the minimum required DC/DC converter output
voltage V
DC(MIN)
.
The DAC has two full-scale settings, 1.38V and 2.65V. In
order to select the appropriate full-scale setting, calculate
the minimum required V
DAC0(F/S)
output voltage:

V
DAC0(F/S)
> V
DC(NOM)
V
DC(MIN) ( )
R30
R20
+ V
FB
(3)
4. Re-calculate the minimum, nominal, and maximum
DC/DC converter output voltages and the resulting
margining resolution.

V
DC(NOM)
V
FB
1+
R20
R10
j
(
,
\
,
(
+I
FB
R20 (4)
V
DC(MIN)
V
DC(NOM)
R20
R30
V
DAC0(F /S)
V
FB ( )
(5)
V
DC(MAX)
V
DC(NOM)
+
R20
R30
V
FB
(6)
V
RES

R20
R30
V
DAC0(F /S)
1024
V/DAC LSB (7)
Trimming and Margining DC/DC Converters with a
TRIM Pin
Figure 32 illustrates a typical application circuit for trim-
ming/margining the output voltage of a DC/DC converter
with a TRIM Pin. The LTC2974s V
DAC0
pin connects to
the TRIM pin through resistor R30. For this configuration,
set the DAC polarity bit Mfr_config_dac_pol in MFR_CON-
FIG_LTC2974 to 1.
LTC2974
87
2974f
DC/DC converters with a TRIM pin may be margined
high or low by connecting an external resistor between
the TRIM pin and either the V
SENSEP
or V
SENSEM
pin. The
relationships between these resistors and the % change
in the output voltage of the DC/DC converter are typically
expressed as:

R
TRIM_DOWN

R
TRIM
50
DOWN
%
R
TRIM
(8)
R
TRIM_UP

R
TRIM
V
DC
100 +
UP
% ( )
2 V
REF

UP
%
50
UP
%
j
(
,
\
,
(
1
,
,
]
]
]
(9)
where R
TRIM
is the resistance looking into the TRIM pin,
V
REF
is the TRIM pins open-circuit output voltage and
V
DC
is the DC/DC converters nominal output voltage.
UP
% and
DOWN
% denote the percentage change in the
converters output voltage when margining up or down,
respectively.
Two-Step Resistor and DAC Full-Scale Voltage Selection
Procedure for DC/DC Converters with a TRIM Pin
The following two-step procedure should be used to cal-
culate the resistor value for R30 and the required full-scale
DAC voltage (refer to Figure 32).
1. Solve for R30:

R30 R
TRIM
50
DOWN
%
DOWN
%
j
(
,
\
,
(
(10)
2. Calculate the maximum required output voltage for
V
DAC0
:

V
DAC0
1+

UP
%
DOWN
%
j
(
,
\
,
(
V
REF
(11)
Note: Not all DC/DC converters follow these trim equations,
especially newer bricks. Consult LTC Field Application
Engineering.
Measuring Current with a Sense Resistor
A circuit for measuring current with a sense resistor is
shown in Figure 33. The balanced filter rejects both com-
mon mode and differential mode noise from the output of
the DC/DC converter. The filter is placed directly across the
sense resistor in series with the DC/DC converters induc-
tor. Note that the current sense inputs must be limited to
less than 6V with respect to ground. Select R
CM
and C
CM

such that the filters corner frequency is < 1/10 the DC/
DC converters switching frequency. This will result in a
current sense waveform that offers a good compromise
between the voltage ripple and the delay through the filter.
A value 1k for R
CM
is suggested in order to minimize gain
errors due to the current sense inputs internal resistance.
Measuring Current with Inductor DCR
Figure 34 shows the circuit for applications that require
DCR current sense. A second order R-C filter is required
in these applications in order to minimize the ripple volt-
age seen at the current sense inputs. A value of 1k
Figure 32. Application Circuit for DC/DC Converters with Trim Pin
V
PWR
V
DD33
V
DD33
V
DD25
V
IN_SNS
V
DAC0
V
SENSEP0
V
SENSEM0
V
OUT_EN0
LTC2974*
0.1F
0.1F
4.5V < V
IBUS
< 15V
GND
V
IN
V
O
+
R30
2974 F32
ON/OFFB
V
SENSE
V
SENSE
+
TRIM
V
O
DC/DC
CONVERTER
LOAD
LTC2974
88
2974f
is suggested for R
CM1
and R
CM2
in order to minimize
gain errors due the current sense inputs internal resis-
tance. C
CM1
should be selected to provide cancellation
of the zero created by the DCR and inductance, i.e.
C
CM1
= L/(DCR R
CM1
). C
CM2
should be selected to provide
a second stage corner frequency at < 1/10 of the DC/DC
converters switching frequency. In addition, C
CM2
needs to
be much smaller than C
CM1
in order to prevent significant
loading of the filters first stage.
Single Phase Design Example
As a design example for a DCR current sense application,
assume L = 2.2H, DCR = 10m, and F
SW
= 500kHz.
Let R
CM1
= 1k and solve for C
CM1
:

C
CM1
2.2H
10m 1k
220nF
Let R
CM2
= 1k. In order to get a second pole at
F
SW
/10 = 50kHz:

C
CM2

1
2 50kHz 1k
3.18nF
Let C
CM2
= 3.3nF. Note that since C
CM2
is much less than
C
CM1
the loading effects of the second stage filter on the
matched first stage are not significant. Consequently, the
delay time constant through the filter for the current sense
waveform will be approximately 3s.
Measuring Multiphase Currents
For current sense applications with more than one phase,
R-C averaging may be employed. Figure 35 shows an
example of this approach for a 3-phase system with DCR
current sensing. The current sense waveforms are aver-
aged together prior to being applied to the second stage of
the filter consisting of R
CM2
and C
CM2
. Because the R
CM1

resistors for the three phases are in parallel, the value of
R
CM1
must be multiplied by the number of phases. Also
note that since the DCRs are effectively in parallel, the
value for IOUT_CAL_GAIN will be equal to the inductors
DCR divided by the number of phases. Care should be
taken in the layout of the multiphase inductors to keep the
PCB trace resistance from the DC side of each inductor to
Figure 33.Sense Resistor Current Sensing Circuits
Figure 34. DCR Current Sensing Circuits
R
CM
R
CM
R
SNS
2974 F33
L
LOAD CURRENT
C
CM
C
CM
LTC2974
I
SENSEP
I
SENSEM
2974 F34
R
CM2
R
CM2
R
CM1
R
CM1
DCR L
C
CM2
C
CM2
LTC2974
I
SENSEP
I
SENSEM
C
CM1
C
CM1
SWX0
LTC2974
I
SENSEP
I
SENSEM
2974 F35
C
CM2
C
CM2
R
CM2
C
CM2
C
CM1
R
CM2
R
CM1
R
CM1
R
CM1
R
CM1/3
DCR
DCR
L
L
DCR
L
SWX2 SWX3
TO LOAD
SWX1
Figure 35. Multiphase DCR Current Sensing Circuits
LTC2974
89
2974f
the summing node balanced in order to provide the most
accurate results.
Multiphase Design Example
Using the same values for inductance and DCR from
the previous design example, the value for R
CM1
will be
3k for a three phase DC/DC converter if C
CM1
is left at
220nF. Similarly, the value for IOUT_CAL_GAIN will be
DCR/3=3.33m.
Anti-aliasing Filter Considerations
Noisy environments require an anti-aliasing filter on
the input to the LTC2974s ADC. The R-C circuit shown
in Figure 36 is adequate for most situations. Keep
R40 = R50 200 to minimize ADC gain errors, and select
a value for capacitors C10 and C20 that doesnt add too
much additional response time to the OV/UV supervisor,
e.g. = 10s (R = 100, C = 0.10F).
Sensing Negative Voltages
Figure 37 shows the LTC2974 sensing a negative power
supply (V
EE
). The R1/R2 resistor divider translates the
negative supply voltage to the LTC2974s V
SENSEM1
input
while the V
SENSEP1
input is tied to the REFP pin which has
a typical output voltage of 1.23V. Read_vout is determined
from the following equation:

V
EE
V
REFP
READ_ VOUT ( )
R2
R1
+ 1
j
(
,
\
,
(
1A R2

(14)
Where READ_VOUT returns V
SENSEP
V
SENSEM
Figure 36. Anti-Aliasing Filter on V
SENSE
Lines
Figure 37. Sensing Negative Voltages
V
PWR
V
DD33
V
DD33
V
DD25
V
IN_SNS
V
DAC0
V
SENSEP0
V
SENSEM0
V
OUT_EN0
LTC2974*
0.1F
0.1F
4.5V < V
IBUS
< 15V
V
IN
V
OUT
R20
R30
R10
2974 F36
RUN/SS
SGND
V
FB
GND
DC/DC
CONVERTER
LOAD
C10
C20
R50
R40
GND
LTC2974
4.5V < V
IBUS
< 15V
GND
ONLY ONE OF FOUR CHANNELS SHOWN,
SOME DETAILS OMITTED FOR CLARITY
POWER_GOOD_ON = 0.5V FOR V
EE
POWER_GOOD = 11.414V
WHERE V
EE
POWER_GOOD =
V
REFP
POWER_GOOD_ON (R2/R1 + 1) 1A R2
0.1F
1.23V TYP
2974 F37
V
PWR
SDA
SCL
ALERTB
CONTROL
FAULTB
WDI/RESETB
SHARE_CLK
ASEL0
ASEL1
WP
V
IN_SNS
REFM
V
SENSEP1
WDI/RESETB
V
SENSEM1
REFP
PWRGD
0.1F R1 = 4.99k 1A AT 0.5V
R2 = 120k
V
EE
= 12V
PMBus
INTERFACE
LTC2974
90
2974f
The voltage divider should be configured in order to present
about 0.5V to the voltage sense inputs when the negative
supply reaches its POWER_GOOD_ON threshold so that
the current flowing out of the V
SENSEMn
pin is minimized
to ~1A. The relationship between the POWER_GOOD_ON
register value and the corresponding negative supply value
can be determined using equation 14:
Connecting the USB to I
2
C/SMBus/PMBus Controller
to the LTC2974 in System
The LTC USB to I
2
C/SMBus/PMBus Controller can be
interfaced to the LTC2974s on the users board for pro-
gramming, telemetry and system debug. The controller,
when used in conjunction with LTpowerPlay software,
provides a powerful way to debug an entire power system.
Failures are quickly diagnosed using telemetry, fault status
registers and the fault log. The final configuration can be
quickly developed and stored to the LTC2974s EEPROM.
Figure 38 and Figure 39 illustrate application schematics
for powering, programming and communicating with
one or more LTC2974s via the LTC I
2
C/SMBus/PMBus
controller regardless of whether or not system power
is present.
Figure 38 shows the recommended schematic to use when
the LTC2974 is powered by the system intermediate bus
through its V
PWR
pin.
Figure 39 shows the recommended schematic to use when
the LTC2974 is powered by the system 3.3V through its
V
DD33
and V
PWR
pins. The LTC4412 ideal ORing circuit
allows either the controller or system to power the LTC2974.
Because of the controllers limited current sourcing capabil-
ity, only the LTC2974s, their associated pull up resistors
and the I
2
C/SMBus pull-up resistors should be powered
from the ORed 3.3V supply. In addition, any device sharing
I
2
C/SMBus bus connections with the LTC2974 should not
have body diodes between the SDA/SCL pins and its V
DD

node because this will interfere with bus communication
in the absence of system power.
The LTC controllers I
2
C/SMBus connections are opto-
isolated from the PCs USB. The 3.3V from the controller and
the LTC2974s V
DD33
pin can be paralleled because the LTC
LDOs that generate these voltages can be backdriven and
draw <10A. The controllers 3.3V current limit is 100mA.
Figure 38. LTC Controller Connections When V
PWR
Is Used
2974 F38
V
PWR
V
DD33
LTC2974*
WP GND
*PIN CONNECTIONS
OMITTED FOR CLARITY
REPEAT OUTLINED CIRCUIT FOR EVERY LTC2974
TO/FROM OTHER
LTC2974s
0.1F
5.49k 10k 10k
V
DD33
0.1F
V
DD25
0.1F
49.9k 150k
SCL
SDA
SHARE_CLK
TO LTC USB TO
I
2
C/SMBUS/PMBUS
CONTROLLER
ISOLATED 3.3V
Si1303
4.5V TO 15V
SCL
GND
SDA
LTC2974
91
2974f
2974 F40
LTC3601
INDUCTOR
TEMPERATURE
SENSOR
TO LTC USB TO
I
2
C/SMBUS/PMBUS
CONTROLLER
ISOLATED 3.3V
SCL
GND
SDA
2974 F39
LTC4412
NOTE: LTC CONTROLLER I
2
C CONNECTIONS ARE OPTO-ISOLATED
ISOLATED 3.3V FROM LTC CONTROLLER CAN BE BACK DRIVEN AND WILL ONLY DRAW <10A
ISOLATED 3.3V CURRENT LIMIT IS 100mA
SENSE V
IN
GATE GND
STAT CTL
V
PWR
V
DD33
LTC2974*
WP GND
*PIN CONNECTIONS
OMITTED FOR CLARITY
TO/FROM OTHER
LTC2974s
IDEAL DIODE
ORD 3.3V TP0101K-SOT23
SYSTEM 3.3V
0.1F
V
DD33
V
DD25
0.1F
SCL
SDA
SHARE_CLK
Figure 39. LTC Controller Connections When LTC2974 Is Powered Directly from 3.3V
ACCURATE DCR TEMPERATURE COMPENSATION
Using the DC resistance of the inductor as a current shunt
element has several advantages no additional power
loss, lower circuit complexity and cost. However, the
strong temperature dependence of the inductor resistance
and the difficulty in measuring the exact inductor core
temperature introduce errors in the current measurement.
For copper, a change of inductor temperature of only 1C
corresponds to approximately 0.39% current gain change.
Figure 40 shows a sample layout using the integrated
DC/DC converter LTC3601 (right) and its corresponding
thermal image (left). The converter is providing 1.8V, 1.5A
to the output load.
Figure 40. Thermal Image of a DC/DC Converter Showing the Difference Between
the Actual Inductor Temperature and the Temperature Sensing Point
LTC2974
92
2974f
Heat dissipation in the inductor under high load condi-
tions creates transient and steady state thermal gradients
between the inductor and the temperature sensor, and the
sensed temperature does not accurately represent the
inductor core temperature. This temperature gradient is
clearly visible in the thermal image of Figure 40. In addition,
transient heating/cooling effects have to be accounted for
in order to reduce the transient errors introduced when
load current changes are faster than heat transfer time
constants of the inductor. Both of these problems are
addressed by introducing two additional parameters: the
thermal resistance
IS
from the inductor core to the on-
board temperature sensor, and the inductor thermal time
constant . The thermal resistance
IS
[C/W], is used to
calculate the steady state difference between the sensed
temperature T
S
and the internal inductor temperature T
I

for a given power dissipated in the inductor P
I
:
T
I
T
S
=
IS
P
I
=
IS
V
DCR
I
OUT
(1.1)
The additional temperature rise is used for a more accurate
estimate of the inductor DC resistance R
I
:
R
I
= R0 (1 + a [T
S
T
REF
+
IS
V
DCR
I
OUT
]) (1.2)
In the equations above, V
DCR
is the inductor DC voltage
drop, I
OUT
is the RMS value of the output current, R0 is
the inductor DC resistance at the reference temperature
T
REF
and a is the temperature coefficient of the resistance.
Since most inductors are made of copper, we can expect
a temperature coefficient close to a
CU
= 3900ppm/C.
For a given a, the remaining parameters
IS
and R0 can
be calibrated at a single temperature using only two load
currents:

R0
R2R1 ( ) P2+P1 ( ) R2+R1 ( ) P2P1 ( )
T2 T1 ( ) P2+P1 ( ) P2P1 ( ) 2+ T1+ T2 2T
REF
,
]
]
( )

(1.3)

IS

1
R0
R1+R2 ( ) T2 T1 ( ) R2R1 ( ) 2+ T1+ T2 2T
REF
,
]
]
( )
T2 T1 ( ) P2+P1 ( ) P2P1 ( ) 2+ T1+ T2 2T
REF
,
]
]
( )

(1.4)
The inductor resistance, R
K
= V
DCR(K)
/I
OUT(K)
, power dis-
sipation P
K
= V
DCR(K)
I
OUT(K)
and the sensed temperature
T
K
, (K = 1, 2) are recorded for each load current. To increase
the accuracy in calculating
IS
, the two load currents should
be chosen around I1 = 10% and I2 = 90% of the current
range of the system.
The inductor thermal time constant models the first order
thermal response of the inductor and allows accurate DCR
compensation during load transients. During a transition
from low to high load current, the inductor resistance
increases due to the self-heating. If we apply a single load
step from the low current I1 to the higher current I2, the
voltage across the inductor will change instantaneously
from I1R1 to I2R1 and then slowly approach I2R2. Here
R1 is the steady state resistance at the given temperature
and load current I1, and R2 is the slightly higher DC resis-
tance at I2, due to the inductor self-heating. Note that the
electrical time constant
EL
= L/R is several orders of mag-
nitude shorter than the thermal one, and instantaneous
is relative to the thermal time constant. The two settled
regions give us the data sets (I1, T1, R1, P1) and (I2, T2,
R2, P2) and the two-point calibration technique (1.3-1.4)
is used to extract the steady-state parameters
IS
and R0
(given a previously characterized average a). The relative
current error calculated using the steady-state expression
(1.2) will peak immediately after the load step, and then
decay to zero with the inductor thermal time constant .

I
I
(t)
IS
V2I2 V1I1 ( )e
t /

(1.5)
The time constant is calculated from the slope of the
best-fit line y = ln(I/I) = a1 + a2t:

1
a2

(1.6)
In summary, a single load current step is all that is needed
to calibrate the DCR current measurement. The stable por-
tions of the response give us the thermal resistance
IS
and
nominal DC resistance R0, and the settling characteristic
is used to measure the inductor thermal time constant .
To get the best performance, the temperature sensor has
to be as close as possible to the inductor and away from
other significant heat sources. For example in Figure 40,
the bipolar sense transistor is close to the inductor and
away from the switcher. Connecting the collector of the
PNP to the local power ground plane assures good thermal
contact to the inductor, while the base and emitter should
be routed to the LTC2974 separately, and the base con-
nected to the signal ground close to LTC2974.
LTC2974
93
2974f
LTpowerPlay: AN INTERACTIVE GUI FOR DIGITAL
POWER
LTpowerPlay is a powerful Windows based development
environment that supports Linear Technology digital power
ICs with EEPROM, including the LTC2974 Quad Digital
Power Supply Manager. The software supports a variety
of different tasks. You can use LTpowerPlay to evaluate
Linear Technology ICs by connecting to a demo board
system. LTpowerPlay can also be used in an offline mode
(with no hardware present) in order to build a multi-chip
configuration file that can be saved and re-loaded at a later
time. LTpowerPlay provides unprecedented diagnostic and
debug features. It becomes a valuable diagnostic tool during
board bring-up to program the power management scheme
in a system. LTpowerPlay utilizes Linear Technologys USB-
to-I
2
C/SMBus/PMBus Controller to communicate with one
of many potential targets, including the DC1809/DC1810
demo board set, the DC1735 socketed programming board,
or a customer target system. The software also provides
an automatic update feature to keep the software current
with the latest set of device drivers and documentation.
A great deal of context sensitive help is available within
LTpowerPlay along with several tutorial demos. Complete
information is available at:
www.linear.com/ltpowerplay
LTC2974
94
2974f
PCB ASSEMBLY AND LAYOUT SUGGESTIONS
Bypass Capacitor Placement
The LTC2974 requires 0.1F bypass capacitors between
the V
DD33
pins and GND, the V
DD25
pin and GND, and the
REFP pin and REFM pin. If the chip is being powered from
the V
PWR
input, then that pin should also be bypassed to
GND by a 0.1F capacitor. In order to be effective, these
capacitors should be made of a high quality ceramic
dielectric such as X5R or X7R and be placed as close to
the chip as possible.
Expose Pad Stencil Design
The LTC2974s package is thermally and electrically ef-
ficient. This is enabled by the exposed die attach pad on
the under side of the package which must be soldered
down to the PCB or mother board substrate. It is a good
practice to minimize the presence of voids within the
exposed pad inter-connection. Total elimination of voids
is difficult, but the design of the exposed pad stencil is
key. Figure 41 shows a suggested screen print pattern.
The proposed stencil design enables out-gassing of the
solder paste during reflow as well as regulating the finished
solder thickness. See IPC7525A
Figure 41. Suggested Screen Pattern for Die Attach Pad
2974 F41
QFN PACKAGE
APERATURE DESIGN 50% TO 80% REDUCTION GROUND PLANE
PCB Board Layout
Mechanical stress on a PC board and soldering-induced
stress can cause the LTC2974s reference voltage and the
voltage drift to shift. A simple way to reduce the stress-
related shifts is to mount the IC near the short edge of
the PC board, or in a corner. The board acts as a stress
boundary, or a region where the flexure of the board is
minimal.
LTC2974
95
2974f
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
package DescripTion
9 .00 0.10
(4 SIDES)
NOTE:
1. DRAWING CONFORMS TO JEDEC PACKAGE OUTLINE MO-220 VARIATION WNJR-5
2. ALL DIMENSIONS ARE IN MILLIMETERS
3. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE, IF PRESENT
4. EXPOSED PAD SHALL BE SOLDER PLATED
5. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE
6. DRAWING NOT TO SCALE
PIN 1 TOP MARK
(SEE NOTE 5)
0.40 0.10
64 63
1
2
BOTTOM VIEWEXPOSED PAD
7.15 0.10
7.15 0.10
7.50 REF
(4-SIDES)
0.75 0.05
R = 0.10
TYP
R = 0.115
TYP
0.25 0.05
0.50 BSC
0.200 REF
0.00 0.05
(UP64) QFN 0406 REV C
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED
0.70 0.05
7.50 REF
(4 SIDES)
7.15 0.05
7.15 0.05
8.10 0.05 9.50 0.05
0.25 0.05
0.50 BSC
PACKAGE OUTLINE
PIN 1
CHAMFER
C = 0.35
UP Package
64-Lead Plastic QFN (9mm 9mm)
(Reference LTC DWG # 05-08-1705 Rev C)
LTC2974
96
2974f
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900
FAX: (408) 434-0507

www.linear.com LINEAR TECHNOLOGY CORPORATION 2012
LT 0112 PRINTED IN USA
relaTeD parTs
Typical applicaTion
PART NUMBER DESCRIPTION COMMENTS
LTC2970 Dual I
2
C Power Supply Monitor and Margining Controller 14-Bit ADC with 0.5% TUE and Reference, 4.5V to 15V Operation
LTC2978 Octal Digital Power Supply Manager with EEPROM I
2
C/PMBus Interface, Configuration EEPROM, Black Box Fault Logging,
16-Bit ADC with 0.25% TUE, 3.3V to 15V Operation
LTC3880 Dual Output PolyPhase
Step-Down DC/DC Controller with

Digital Power System Management
I
2
C/PMBus Interface, Configuration EEPROM, 0.5% Output Voltage
Accuracy, MOSFET Gate Drivers
VIN
SWX
TG
62
5
57
19
61
RUN/SS SGND
VFB
PGND
DC/DC
CONVERTER
MMBT3906
330nF
LOAD
VDAC2
VSENSEP2
27
TSENSE2
VSENSEM2
VOUT_EN2
46
ISENSEM2
45
ISENSEP2
REFP
REFM
LTC2974
GND
20
GND
21
GND
37
GND
39
GND
2974 TA02
INTERMEDIATE
BUS
7
AUXFAULTB
TO/FROM OTHER LTC2974s, LTC2978s AND MICROCONTROLLER
25
F
A
U
L
T
B
0
0.1F
65 28 13 9
18
S
H
A
R
E
_
C
L
K
29
S
D
A
30
S
C
L
31
A
L
E
R
T
B
17
P
W
R
G
D
23 22
C
O
N
T
R
O
L
3
33
C
O
N
T
R
O
L
2
C
O
N
T
R
O
L
1
32
C
O
N
T
R
O
L
0
24
W
D
I
/
R
E
S
E
T
B
G
N
D
W
P
V
D
D
2
5
14
V
D
D
2
5
51 11 12 10 36 35
3.3V
N
C
52
N
C
55
N
C
56
N
C
59
N
C
60
N
C
8
D
N
C
V
D
D
3
3
V
D
D
3
3
V
P
W
R
A
S
E
L
1
A
S
E
L
0
V
I
N
_
S
N
S
26
F
A
U
L
T
B
1
0.1F
0.1F
BG
VIN
SWX
TG
50
6
58
49
RUN/SS SGND
VFB
PGND
DC/DC
CONVERTER
MMBT3906
330nF
LOAD
VDAC3
VSENSEP3
34
TSENSE3
VSENSEM3
VOUT_EN3
48
ISENSEM3
47
ISENSEP3
BG
2
3
53
1
VDAC0
VSENSEP0
15
TSENSE0
VSENSEM0
VOUT_EN0
42
38
40
ISENSEM0
41
ISENSEP0
64
4
54
63
VDAC1
VSENSEP1
16
TSENSE1
VSENSEM1
VOUT_EN1
44
ISENSEM1
43
ISENSEP1
10k
5.49k
3.3V 3.3V
10k
10k
10k
10k
10k
10k
10k
10k
10k
10k
VIN
SWX
TG
RUN/SS SGND
VFB
PGND
DC/DC
CONVERTER
BG
VIN
SWX
TG
RUN/SS SGND
VFB
PGND
DC/DC
CONVERTER
BG
MMBT3906
330nF
LOAD
MMBT3906
330nF
LOAD
3.3V
0V

2974 F

Uploaded by

Copyright:

Available Formats

2974 F

Uploaded by

Document Information

Original Description:

Original Title

Copyright

Available Formats

Share this document

Share or Embed Document

Sharing Options

Did you find this document useful?

Is this content inappropriate?

Copyright:

Available Formats

2974 F

Uploaded by

Copyright:

Available Formats

LTC2974

2974 is a quad, digital power-supply monitor,

= CAPACITANCE REPRESENTING THERMAL HEAT CAPACITY OF THE INDUCTOR

is not required. The important quantity is the thermal time constant

FAX: (408) 434-0507

Step-Down DC/DC Controller with

You might also like