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Introduction to VerilogHDL Module 1 Part3 Procedural Assignments

The document provides an introduction to Verilog HDL, focusing on procedural assignments used in VLSI design. It explains continuous and procedural assignments, detailing the use of 'initial' and 'always' blocks for modeling combinational and sequential logic. Additionally, it discusses the importance of sensitivity lists and the differences between blocking and non-blocking assignments in Verilog.

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Mohammad Sania 22221882101
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© © All Rights Reserved
Available Formats
Download as PDF, TXT or read online on Scribd
3 views

Introduction to VerilogHDL Module 1 Part3 Procedural Assignments

The document provides an introduction to Verilog HDL, focusing on procedural assignments used in VLSI design. It explains continuous and procedural assignments, detailing the use of 'initial' and 'always' blocks for modeling combinational and sequential logic. Additionally, it discusses the importance of sensitivity lists and the differences between blocking and non-blocking assignments in Verilog.

Uploaded by

Mohammad Sania 22221882101
Copyright
© © All Rights Reserved
Available Formats
Download as PDF, TXT or read online on Scribd
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Introduction to Verilog HDL

VLSI Design (Module I)

Y V Appa Rao

Department of Electrical, Electronics and Communication Engineering


GITAM Institute of Technology
GITAM University

2024-2025

Y V Appa Rao VLSI Design (Module I)


Introduction to Verilog HDL

Outline

1 Introduction to Verilog HDL


Procedural assignments

Y V Appa Rao VLSI Design (Module I)


Procedural assignments
Introduction to Verilog HDL
References

Assignments in Verilog

(i) Continuous assignments: Assign values for various nodes in


Combinational logic circuits
Explicit continuous assignment: ”assign” keyword can be used
for the assignment after the net is separately declared (wire)
Implicit continuous assignment: The values is assigned in
declaration without using the keyword ”assign”
(ii) Procedural assignments: Used to model registers and
Finite state machines (FSMs) [Synchronous sequential logic]

Y V Appa Rao VLSI Design (Module I)


Procedural assignments
Introduction to Verilog HDL
References

Procedural assignments
w.k.t Concurrent statements are useful in modeling
Combinational logic
Synchronous Sequential logic: Unlike Combinational logic,
Sequential logic circuits are sensitive to events on the clock
signal (Positive edge or Negative edge)
Input changes are sensed by the Sequential logic only at the
specified clock edge and the output and state changes occur
on the respective edge of the clock signal
Modeling Sequential logic: Primitives to model ”selective
activity conditional on clock, Edge triggered elements,
sequence of operations (Setting or Resetting)” etc. are
required
Types of Procedural assignments for modeling Sequential
logic: ”Initial” and ”always” blocks
Y V Appa Rao VLSI Design (Module I)
Procedural assignments
Introduction to Verilog HDL
References

Procedural assignments

Initial block
Initial blocks execute only once at time zero (Simulation time)
All the statements within the block are executed; don’t wait
for an event
Useful in Simulation and Verification
initial blcoks are not synthesizable, i.e., they can’t be
translated into hardware
declaration: initial begin //Sequential-statements end

Y V Appa Rao VLSI Design (Module I)


Procedural assignments
Introduction to Verilog HDL
References

Procedural assignments

always block
always blocks execute repeatedly
All the statements within the block are executed; based on an
event
Useful in Simulation and Verification (like clock signal or any
other periodic signal generation)
always blcoks are synthesizable, for e.g. a Synchronous counter
can be described in Verilog using Procedual assignments
(if-else or case statement)
declaration: always @(sensitivity-list) begin
//Sequential-statements end
The variables to which values are to be assigned in an always
block should be of type ”reg”, other data tpes are illegal

Y V Appa Rao VLSI Design (Module I)


Procedural assignments
Introduction to Verilog HDL
References

Procedural assignments

always block
Sequential statements: When an always statement is used, the
statements between the ”begin” and the ”end” are executed
sequentially rather than concurrently
Sensitivity list: The always block gets executed whenever any
signal in the sensitivity list changes
”@” symbol should be used before the sensivity list
Whenever any signal in the sensitivity list changes, the
sequential statements in the always block are executed
sequentially, one time
When an always block finishes executing, it goes back to the
beginning and waits for a signal in the sensitivity list to change
again

Y V Appa Rao VLSI Design (Module I)


Procedural assignments
Introduction to Verilog HDL
References

Procedural assignments

always block
”*” operator: A ”*” in the sensitivity list causes always block
to execute whenever any one of the signal in the list changes
Assignment operator: Outside the always block the assignment
is a ”Concurrent assignment”
Types of evaluation for Sequential statements in an always
block: (i) Blocking assignment (ii) Non-Blocking assignment
Blocking assignment: A blocking assignment has to be
completed before the next statement gets executed
”=” operator is used for blocking assignments
Non-Blocking assignment: Allows succeedng statements to be
evaluated without blocking the flow
Several assignments can be evaluated at the same time, as
they are non-blocking in nature

Y V Appa Rao VLSI Design (Module I)


Procedural assignments
Introduction to Verilog HDL
References

Procedural assignments

always block
Statements in the ”always” block can be executed at the same
time if they are non-blocking, otherwise they are executed
sequentially
”always” block can be used for modeling Combinational logic
and Sequential logic
However, ”always” statements are not necessary for modeling
Combinational logic

Y V Appa Rao VLSI Design (Module I)


Procedural assignments
Introduction to Verilog HDL
References

Procedural assignments

always block
”=” assignment operator is concurrential outside the always
block, while it is sequential in nature inside the always block
(Blocking)
Use non-blocking assignments in ”always” blcok for
”Sequential” logic, while blocking assignments for
”Combinational” logic
Noe: Don’t mix blocking and non-blocking assignments in the
same always block
If the sensitivity list is omitted, delays or time-controlled events
must be specified inside the always block

Y V Appa Rao VLSI Design (Module I)


Procedural assignments
Introduction to Verilog HDL
References

References

Charles H. Roth, Lizy Kurian John, and Lee


Digital Systems design Using Verilog
Cengage Learning, 2016.
Douglas A. Pucknell, Kamran Eshraghian
Digital Systems design Using Verilog
Cengage Learning, 2016.

Y V Appa Rao VLSI Design (Module I)

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