Introduction to Verilog HDL

VLSI Design (Module I)

Y V Appa Rao

Department of Electrical, Electronics and Communication Engineering

GITAM Institute of Technology
GITAM University

2024-2025

Y V Appa Rao VLSI Design (Module I)

 Introduction to Verilog HDL

Outline

1 Introduction to Verilog HDL

Verilog descriptions for Combinational logic

Y V Appa Rao VLSI Design (Module I)

 Verilog descriptions for Combinational logic
Introduction to Verilog HDL
References

Introduction

Concurrency
HDLs use statements that execute concurrently since they
must model real hardware in which all the subsystems are in
operation at the same time
General-purpose computer languages can’t describe
concurrently operating hardware, as they are executed
sequentially
To model Combinational logic, it is essential to simulate the
execution of several parts of the circuit at the same
time-Concurrential execution
To model Sequential logic, it is necessary incorporate edge
sensitive ”always”block, to describe Synchronous behavior of
the circuit

Y V Appa Rao VLSI Design (Module I)

 Verilog descriptions for Combinational logic
Introduction to Verilog HDL
References

Concurrent statements or Continuous assignments

Concurrent statements are always ready to execute

Evaluated any time and every time a signal on the RHS of the
statement changes
The order of the statements is not relevant for concurrential
execution
The signal assignment operator ”=”
”assign” statement is used to assign a value computed on the
right side to the signal on the left side
A signal declaration in Verilog usually corresponds to a signal
in a physical system

Y V Appa Rao VLSI Design (Module I)

 Verilog descriptions for Combinational logic
Introduction to Verilog HDL
References

Concurrent statements or Continuous assignments

Interpretation of Continuous assignments by Verilog Simulator

Any time a signal on the RHS changes, the expression is

immediately reevaluated
Updates the signal on the LHS
Delays: Similar to the propagation delays associated with gates
and wires, delays in the continuous assignments are meaningful
The order of the statements is not important
The expression (on the RHS) is evaluated, and the signal on
the LHS is scheduled to change after the elapsement of the
delay
The delay is optional

Y V Appa Rao VLSI Design (Module I)

 Verilog descriptions for Combinational logic
Introduction to Verilog HDL
References

Concurrent statements or Continuous assignments

Interpretation of Continuous assignments by Verilog Simulator

If the delay is omitted, the signal on the LHS will be updated

immediately
The time at which the statement executes and the time at
which the signal is updated are not the same if the delay is
specified
Even if a Verilog HDL program has no explicit loops,
concurrent statements execute repeatedly as if they were in a
loop
Contrast to VHDL, delta delays are not displayed for
continuous assignmnets in Verilog
Delta delay: It is an infinitesimally small delay used to
maintain sequnetiality detween dependent events happening at
the same time

Y V Appa Rao VLSI Design (Module I)

 Verilog descriptions for Combinational logic
Introduction to Verilog HDL
References

Syntax for writing a valid Verilog description

Verilog is case sensitive: Upper-case and lower-case letters are

treated as different by the compiler and by the simulator
Identifiers: Contain letters, numbers, underscore character ( ),
and $ sign
An identifier must start with a letter or character, it can’t
start with a number or a $ sign
The $ sign is reserved as the first character for ”System tasks”
Every Verilog statement ends with a semicolon ( )

Y V Appa Rao VLSI Design (Module I)

 Verilog descriptions for Combinational logic
Introduction to Verilog HDL
References

Syntax for writing a valid Verilog description

Spaces, tabs, carriage returns are treated in the same way

i.e., A Verilog statement can be written over several lines, or
several statements can be placed on one line
Wire (or net) type signals in Verilog, generally has a value of
0 or 1
The values on nets can be represented as binary, decimal, or
hexadecimal (b,d, and h)

Y V Appa Rao VLSI Design (Module I)

 Verilog descriptions for Combinational logic
Introduction to Verilog HDL
References

Lexical conventions in Verilog

Vector: A 1-d array of bit signals is referred to as a vector,

e.g. 4-bit vector: wire [3:0] B; indicates a multiple bit wire
Array of gates: assign C = A & B; // bitwise ”AND” (&)
operator applied to two n-bit vectors ”A” and ”B”
Module in Verilog: A module in Verilog is a basic building
blocks that declares input, output signals and specifies the
operation of the digital system to be designed
Declaration of ”wire”: In Verilog internal signals are declared
as wire
Input/Output declaration part can be considered as the black
box picture of the module being designed and its external
interface
”inout”mode can be used for bi-directional signals

Y V Appa Rao VLSI Design (Module I)

 Verilog descriptions for Combinational logic
Introduction to Verilog HDL
References

Lexical conventions in Verilog

Module instantiation: When we describe a digital system we

must specify input and output signals and also specify the
functionalities of the modules (instances) that are part of the
system
Each instance has a hierarchy of ports (port map): The
instance created has a one-to-one correspondence with the
signals in the actual module
This implies the order of the signals in the instantiated
module must be the same as the order of signals in the port of
the module declaration (Positional association)

Y V Appa Rao VLSI Design (Module I)

 Verilog descriptions for Combinational logic
Introduction to Verilog HDL
References

Lexical conventions in Verilog

Testbench: To generate test patterns to be applied to the

device or circuit under test (DUT/CUT) for verifying the
functionality, or timing specifications
Except for the ”Test bench”, each module declaration
includes a list of interface signals that can be used to connect
to other modules or to the outside world
Order of precedence: Verilog does not specify an order of
precedence for logical operators except the ”NOT” operator

Y V Appa Rao VLSI Design (Module I)

 Verilog descriptions for Combinational logic
Introduction to Verilog HDL
References

Lexical conventions in Verilog

Testbench: To generate test patterns to be applied to the

device or circuit under test (DUT/CUT) for verifying the
functionality, or timing specifications
Except for the ”Test bench”, each module declaration
includes a list of interface signals that can be used to connect
to other modules or to the outside world
Operators in Verilog include Logical, Bitwise, Arithmetic,
Concatenation and Conditional operators
Order of precedence for logical operators: Verilog does not
specify an order of precedence for logical operators except the
”NOT” operator

Y V Appa Rao VLSI Design (Module I)

 Verilog descriptions for Combinational logic
Introduction to Verilog HDL
References

Verilog assignments

Two types of assignments in Verilog

(i) Continuous assignments: To assign values for various nodes
in Combinational logic circuits
Explicit continuous assignment: ”assign” keyword can be used
for the assignment after the net is separately declared
Implicit continuous assignment: The values is assigned in
declaration without using the keyword
(ii) Procedural assignments: Used to model registers and
Finite state machines (FSMs)
The keyword used: ”always”

Y V Appa Rao VLSI Design (Module I)

 Verilog descriptions for Combinational logic
Introduction to Verilog HDL
References

References

Charles H. Roth, Lizy Kurian John, and Lee

Digital Systems design Using Verilog
Cengage Learning, 2016.
Douglas A. Pucknell, Kamran Eshraghian
Digital Systems design Using Verilog
Cengage Learning, 2016.

Y V Appa Rao VLSI Design (Module I)