The document provides an overview of the ARM processor architecture, detailing its register set, operating modes, and instruction sets. It explains the function of various registers, including general-purpose and special registers, as well as the significance of the Program Status Register (PSR) and the different processor modes. Additionally, it covers instruction execution mechanisms such as pipelining and the handling of exceptions and interrupts.
The document provides an overview of the ARM processor architecture, detailing its register set, operating modes, and instruction sets. It explains the function of various registers, including general-purpose and special registers, as well as the significance of the Program Status Register (PSR) and the different processor modes. Additionally, it covers instruction execution mechanisms such as pipelining and the handling of exceptions and interrupts.
The document provides an overview of the ARM processor architecture, detailing its register set, operating modes, and instruction sets. It explains the function of various registers, including general-purpose and special registers, as well as the significance of the Program Status Register (PSR) and the different processor modes. Additionally, it covers instruction execution mechanisms such as pipelining and the handling of exceptions and interrupts.
The document provides an overview of the ARM processor architecture, detailing its register set, operating modes, and instruction sets. It explains the function of various registers, including general-purpose and special registers, as well as the significance of the Program Status Register (PSR) and the different processor modes. Additionally, it covers instruction execution mechanisms such as pipelining and the handling of exceptions and interrupts.
N = Negative result from ALU I = 1: Disables the IRQ. Z = Zero result from ALU F = 1: Disables the FIQ. C = ALU operation Carried out V = ALU operation oVerflowed T Bit Architecture xT only Sticky Overflow flag - Q flag T = 0: Processor in ARM state Architecture 5TE/J only T = 1: Processor in Thumb state Indicates if saturation has occurred Mode bits J bit Specify the processor mode Architecture 5TEJ only J = 1: Processor in Jazelle state
039v12 6 Operating modes Processor modes determines which registers are active & access rights to CPSR itself. Each processor mode is either privileged or non privileged. Privileged mode- allows full read-write access to CPSR. Non privileged mode- allows only read access to control field but read & write access to condition flags. There are 7 processor modes- Six privileged- system, supervisor, abort, undefined, Interrupt request(IRQ), Fast interrupt request (FIQ) One- Non privileged Abort- CPU enters in abort mode when there is a failed attempt to access a memory. FIQ& IRQ modes corresponds to 2 interrupt levels available on ARM. Supervisor mode- CPU enters in this mode after reset & it is the mode in which OS kernel operates in. System- it is a special version of user mode that allow full access to CPSR. Undefined- CPU enters in this mode when it comes across the instruction that is not defined or not supported by implementation. User- it is used for programs & applications.
039v12 7 Changing mode on an exception
039v12 8 Processor modes
039v12 9 ARM & Thumb Instruction set features
039v12 10 Condition flags
039v12 11 Pipeline- A mechanism the RISC processor uses to execute the instruction It speeds up the execution by fetching next instruction while the other instructions are being decoded & executed.
039v12 12 Pipeline example- Consider a program sequence- ADD R1,R2,R3 SUB R4,R5,R6 CMP R8,R9
039v12 13 ARM9- 5 STAGE PIPELINE ARM9 increases the pipeline depth to 5 stages. It adds a memory & write back stage that allows ARM9 to process on average 1.1 dhrystone MIPS per MHz. Increase in instruction throughput by 13 % compared to ARM7. Max. core frequency attainable by ARM9 is also higher.
039v12 14 ARM10- 6 STAGE PIPELINE
ARM10 increases the pipeline depth still furhter by
adding one more stage. It adds a issue stage that allows ARM9 to process on average 1.3 dhrystone MIPS per MHz. Increase in instruction throughput by 34 % compared to ARM7. Max. core frequency attainable by ARM9 is also higher.
039v12 15 Exceptions, interrupts & vector table Whenever exception or interrupt occurs, the CPU sets PC to a specific memory address. This address is within a special address range called vector table. Entries in the vector table are the special instructions that branch to a specific routines designed to handle a particular interrupt or exception. Memory address 0x00000000 is reserved for vector table, a set of 32 bit words. Some processors allows to locate a vector table at higher address 0xffff0000. OS can take advantage of this feature. When interrupt occurs, the CPU starts loading instruction from interrupt vector table. Each vector entry contains a form of branch instruction pointing to a start of specific routine. 039v12 16 Exceptions, interrupts & vector table
039v12 17 039v12 18 Vector table-
039v12 19 ARM FAMILY COMPARISION
039v12 20 ARM INSTRUCTION SET- Most of the instructions in ARM state can be executed on conditional basis
• They are-MOVE instructions,arithmetic, logical comparison & multiply instructions. • Most data processing instructions can process one of their operands using barrel shifter. • If we use suffix “s” on a data processing instruction, then it updates the flags in cpsr.
039v12 24 DATA PROCESSING INSTRUCTIONS-
039v12 25 BARREL SHIFTER OPERATIONS
039v12 26 DATA PROCESSING INSTRUCTIONS-
039v12 27 DATA PROCESSING INSTRUCTIONS-
039v12 28 BARREL SHIFTER
039v12 29 BARREL SHIFTER
039v12 30 ARITHMETIC INSTRUCTIONS
039v12 31 ARITHMETIC INSTRUCTIONS
039v12 32 LOGICAL INSTRUCTIONS
039v12 33 COMPARE INSTRUCTIONS
039v12 34 MULTIPLY INSTRUCTIONS
039v12 35 BRANCH INSTRUCTIONS-
039v12 36 LOAD-STORE INSTRUCTIONS-
039v12 37 LOAD-STORE INSTRUCTIONS-
039v12 38 LOAD-STORE INSTRUCTIONS-
039v12 39 EXAMPLES -
039v12 40 SINGLE REGISTER LOAD-STORE ADDRESSING
039v12 41 MULTI REGISTER TRANSFER
039v12 42 EXAMPLES-
039v12 43 MULTIPLE REGISTER TRANSFER-
039v12 44 MULTIPLE REGISTER TRANSFER ADDRESSING MODES-
039v12 45 EXAMPLES-
039v12 46 STACK OPERATIONS- ARM uses load –store instructions to carry out stack operations. POP operation uses load multiple instruction. PUSH operation uses store multiple instruction. User can decide how the stack will grow (up or down). A stack is either ascending(A) or descending(D). Ascending stack grows towards higher memory addresses. Descending stack grows towards lower memory addresses. When we use full stack(F),the SP points to an address that is last used or full location. When we use empty stack(E), the SP points to an address that is first unused or empty location. 47 039v12 STACK OPERATIONS-
STMED
039v12 48 STACK OPERATIONS-
039v12 49 SWAP INSTRUCTION
039v12 50 SWAP INSTRUCTION-
039v12 51 SOFTWARE INTERRUPT INSTRUCTION-
039v12 52 039v12 53 039v12 54 039v12 55 THUMB INSTRUCTION SET
039v12 56 INTRODUCTION
039v12 57 DECODING
039v12 58 039v12 59 039v12 60 ARM –THUMB INTERWORKING A name given to method of linking ARM and thumb code together for assembly and C/C++. It handles a transition between 2 states. Extra code named veneer code is needed to carry out the transition. BX and BLX instructions causes a switch between ARM and thumb state. There are 2 versions of BX and BLX. ARM version & thumb version. Syntax:- BX Rm BLX Rm | label
039v12 68 Whenever an exception causes a mode change, the core automatically- Saves the CPSR to the SPSR of exception mode Saves the PC to the LR of exception mode Sets the CPSR to the exception mode sets the PC to the handler of the exception mode.
