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Minimum input delay is greater than maximum input delay

The document discusses how to specify a minimum input delay that is greater than the maximum input delay in Design Compiler. By default, the tool uses the last applied value for both delays if the minimum exceeds the maximum. To allow independent setting of these delays, the variable 'allow_input_delay_min_greater_than_max' can be set to true.

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8 views

Minimum input delay is greater than maximum input delay

The document discusses how to specify a minimum input delay that is greater than the maximum input delay in Design Compiler. By default, the tool uses the last applied value for both delays if the minimum exceeds the maximum. To allow independent setting of these delays, the variable 'allow_input_delay_min_greater_than_max' can be set to true.

Uploaded by

xylcool5
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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Dec 11, 2019 • Knowledge

Title
Minimum input delay is greater than maximum input delay

Description
Minimum input delay is greater than maximum input delay
Question:

For input ports how can I specify a minimum input delay that is greater
than the maximum input delay?

Answer:
By default if the minimum delay specified on an input port is greater
than the maximum delay specified on the port, Design Compiler
uses which ever value was last applied. The following example
shows how Design Compiler handles this type of situation:

dc_shell-t> set_input_delay -clock clk -min 2 in


dc_shell-t> set_input_delay -clock clk -max 1 in

Design Compiler will take 1 library time units as the input delay
for both minimum (hold) and maximum (setup) analysis.

You can verify this reaction by giving report_port -verbose


dc_shell-t > report_port -verbose in

.....
....
Input Delay
Min Max Related Max
Input Port Rise Fall Rise Fall Clock Fanout
----------------------------------------------------------------
in 1.00 1.00 1.00 1.00 clk --

----------------------------------------------------------

If the constraints were applied in reverse order i.e

dc_shell-t> set_input_delay -clock clk -max 1 in


dc_shell-t> set_input_delay -clock clk -min 2 in

If the constraints were applied in reverse order,

dc_shell-t> set_input_delay -clock clk -max 1 in


dc_shell-t> set_input_delay -clock clk -min 2 in

Design Compiler uses two library time units as the input


delay for minimum (hold) and maximum (setup) analysis.

...........
.........

Input Delay
Min Max Related Max
Input Port Rise Fall Rise Fall Clock Fanout
------------------------------------------------------------
in 2.00 2.00 2.00 2.00 clk --

------------------------------------------------------

To control this reaction, use the variable


allow_input_delay_min_greater_than_max

The default value of this variable is false. Setting this variable to


true will allow minimum input delay greater than maximum input delay to be
set independently of the command order.

Workaround
Product L1
Design Compiler (/s/detail/01t1U000003IXzwQAG)

Additional Product(s)

Article Number
000010000

Last Published Date


12/11/2019, 12:22 PM

Article Record Type


How To

URL Name
Minimum-input-delay-is-greater-than-maximum-input-delay-1576091141735

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