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Script To Generate Input - Output Constraint With All Related Clocks

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thsim85
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17 views

Script To Generate Input - Output Constraint With All Related Clocks

genus document

Uploaded by

thsim85
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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Script to generate input/output constraint with all related clocks

Explanation of Script
This script only works in Genus Common UI. If you run MMMC mode, you need to use set_interactive_constraint_modes to set one specified mode before you
source this script.

Usage
This script can generate input/output delay constraint with all related clocks.

User can change the input_delay_factor and output_delay_factor. Directly source this script in Genus Common UI; it will generate two output files:
input_delay_constraint.tcl and output_delay_constraint.tcl.

Code
set input_delay_factor 0.5
set output_delay_factor 0.5

echo "" > input_delay_constraint.tcl


echo "" > output_delay_constraint.tcl

foreach_in_collection input_ports [all_inputs] {


if { [get_db [get_ports $input_ports] .clocks] == "" } {
set clock_list ""
set full_name [get_object_name $input_ports]
#echo $full_name
foreach_in_collection end_pins [get_object_name [all_fanout -from $full_name -flat -endpoints_only]] {
foreach my_clock [get_db [get_pins -of_objects [get_cells -of_objects [get_pins $end_pins]] -filter "is_clock == true"]
.clocks] {
set my_clock_fullname [get_object_name $my_clock]
if { [lsearch $clock_list $my_clock_fullname] == -1 } {
lappend clock_list $my_clock_fullname
}
}
}
#echo $clock_list
foreach valid_clock $clock_list {
set period [get_db [get_clocks $valid_clock] .period]
set div_period [get_db [get_clocks $valid_clock] .divide_period]
set real_period [expr $period / $div_period ]
echo "set_input_delay -clock $valid_clock -add_delay [expr $input_delay_factor * $real_period / 1000] $full_name" >>
input_delay_constraint.tcl
}
}
}

foreach_in_collection output_ports [all_outputs] {


set clock_list ""
set full_name [get_object_name $output_ports]
#echo $full_name
foreach_in_collection start_pins [get_object_name [all_fanin -to $full_name -flat -startpoints_only]] {
foreach my_clock [get_db [get_pins $start_pins] .clocks] {
set my_clock_fullname [get_object_name $my_clock]
if { [lsearch $clock_list $my_clock_fullname] == -1 } {
lappend clock_list $my_clock_fullname
}
}
}
#echo $clock_list
foreach valid_clock $clock_list {
set period [get_db [get_clocks $valid_clock] .period]
set div_period [get_db [get_clocks $valid_clock] .divide_period]
set real_period [expr $period / $div_period ]
echo "set_output_delay -clock $valid_clock -add_delay [expr $output_delay_factor * $real_period / 1000] $full_name" >>
output_delay_constraint.tcl
}
}

Internal Notes
None

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