International Journal of Science, Engineering and Technology Research (IJSETR), Volume 5, Issue 2, February 2016

Implementation and Analysis of Different Line

Coding Schemes using Verilog
Ankit Gupta, Gurashish Singh

Generally, the Line Coding schemes are implemented on

Abstract—Line Coding is a discipline in the field of trainers in educational institutions. With the aid of this
telecommunication which governs several kinds of sophisticated proposed project, one can simulate the Line Coding using
coding methods for transmitting a digital signal. It is intensively
versatile HDL (Hardware Description Language), Verilog.
employed in baseband communication systems. In educational
institutions, Line Coding is practiced on electronic trainers. Verilog is a Hardware Description Language, which is
This paper represents the implementation of different Line widely used as a textual format for describing electronic
Coding schemes like NRZ, RZ and Biphase on the Verilog-HDL circuits and systems. It came into existence as a proprietary
software platform. The Verilog-HDL code is simulated and language supported by a simulation environment that was
analyzed using ModelSim tool of MentorGraphics. The results first to support mixed-level design representations
have been observed on the software interface in the form of comprising Switches, Gates, Register Transfer Level (RTL)
various waveforms. An attempt has been made for a
user-friendly software oriented approach to study different
circuits, and higher level abstractions of digital circuits. The
kinds of Line Codes which eventually poses a merit over simulation environment provides an authentic and uniform
traditional trainers. method to implement and verify digital circuits.

Index Terms—Biphase, HDL, Line Coding, NRZ, RZ and 2. THE LINE CODING SCHEMES
Verilog.
The various Line Coding schemes that have been discussed
1. INTRODUCTION
in this paper are as follows:

In every digital transmission, the data has to be reformatted 2.1 Not-Return to Zero (NRZ):
before modulation. Modulation is a technique of producing a
new signal by mixing it with a sinusoid of high frequency. It is one of the most commonly used signaling scheme which
Expressing the digital data in a specified format is known as deals with different levels for different symbols. During the
Line Coding. It is a process of encoding every bit into some clock interval, the value of the signal does not return to zero.
signal elements where in every signal element is a discrete For NRZ-Unipolar, the bit ‘1’ is represented by voltage +V
and discontinuous voltage pulse. This has huge application in whereas ‘0’ is represented by voltage 0. If the bit ‘0’ is
modulation. It is an important part of any digital represented by a negative –V, the signal is called
communication system. It has already been established that it NRZ-Bipolar.
is dependent on the available system parameters. As a block,
it takes digital data as an input and gives digital data as output 2.1.1 NRZ- Level (NRZ-L):
(not necessarily binary). So, it can be considered as a Digital
Logic System. When bits are represented with certain levels for the two
symbols, it is called as NRZ - Level (NRZ-L).
Line Coding is done to achieve many goals such as
 Self-clocking, A1 (t) = +V, 0 ≤ t ≤ Tb (2)
 In-service error monitoring, A0 (t) = 0, 0 ≤ t ≤ Tb (3)
 Introducing spectral nulls in dc frequency when channel is
ac coupled, At receiver side, the clock signal is not directly available.
 Modifying the signal spectrum, thereby further reducing So, it can be extracted using the receiver signal. This is also
cross-talk in radio-frequency interferences and foreign called self-clocking and forms a basis for clock regeneration.
systems, It is required that transmitter and receiver clock should be
 To reduce the complexity in equalization, detection, timing synchronized for apt recovery of data. However, in NRZ-L
recovery circuits and echo cancellations etc. [1]. coding, the synchronization and clock information is lost
whenever a long stream of zeros or ones is encountered.
The encoding scheme is chosen on the basis of various Clock regeneration is difficult in this case.
distinct characteristics. Some vital features to demarcate and This encoding has a maximum rate of change which is
choose various kinds of Line Coding schemes are Bandwidth, nearly equal to half of the clock input (alternate 1’s and 0’s).
Self-synchronization, Error-detection, Differential encoding, NRZ-L requires comparatively lower bandwidth than the
Dc-component and Transparency. other schemes.
For a system to be ac coupled, the dc energy is eliminated
from its power spectrum. Hence, magnetic recording systems

395
ISSN: 2278 – 7798 All Rights Reserved © 2016 IJSETR
 International Journal of Science, Engineering and Technology Research (IJSETR), Volume 5, Issue 2, February 2016

or systems with transformer coupling have very less When a string of data ‘1’ is transmitted, the maximum
sensitivity to low frequency signal components and thence signal frequency of RZ signal occurs that implies the
information gets lost. NRZ-L contains dc level therefore it bandwidth. It is similar as sending two logic levels in a single
can't be used in systems which cannot pass dc signals. NRZ-L clock period. Therein, the signal frequency is equal to the
is most commonly in digital logic circuits [3]. clock rate. It means RZ requires twice bandwidth as used in
NRZ scheme. It does not have error detecting capability.
2.1.2 NRZ- Mark (NRZ-M): Passing of DC-level is a problem in RZ waveform i.e.
systems that do not allow DC levels to pass, that results in
When bits are represented by change in levels, then we information loss in RZ signals [4].
refer it as differential coding. When level changes for mark
points i.e. bit 1, and then we call it NRZ-Mark (NRZ-M). It 2.2.2RZ- Bipolar:
means that on arrival of bit ‘1’ at input, the polarity of the
signals changes and no change takes place for bit ‘0’. In long range transmission, stream of zeros can create
The timing implementation can be extracted for the synchronization problems. The general RZ-Bipolar has the
NRZ-M signal unless there are long periods which do not following representation:
contain any level change. This corresponds to long stream of
bit ‘0’ in data. Long stream of ones is not a problem as A1 (t) = +V, 0 ≤ t ≤ Tb/2 (6)
changes occur at each mark point (1’s). 0, Tb/2 ≤ t ≤ Tb
It is somewhat similar to NRZ-L in terms of bandwidth A0 (t) = -V, 0 ≤ t ≤ Tb/2 (7)
utilization and dc level passing. However, as NRZ-M is 0, Tb/2 ≤ t ≤ Tb
independent of absolute level, therefore, receiver simply
needs to know the level changes, which is an advantage in This is a three level code i.e. +V level for denoting data ‘1’,
phase shift keying. - V level for denoting data bit ‘0’, and level zero as the signal
This type of encoding is primarily used in magnetic tape is RZ format (i.e. at Tb/2 it returns to 0).
recording. Maximum signal frequency is same as the clock frequency.
Thus, bandwidth requirement for RZ-Bipolar is double to that
2.1.3 NRZ- Space (NRZ-S): of NRZ and same as RZ-Unipolar and Biphase codes.
One of the most important advantages of RZ-Bipolar is that
When level changes for space points i.e. bit ‘0’, and then it is timing information is very easy to obtain. There is no loss of
referred as NRZ-Space (NRZ-S). It means that on arrival of synchronization irrespective of data bits. However, due to the
bit ‘0’ at input, the polarity of the signals changes and no generation of three levels, the transmitter complexity
change takes place for bit ‘1’. NRZ-S is, in a way, a increases.
complement of NRZ-M. A ‘1’ or mark is represented by no DC level passing is dependent on the data bits. In a time
change in level and a ‘0’ or space is represented by a change frame which contains equal number of 1’s and 0’s, the DC
in level i.e. level changes from +V to 0 or vice versa. level is null. But, if the number of bits is unbalanced, there
Like NRZ-M, the bandwidth requirements and passing of Dc exists a non-zero DC level.
level is same as that for NRZ-L. Also if there are long streams The decoder design for this encoding scheme is easy. It
of ‘1’ in data, there is no level change in NRZ-S waveform requires a comparator with reference voltage set to zero volts.
and clock regeneration becomes difficult.
2.2.3 RZ-Alternate Mark Inversion (RZ-AMI):
2.2 Return to Zero (RZ):
It is a code which contains positive and negative pulses of
This type of encoding scheme incorporates signal whose equal magnitude (i.e. +A and –A) alternatively to represent
value returns to zero at time Tb/2 (i.e. half the bit period). RZ symbol ‘1’. For representation of bit ‘0’, zero amplitude is
codes (Unipolar, Bipolar and AMI) are widely used in used.
baseband data transmission and also in magnetic recordings.
For RZ-AMI, the symbols can be defined by
2.2.1RZ-Unipolar:
A1 (t) = +V, 0 ≤ t ≤ Tb/2 (8)
The RZ unipolar scheme may be implemented by 0, Tb/2 ≤ t ≤ Tb
representing bit ‘1’ by the signal:
or A1 (t) = -V, 0 ≤ t ≤ Tb/2 (9)
A1 (t) = +V, 0 ≤ t ≤ Tb/2 (4) 0, Tb/2 ≤ t ≤ Tb
0, Tb/2 ≤ t ≤ Tb
A0 (t) = 0, 0 ≤ t ≤ Tb (10)
And bit '0' by the signal:
A0 (t) = 0, 0 ≤ t ≤ Tb (5) The signal returns to zero at time Tb/2 for each bit ‘1’. Due
to alternative nature of bit ‘1’, the clock synchronization
It has rising and falling transition for each data 1, therefore, problem is less as compared to the NRZ technique.
the number of transitions increases. As a result, clock Long string of zeros implies null level in the output
regeneration is simpler than NRZ scheme. This type of waveform which may cause the receiver to step out of
coding is not preferable if long stream of zeros occurs.
396
ISSN: 2278 – 7798 All Rights Reserved © 2016 IJSETR
 International Journal of Science, Engineering and Technology Research (IJSETR), Volume 5, Issue 2, February 2016

synchronization. The generation of three levels makes the

transmitter design complex. In this coding scheme, a transition occurs at the beginning of
AMI codes are independent of DC level because bit ‘1’ is every bit interval. A ‘1’ is represented by a second transition
represented by alternative levels of equal amplitudes and one-half bit interval later (i.e. at Tb/2); whereas a zero is
different polarity. Hence, AC-coupled communication represented by no second transition [8].
systems can easily employ RZ-AMI coding [5].
Transmission rate is equal to two transitions per period (as Bandwidth requirements and passing of DC level is
it is RZ) in case of a string of 1’s. Thus, the bandwidth of somewhat similar to Biphase-L. Clock regeneration is easier
RZ-AMI is twice that of NRZ codes. than Biphase-L. This is because at each positive edge of the
The advantage of AMI is quoted in case where if noise clock, a transition certainly occurs in Biphase-M encoding.
corrupts the data bit ‘1’ (such that it acquires the same
polarity as the previous ‘1’ bit), the coding rule will be 1=
violated. Thence, transmitter is required to re-send the string.
In this way, the transmission reliability is increased in AMI
and it finds wide application in telecommunication systems. 0 Tb OR 0 Tb

2.3 Biphase Coding:

0=
The Biphase coding technique contains at least one
transmission per bit interval irrespective of the input data.
Therefore, its maximum frequency is same as the data clock OR
rate. The required bandwidth is same as RZ codes and is 0 Tb 0 Tb
double of NRZ codes. It finds application in magnetic
recording systems, satellite telemetry links and optical Fig.2 Representation of ‘1’ and ‘0’ bits in Biphase-M
communication [6].
2.3.3 Biphase Space Coding:
2.3.1 Biphase Level Coding:
Its operation is complementary to that of Biphase-M. In
This coding is also referred as the Manchester Coding. In Biphase-S, a transition occurs at the beginning of every bit
this, bit ‘1’ is represented by a pulse in the first half of the interval. A ‘0’ bit is represented by a second transition at
clock period whereas bit ‘0’ is represented by a pulse in the one-half bit interval (at Tb/2). On other hand, bit ‘1’ does not
second half of the clock period. have a second transition within a single clock pulse.
Biphase-S shares all characteristics (bandwidth, clock
A1 (t) = +V, 0 ≤ t ≤ Tb/2 (11) recovery, and DC level passing) similar to Biphase-M.
-V, Tb/2 ≤ t ≤ Tb

A0 (t) = -V, 0 ≤ t ≤ Tb/2 (12) 1=

+V, Tb/2 ≤ t ≤ Tb

OR
Bit ‘0’: Bit ‘1’: 0 Tb 0 Tb

0=

0 Tb 0 Tb
0 Tb OR 0 Tb
Fig.1 Representation of ‘1’ and ‘0’ bits in Biphase-L
Fig.3 Representation of ‘1 and ‘0’ bits in Biphase-S
Biphase code has high level for half of each bit interval and
opposite polarity (low) for second half, irrespective of data. Commonly, Line Coding schemes are used for digital data
Therefore DC level becomes null. As a result, it can be used transport, digital baseband modulation or digital baseband
in AC coupled circuits. transmission methods.
There are many transitions in the Biphase coded waveform In coherence with the above discussion regarding Line
Coding schemes, there are subtle differences amongst them
which make clock recovery easy [7].
which can be summarized and observed in the following
2.3.2 Biphase Mark Coding:
Table 1 [9].

397
ISSN: 2278 – 7798 All Rights Reserved © 2016 IJSETR
 International Journal of Science, Engineering and Technology Research (IJSETR), Volume 5, Issue 2, February 2016

Table 1 Comments for different Line Coding schemes cumbersome and require professional advice for
maintenance.
6. Many of the simulation tools for Verilog have an
open access on the internet. This is a merit over the
costly hardware trainers.

4. IMPLEMENTATION USING VERILOG

Abou-El-Azm has implemented Line Coding schemes on

the electronic trainer kit wherein there is an obvious presence
of errors during transmission. They have tried detecting and
correcting errors by re-transmitting the data block; which on
the whole, is time consuming and results in eventual loss of
system’s efficiency [10].

Hardware description language languages like Verilog and

VHDL are used commonly for design and implementation of
various digital systems. The choice of Verilog mainly
adheres to ease of programming and global acceptability. So,
we have devised and implemented the encoding schemes
using a Verilog Code.
The Line Coding schemes that have been implemented are
categorized in two types:

 Having two levels in the waveform

 Having three levels in the waveform

The first category consists of NRZ-L, NRZ-M, NRZ-S,

RZ-Unipolar, Biphase-L, Biphase-M, and Biphase-S. All
these signals are either having levels +V and 0 (like the NRZ
and RZ schemes in Unipolar format); or +V and -V (like the
Biphase codes).
3. COMPARISON OF SOFTWARE APPROACH AND As there are only two levels, therefore, only one bit is
CONVENTIONAL TRAINERS required for representation. +V level is represented by logic
level ‘1’ while other level is represented by logic level ‘0’.
The proposed project has some noteworthy advantages when
observed in comparison with the conventionally used The second category has only two schemes: RZ-Bipolar
electronic trainers. Some of them have been mentioned and RZ-AMI. Both have three levels which are +V, -V and 0.
below: For representing the three levels we require at least two bits.
The encoding scheme used is
1. Understanding the software is more convenient. It can
be simulated according to the requirements of the  +V is represented by 01
programmer.  0 is represented by 00
2. Many new coding schemes can be devised and tested  -V is represented by 11
on the Verilog, just merely with the help of code. Not
all coding schemes are formulated directly on the Amongst the three modeling styles in Verilog, the
hardware trainers. Rather they ought to be first Behavioral style of modeling has been used. The data
verified on the software platform. assignment statements have been used in ‘always’ block to
3. The trainer trainers act just like a black box. A learner account for the level transitions at the positive and negative
is not aware of the internal connections and circuits edge. From programming point of view, clock signal is
and also, how the output is being generated. Whereas, important for synchronization because changes made to a
the software approach requires programmer to first signal depend on the edges of the clock signal. Two ‘always’
understand the code and then simulate it. This way, blocks have been used in the Verilog code in which one is
the software approach is more learning-oriented. sensitive to the positive edge and other to its negative edge.
4. The hardware problems are a big deal while learning The transitions that occur at the positive edge are included in
on the conventional trainer trainers as they are more the former ‘always’ block and similarly, the changes that
wearisome. Moreover, a great deal of other hardware occur at the negative edge are included in the latter ‘always’
devices and accessories are also required like Data block.
generator, DSO (Digital Storage Oscillation),
connecting pins etc.
5. Software is portable and can be installed on almost all
operating systems, while Hardware trainers are bulky,

398
ISSN: 2278 – 7798 All Rights Reserved © 2016 IJSETR
 International Journal of Science, Engineering and Technology Research (IJSETR), Volume 5, Issue 2, February 2016

5. RESULTS AND OBSERVATIONS

Fig.4 Screenshot of Waveforms after Simulating NRZ Line Coding schemes

Fig. 5 Screenshot of Waveforms after simulating RZ Line Coding schemes

Fig. 6 Screenshot of Waveforms after simulating Biphase Line Coding schemes

The set of waveforms in Fig.4 shows the three NRZ In NRZ-S, a change in level takes place at data bit ‘0’ which
(Non-Return to Zero) outputs along with the CLK (clock) and occur at time instants 100ns, 400ns, 500ns and 700ns. No
the DATA input signal (10110010). The data is sampled at level changes takes place at other instants because of the data
positive edge of the clock only. It is observed that NRZ-L bit ‘1’.
output changes with the data at each positive clock edge. Its In Fig. 5, the waveforms displayed, are the result of
waveform resembles the data itself. NRZ-M and NRZ-S are simulation of RZ Line Coding schemes.
differential encoding schemes, which imply their value Here, the RZ-Unipolar takes the data value at clock’s
depends on the previous output as well. Thus, an initial 0 positive edge and holds it till half of the clock period. After
value is fed to the waveforms to obtain the first output. this, the output returns to zero and remains at ‘0’ value
In NRZ-M, a change in level takes place at data bit ‘1’ throughout the period.
which occur at time instants 0ns, 200ns, 300ns and 600ns. At The RZ-Bipolar is represented using two bits. Data ‘1’ is
other instants, no level changes takes place because of the denoted by bits ‘01’ for first half interval and ‘00’ for the
presence of ‘0’ bit. second half (according to Return to Zero scheme). Similarly
data ‘0’ is denoted by bits ‘11’ for first half interval and ‘00’

399
ISSN: 2278 – 7798 All Rights Reserved © 2016 IJSETR
 International Journal of Science, Engineering and Technology Research (IJSETR), Volume 5, Issue 2, February 2016

for the second half. The last output wave here is of RZ-AMI done. However, the merit of software based approach over
(Alternate Mark Inversion). This is also represented by two electronic trainer trainers has been explicitly explained,
bits per symbol. Data ‘0’ is witnessed as a ‘00’ for entire which is the main purpose of the paper.
clock period. Data ‘1’ first occurs as ‘01’ for first half period
and ‘00’ in second half. The next immediate occurring bit‘1’ ACKNOWLEDGMENT
is formatted as ‘11’ in first half period whereas ‘00’ in second
Sincerely, we would like to thank Ms. Monica Bhutani and
half. Thus, at instants 0ns and 300ns, data ‘1’ is ‘01’ and at
Mr. Abhishek Gagneja, faculty of ECE department, Bharati
instants 200ns and 600ns, data ‘1’ is ‘11’, thereby showing
Vidyapeeth’s College of Engineering, New Delhi who
the alternative nature of transition.
guided and inspired us to write this paper with ample
The last set of waveforms is displayed in Fig.06, which
enthusiasm and verve. Without them, the paper and the
shows the Biphase Codes.
project wouldn’t have been on a completion state till date.
The Biphase-Level code represents the data ‘1’ by a high
pulse in first half of clock period and data ‘0’ by high pulse in
REFERENCES
second half of clock period. Thus, the Fig.01 in Section 2.3.1
represents the data bits ‘0’ and ‘1’. Biphase-Mark and [1] V.Sneha Latha et al., “Performance evaluation of different line codes”,
Biphase-Space are also differential codes. Initial value of 0 IJCSE, vol.02, no.04, pp. 575-588, Aug-Sept 2011.
has been fed to them. At all positive edges, a transition in the [2] John G. Proakis, “Digital Signal Processing”, Pearson India, Fourth
Edition,2007
level occurs. [3] Bernard Sklar, “Digital communication: Fundamentals and
For Biphase-Mark, another transition occurs at middle of Application”, Pearson Education, IInd Edition, 2011.
clock period for data bit ‘1’ (mark-point) i.e. at instants 50ns, [4] Haykin,S., Communication Systems, IIIrd Edition, John Wiley & Sons,
250ns, 350ns and 650ns. Likewise, for Biphase-Space, the Inc., New York, 1994, ch.4.
[5] Samir Palnitkar, “Verilog HDL, A guide to digital design and
transition occurs for data bit ‘0’ at instants 150ns, 450ns, synthesis”, Prentice Hall, IInd Edition, 2003..
550ns and 750ns. [6] Cariolaro,G.L., Pierobon ,G.L and Pupolin, S.G. “Spectra of Blocked
Relative bandwidth utilization can also be compared using Coded Digital Signals” IEEE Transactions on Information Theory, Vol
the above waveforms. All NRZ waveforms have a frequency IT-28,No.3, May 1982.
[7] Cariolaro, G.L., and Tronca, G.P. “Spectral Analysis of variable length
which is half the clocking rate as there is at most one change coded digital signals” IEEE Transactions on communications, Vol
within a bit period. In RZ codes and Biphase codes, the COM-22, no.10,October 1974.
frequency is same as of the clock signal. This is so because [8] Couch, Leon W., “Digital and Analog communication systems”, Third
transitions occur at most twice within a clock period. Thus, Edition. MacMillan Publishing Company, New York, 1990.
[9] Communication Systems/Line Codes, Wikibooks.
RZ and Biphase codes require double bandwidth than NRZ https://en.wikibooks.org/wiki/Communication_Systems/Line_Codes
codes. [10] Abou-El-Azm, A., El. Daim,“ Error detection and optimum decoding
Ease of clock regeneration can also be observed using the line codes in digital transmission systems”, IEEE Radio Science
same set of waveforms. In NRZ codes, RZ-Unipolar and Conference, 1999. NRSC '99. Proceedings of the Sixteenth National,
Feb.1999
RZ-AMI long stream of zeros or ones or both causes no level
change in the coded waveform. Hence, there is a higher
chance of synchronization loss. On the other hand, RZ
bipolar and Biphase codes have ample number of transitions
due to which clock regeneration is easy, and probably cause
less synchronization loss.
This is a very efficient way of knowing how these coding
schemes actually work as compared to the trainer trainers
where the aforementioned bit by bit running procedure is not
possible. Hence, software simulation gives a better insight to
the students for analyzing the output with respect to varying
data input.

7. CONCLUSION AND FUTURE SCOPE

In this project work, the various Line Coding schemes that

are commonly employed in baseband modulation systems
have been discussed. Their vivid characteristics have been
studied. These different Line Coding schemes namely
NRZ-L, NRZ-M, NRZ-S, RZ-Unipolar, RZ-Bipolar,
RZ-AMI, Biphase-L, Biphase-M and Biphase-S, have been
implemented and simulated on Verilog-HDL using the
ModelSim tool of Mentor-Graphics. The methodology of
implementation and analysis of the results have been
specified. However as a limitation it may be said that a few
coding schemes that are used now-a-days have not been
discussed. This can be an extension to the project whereby
synthesis and FPGA implementation of the system can be

400
ISSN: 2278 – 7798 All Rights Reserved © 2016 IJSETR
 International Journal of Science, Engineering and Technology Research (IJSETR), Volume 5, Issue 2, February 2016

Ankit Gupta is currently in the final year of Bachelors of Technology in

Electronics and Communication Department of Bharati Vidyapeeth’s Gurashish Singh is currently in final year of Bachelors of Technology of
College of Engineering, New Delhi. He is a gold medalist from Delhi Public Electronics and Communication Department in Bharati Vidyapeeth’s
School, RK Puram. He has been awarded twice by the Lambda Eta chapter of College of Engineering. He is a student member of IEEE-HKN and has one
IEEE-HKN for academic excellence. The field of interest mainly includes published work in the field of Digital Image Processing. The research field of
subjects of electronics and communication discipline. interest broadly includes electronics and communication discipline.

401
ISSN: 2278 – 7798 All Rights Reserved © 2016 IJSETR