CHAPTER 5

5.1 Concept of CISC and RISC

5.2 PIC Microcontroller
5.3 Controller Design using selected MPU
CONTENTS
○ CISC and RISC
○ PIC Microcontroller
○ Controller Design

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❑ A complex instruction set computer
(CISC, pronounced like "sisk") is a
microprocessor instruction set
architecture (ISA) in which each
instruction can execute several low-
level operations, such as a load from
memory, an arithmetic operation, and a
memory store, all in a single instruction. 3
❑ The philosophy behind it is, that
hardware is always faster than software,
therefore one should make a powerful
instruction set, which provides
programmers with assembly instructions
to do a lot with short programs.
❑ So the primary goal of the Cisc is to
complete a task in few lines of assembly
instruction as possible. 4
❑ Memory in those days was expensive
✓ bigger program->more storage->more money
Hence needed to reduce the number of instructions
per program
❑ Number of instructions are reduced by having
multiple operations
within a single instruction
❑ Multiple operations lead to many different kinds of
instructions that
access memory
✓ In turn making instruction length variable and
fetch-decodeexecute
time unpredictable – making it more complex 5
✓ Thus hardware handles the complexity
➢ Use microcode
• Used a simplified microcode instruction set to control
the data path logic. This type of implementation is known
as a microprogrammed implementation.
➢ Build rich instruction sets
• Consequences of using a microprogrammed design is
that designers could build more functionality into each
instruction.
➢ Build high-level instruction sets
• The logical next step was to build instruction sets
which map directly from high-level languages 6
❑ Register to register, register to
memory, and memory to register
commands.
❑ Uses Multiple addressing modes .
❑ Variable length instructions where
the length often varies according
to the addressing mode
❑ Instructions which require
multiple clock cycles to execute.
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 Main memory

Memory (1,1) .. (6,4) = 24 locations

General purpose registers

Registers: A,B,C,D,E,F

Arithmetic Logical Unit

Execution unit : arithmetic ( + -* ÷)

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 ➢ Let's say we want to find
the product of two numbers
5,2
- one stored in location 2:3
and another stored in
location 5:2 - and then
store the product back in
the location 2:3.
➢ i.e.,
M(2,3)<- M(5,2)*M(2,3)

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For this particular task, a CISC
➢ processor would come prepared with a specific instruction (we'll call it
"MULT").
MULT A,B
When executed, this instruction
➢ loads the two values into separate registers,
➢ multiplies the operands in the execution unit, and then
➢ stores the product in the appropriate register.

Thus, the entire task of multiplying two numbers can be completed with
one instruction
➢ MULT is what is known as a "complex instruction."
➢ It operates directly on the computer's memory banks and does not
require the programmer to explicitly call any loading or storing
functions.
➢ It closely resembles a command in a higher level language,identical to

the C statement "a = a * b." 10

❑ RISC processors only use simple instructions that
can be executed within one clock cycle.
❑ The "MULT" command described above could be
divided into three separate commands:
LOAD A, 2:3 (LOAD, which moves data from
LOAD B, 5:2 the memory bank to a register)
PROD A, B ("PROD,"finds the product of two
operands )
STORE 2:3, A ("STORE,“ moves data from a
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register to the memory banks)
➢ Primary goal is to complete a
task in as few lines of assembly ➢ Primary goal is to speedup
as possible individual instruction
➢ Emphasis on hardware ➢ Emphasis on software
➢ Includes multi-clock ➢ Single-clock,
complex instructions reduced instruction only
➢ Memory-to-memory: ➢ Register to register:
"LOAD" and "STORE" "LOAD" and "STORE"
incorporated in instructions are independent instructions
➢ Difficult to apply pipelining. ➢ Easy to apply pipelining.
➢ Small code sizes, ➢ Low cycles per second,
high cycles per second large code sizes

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! The following equation is commonly used for cisc
expressing a computer's performance ability:

Risc
The CISC approach attempts to minimize the
number of instructions per program, sacrificing
the number of cycles per instruction.
RISC does the opposite, reducing the cycles per
instruction at the cost of the number of
instructions per program.
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❑ There is still considerable controversy
among experts about which architecture is
better.
Some say that RISC is cheaper and
faster and therefore the architecture of the
future.
Others note that by making the
hardware simpler, RISC puts a greater
burden on the software. Software needs to
become more complex. Software developers
need to write more lines for the same tasks. 14
INTRODUCTION

■ What is PIC?
- A family of Harvard architecture
microcontrollers made by Microchip Technology

- Derived from the PIC1650 originally

developed by General Instrument
Microelectronics Division.

- The name PIC was originally an acronym

for "Programmable Intelligent Computer". 15
INTRODUCTION

■ Why PIC is popular?

low cost ,wide availability with high clock speed
availability of low cost or free development tools
Only 37 instructions to remember
serial programming and re-programming with flash
memory capability
Its code is extremely efficient, allowing the PIC to
run with typically less program memory than its
larger competitors
PIC is very small and easy to implement for non-
complex problems and usually accompanies to the
microprocessors as an interface
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TWO DIFFERENT ARCHITECTURES

■ Harvard Architectures (newer arch.)

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TWO DIFFERENT ARCHITECTURES

■ Harvard Architectures ■ Von-Neumann Architecture

■ Used mostly in RISC CPUs ■ Used in: 80X86 (CISC PCs)

■ Separate program bus and data ■ Only one bus between CPU and
bus: can be of different widths memory
■ For example, PICs use: ■ RAM and program memory share
● Data memory (RAM): a small the same bus and the same
number of 8bit registers memory, and so must have the
● Program memory (ROM): 12bit, same bit width
14bit or 16bit wide (in EPROM, ■ Bottleneck: Getting instructions
FLASH, or ROM) interferes with accessing RAM

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RISC VS. CISC

■ Reduced Instruction Set ■ Complex Instruction Set

Computer (RISC) Computer (CISC)
● Used in: SPARC, ALPHA, Used in: 80X86, 8051,
Atmel AVR, etc. 68HC11, etc.
● Few instructions Many instructions
(usually < 50) (usually > 100)
● Only a few addressing Several addressing modes
modes Usually takes more than 1
● Executes 1 instruction in internal clock cycle (Tcyc) to
1 internal clock cycle execute
(Tcyc)

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FAMILY CORE ARCHITECTURE
DIFFERENCES

■ The PIC Family: Cores

12bit cores with 33 instructions: 12C50x, 16C5x

14bit cores with 35 instructions: 12C67x,16Cxxx

16bit cores with 58 instructions: 17C4x,17C7xx

‘Enhanced’ 16bit cores with 77 instructions: 18Cxxx

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THE PIC FAMILY: SPEED
■ Can use crystals, clock oscillators, or even an RC
circuit.
■ Some PICs have a built in 4MHz RC clock, Not very
accurate, but requires no external components!
■ Instruction speed = 1/4 clock speed (Tcyc = 4 * Tclk)
■ All PICs can be run from DC to their maximum
specified speed:
12C50x 4MHz

12C67x 10MHz
16Cxxx 20MHz
17C4x / 17C7xxx 33MHz 21

18Cxxx 40MHz
CLOCK AND INSTRUCTION CYCLES
■ Instruction Clock
● Clock from the oscillator enters a microcontroller via OSC1 pin where internal
circuit of a microcontroller divides the clock into four even clocks Q1, Q2, Q3, and
Q4 which do not overlap.
● These four clocks make up one instruction cycle (also called machine cycle)
during which one instruction is executed.
● Execution of instruction starts by calling an instruction that is next in string.
● Instruction is called from program memory on every Q1 and is written in
instruction register on Q4.
● Decoding and execution of instruction are done between the next Q1 and Q4
cycles. On the following diagram we can see the relationship between instruction
cycle and clock of the oscillator (OSC1) as well as that of internal clocks Q1-Q4.
● Program counter (PC) holds information about the address of the next
instruction.

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PIPELINING IN PIC
■ Instruction Pipeline Flow

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THE PIC FAMILY: PROGRAM MEMORY
■ Technology: EPROM, FLASH, or ROM
■ It varies in size from one chip to another.
- examples:
12C508 512 12bit
instructions
16C711 (1k) 1024 14bit
instructions
16F877 (8k) 8192 14bit
instructions
17C766 (16k) 16384 16bit 24
instructions
THE PIC FAMILY: DATA MEMORY
■ PICs use general purpose “File registers” for
RAM (each register is 8bits for all PICs)
- examples:

12C508 25B RAM

16C71C 36B RAM

16F877 368B RAM + 256B of
nonvolatile EEPROM

17C766 902B RAM

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PIC PROGRAMMING PROCEDURE
■ For example: in programming an embedded PIC featuring
electronically erasable programmable read-only memory
(EEPROM). The essential steps are:

● Step 1: On a PC, type the program, successfully compile it and

then generate the HEX file.

● Step 2: Using a PIC device programmer, upload the HEX file

into the PIC. This step is often called "burning".

● Step 3: Insert your PIC into your circuit, power up and verify
the program works as expected. This step is often called
"dropping" the chip. If it isn't, you must go to Step 1 and
debug your program and repeat burning and dropping.
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PIC16F877A FEATURES
High Performance RISC CPU:
■ Only 35 single word instructions to learn

■ All single cycle instructions except for

program branches, which are two-cycle

■ Operating speed: DC - 20 MHz clock input

DC - 200 ns instruction cycle

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REFERENCES AND FURTHER
READINGS
■ http://www.microchip.com

■ http://en.wikipedia.org/wiki/
PIC_microcontroller

■ 16F87x Data Sheet

Thank You
■ Mid Range Manual For Your
Attendance.
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