80286 Basic Features:

(i) The 80286 microprocessor is an advanced version of the 8086 microprocessor that is designed
for multi user and multitasking environments.
(ii) The 80286 addresses 16 M Byte of physical memory and 1G Bytes of virtual memory by
using its memory management system.
(iii) The 80286 is basically an 8086 that is optimized to execute instructions in fewer clocking
periods than the 8086.
(iv) Like the 80186, the 80286 doesn’t incorporate internal peripherals; instead it contains a
memory management unit (MMU).
(v) The 80286 operates in both the real and protected modes.
(vi) In the real mode, the 80286 addresses a 1MByte memory address space and is virtually
identical to 8086.
(vii) In the protected mode, the 80286 addresses a 16MBer memory space The clock is provided
by the 82288 clock generator, and the system control signals are provided by the 82288 system
bus controller.

(viii) The 80286 contains the same instructions except for a handful of additional instructions
that control the memory management.

architecture of the 80286

  The 80286 was designed for multi-user systems with multitasking
applications, including communications and real-time process control.
 These were organized into a pipeline, significantly increasing performance.
 It was produced in a 68-pin package including PLCC (Plastic Leaded
Chip Carrier), LCC (Leadless chip carrier) and PGA (Pin Grid Array)
packages.
 The Intel 80286 had a 24-bit address bus and was able to address up
to 16 MB of RAM, compared to 1 MB for its predecessor.
80286 Architecture contains 4 separate processing units.
1. Bus Unit (BU)
2. Instruction Unit (IU)
3. Address Unit (AU)
4. Execution Unit (EU)
Bus Unit (BU):
It has address latches, data transceivers, bus interface and circuitry, instruction
pre-fetcher, processor extension interface and 6 byte instruction queue.
Functions :
- To perform all memory and I/O read and write.
- To pre-fetch the instruction bytes.
- To control the transfer of data to and from processor extension devices like
 80287 math co- processor.
- Whenever BU is not using the buses for the operation, it pre-fetches the
instruction bytes and put them is a 6 byte pre-fetch queue.
Instruction Unit (IU):
It has 3 decoded instruction queue and
instruction decoder. Functions :
- It fully decodes up to three prefetched instructions and holds them in a queue.
- So that EU can access them.
- It helps the processor to speed up, as pipelining of instruction is done.
Execution Unit (EU):
It includes ALU, registers and the Control unit. Registers are general purpose,
index, pointer, flag register and 16 –bit Machine Status Word (MSW).
Functions :
- To sequentially execute the instructions received from the instruction unit.
- ALU result is either stored in register bank or sent over the data bus.
Address Unit (AU):
It consists of segment registers, offset address and a physical
address adder. Functions :
- Compute the physical address that will be sent out to the memory or I/O by BU.
- 80286 operate in two different modes
1. real address mode
2. Protected virtual address mode.
- When used in Real address mode, AU computes the address with segment
base and offset like 8086. Segment register are CS, DS, ES and SS hold base
address. IP, BP, SI, DI , SP hold offset.
- Maximum physical space allowed in this mode is 1MB.
- When 80286 operate in protected mode, the address unit acts as MMU.
- All 24 address lines used and can access up to 16MB of physical memory.
- If descriptor table scheme is used it can address up to 1GB of virtual memory.

2. Explain Register Organization of 80286

1. Eight 16-bit general purpose registers (AX, BX, CX, DX, SP, BP, SI, DI)
2. Four 16-bit segment registers (CS, SS, DS, ES)
3. 16-bit Instruction Pointer (IP)
4. 16-bit Flag Register Plus
5. one new 16-bit machine status word (MSW) register
80286 Flag Register

- Flag register is of 32 –bit, 15th bit undefined/reserved.

- System flags: reflect the current status of machine.
i. IOPL – I/O Privilege Level flag: 2 –bits are used in protected mode. It
holds the privilege level from 0 to 3. ‘0’ assigns to highest privilege
whereas ‘3’ assigns to lower privilege level.
ii. NT: Nested Task flag: It is used in protected mode. Bit is set when one
task invokes another task.
Machine Status Word (MSW) Register

Protected Mode Enable

PE=1; Places 80286 in protected mode
PE=0; It can be only cleared by resetting CPU
Task Switch
TS is automatically set whenever a task switch operation is performed.
 Monitor processor extension
If set, this flag allows WAIT instruction to generate a processor extension not present
exception

EMulate processor extension flag

If set, The EMulate coprocessor bit is set to cause all coprocessor opcodes to
generate a Coprocessor Not Available fault.

Instructions used to load and store MSW:

1. LMSW instruction (Load Machine Status Word)
2. SMSW instruction (Store Machine Status Word)
3. Differentiate between the real mode and protected mode
of an 80286 microprocessor.
Real Mode
 Address Unit computes the address with segment base and offset like 8086.
 Maximum physical space allowed in this mode is 1MB.
 When 80286 get reset, it always starts execution in real mode.
Task carried out in Real Mode
 Initializes IP and other registers of 80286
 Initializes the peripheral
 Enables interrupts
 Set up the descriptor table
 Prepares for entering in PVAM(Protected Virtual Address Mode)

Protected Virtual Address Mode (PVAM)

 80286 is the 1st processor to support the concept of Virtual
memory and Memory management.
 Here, the address unit acts as MMU.
 All 24 address lines are used and can access up to 16MB of physical memory.
 If descriptor table scheme is used it can address up to 1GB of virtual memory.
Task carried out in PVAM
 The complete virtual memory is mapped on to the 16Mbyte physical memory.
 If a program larger than 16Mbyte is stored on the hard disk and is
to be executed by swapping sequentially as per sequence of
execution.
 The huge programs are divided in smaller segments or pages
arranged in appropriate sequence.
4. Explain features of 80486
 The 32-bit 80486 is the next evolutionary step up from the 80386.
 One of the most obvious feature included in 80486 is a built-in math
coprocessor. This coprocessor is essentially the same as the 80387
processor used with a 80386, but being integrated on the chip allows it
to execute math instructions about three times as fast as a 80386/387
combination.
 80486 is an 8Kbyte code and data cache.
 To make room for the additional signals, the 80486 is packaged in a 168
pin, pin grid array package instead of the 132 pin PGA used for the
80386.
 Operates on 25MHz, 33 MHz, 50 MHz, 60 MHz, 66 MHz or 100MHz.
 It consists of parity generator/checker unit in order to implement parity
detection and generation for memory reads and writes.
 Supports burst memory reads and writes to implement fast cache fills.
 Three mode of operation: real, protected and virtual 8086 mode.
 The 80486 microprocessor is a highly integrated device, containing well
over 1.2 million transistors.
New feature found in the 80486 are as follows:
1. BIST (built-in self-test) that tests the microprocessor
2. 8KB Code and data cache
3. On-chip FPU(Floating Point Unit)
5. Features of Pentium Processor
It consists of all the features that 80486 has. The additional enhancements that
Pentium provides are:
1. Wider data bus width :
 It has 64 bit data bus and 32 bit address bus.
 It allows 8 byte of data info to be transferred to and from memory.
 Bus cycle pipelining has been added to allow two bus cycles to be in progress
simultaneously.
2. Improved Cache Structure:
 8KB dedicated instruction cache which gives instruction to its execution units
and floating point unit via dual instruction pipeline.
 Cache is organized in a 2 way set associate cache with 32 byte line (256 lines).
 8KB data cache which gives data to its execution unit.
 This allows 32 byte transfer from cache to pre-fetch buffer which is of 64 bytes.
3. Two parallel integer execution unit :
 It allows the execution of two instructions to be executed simultaneously in a
single processor clock.
4. Faster floating point unit :
 The floating point unit has been completely redesigned over 80486.
 Faster algorithms provide up to ten times speed – up for common
 operations including add, multiply etc.
5. Branch prediction logic:
 The Pentium uses tech called branch prediction.
 To implement this Pentium has two pre-fetch buffers, one to pre-fetch code
in linear fashion, and one that pre-fetches code according to the Branch
Target Buffer (BTB).
 Therefore, needed code is almost pre-fetched before it is required for execution.
6. Data Integrity and Error Detection:
 The Pentium have added significant data integrity and error detection capability.
 Data parity checking is still byte-by-byte basis.
 Address parity checking has also been added.
7. Functional Redundancy Checking: (provide maximum error detection)
 Two or more Pentium Processor can participate in functional redundancy
checking.
 One processor (the master) fetching the instruction and executes the
instruction in normal fashion.
 Other processor (the checker) (connected directly to the master processor’s
buses)verify correctness of master processor.
 Checker executes the instruction same as the master but doesn’t drive the buses.
 Checker samples master’s output and compares the values with the internal
computed values. An error signal is asserted in case if mismatch occurs.
8. Super Scalar Architecture :
 Processor is capable of parallel instruction execution of multiple instructions
are known as superscalar processors.
 Pentium is capable in some cases of executing two integer of two floating
point instruction simultaneously and thus support superscalar architecture.

Pentium Architecture
The term ''Pentium processor'' refers to a family of microprocessors that share a
common architecture and instruction set. The first Pentium processors were
introduced in 1993. It runs at a clock frequency of either 60 or 66 MHz and has 3.1
million transistors. Some of the features of Pentium architecture are
 Complex Instruction Set Computer (CISC) architecture with Reduced
Instruction Set Computer (RISC) performance.
 64-Bit Bus
 Upward code compatibility.
 Pentium processor uses Superscalar architecture and hence can issue
multiple instructions per cycle.
 Multiple Instruction Issue (MII) capability.
 Pentium processor executes instructions in five stages. This staging, or
pipelining, allows the processor to overlap multiple instructions so that it
takes less time to execute two instructions in a row.
 The Pentium processor fetches the branch target instruction before it executes the
branch instru
 The Pentium processor has two separate 8-kilobyte (KB) caches on chip, one for
instructions and for data. It allows the Pentium processor to fetch data and
instructions from the cache simultaneo
 When data is modified, only the data in the cache is changed. Memory data is
changed only when Pentium processor replaces the modified data in the cache
with a different set of data

 The Pentium processor has been optimized to run critical instructions in fewer
clock cycles than 80486 processor.