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    C60 - Fujitsu Digital To Analog Converter LEIA 55-65 GSa/s 8-Bit DAC

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    Fujitsu Semiconductor Europe
    This document describes Fujitsu's 55-65 GSa/s 8-bit CMOS DAC which targets highly integrated 100/200G optical transceiver devices. The high sample rate and CMOS technology allows for a compact, low power solution. Fujitsu's DAC integration mitigates the need for a separate modulation-encoding multiplexor, extending power, footprint, flexibility and reliability advantages. Development kits including an evaluation board, test chips, and software will be available to evaluate the DAC IP.

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    C60 - Fujitsu Digital To Analog Converter LEIA 55-65 GSa/s 8-Bit DAC

    Uploaded by

    Fujitsu Semiconductor Europe
    393 views2 pages
    This document describes Fujitsu's 55-65 GSa/s 8-bit CMOS DAC which targets highly integrated 100/200G optical transceiver devices. The high sample rate and CMOS technology allows for a compact, low power solution. Fujitsu's DAC integration mitigates the need for a separate modulation-encoding multiplexor, extending power, footprint, flexibility and reliability advantages. Development kits including an evaluation board, test chips, and software will be available to evaluate the DAC IP.

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    C60 - Fujitsu Digital to Analog Converter LEIA 55-65 GSa/s 8-bit DAC

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    This document describes Fujitsu's 55-65 GSa/s 8-bit CMOS DAC which targets highly integrated 100/200G optical transceiver devices. The high sample rate and CMOS technology allows for a compact, low power solution. Fujitsu's DAC integration mitigates the need for a separate modulation-encoding multiplexor, extending power, footprint, flexibility and reliability advantages. Development kits including an evaluation board, test chips, and software will be available to evaluate the DAC IP.

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    Attribution Non-Commercial (BY-NC)
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    393 views2 pages

    C60 - Fujitsu Digital To Analog Converter LEIA 55-65 GSa/s 8-Bit DAC

    Uploaded by

    Fujitsu Semiconductor Europe
    This document describes Fujitsu's 55-65 GSa/s 8-bit CMOS DAC which targets highly integrated 100/200G optical transceiver devices. The high sample rate and CMOS technology allows for a compact, low power solution. Fujitsu's DAC integration mitigates the need for a separate modulation-encoding multiplexor, extending power, footprint, flexibility and reliability advantages. Development kits including an evaluation board, test chips, and software will be available to evaluate the DAC IP.

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    Attribution Non-Commercial (BY-NC)
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    of 2

    Fujitsu Semiconductor Europe Factsheet LEIA 55 65 GSa/s 8-bit DAC

    Digital to Analog Converter

    AVDNEGDAC

    Fujitsus data converter technology has brought forward the enablement of real 100G transport networks. This technological progress continues with Fujitsus 55-65 GSa/s 8-bit CMOS DAC. Targeting highly integrated 100/200G optical transceiver devices the challenge is to enable greater functionality whilst staying within a stringent power budget. This is achieved largely due to the high sample rate of the DAC coupled with the IPs availability in CMOS technology which allows for a compact low power solution. Fujitsus existing CHAIS ADC IP macros in 65nm and 40nm have provided the opportunity to combine features such as soft decision FEC with high speed ADCs to enable feature-rich receiver designs. This reduces the chip count, in turn reducing power consumption and total footprint while increasing reliability and exibility. These benets are further enhanced when the DACs are included due to the Transmit features which can be realised using the

    4-channel DAC macro with its integrated PLL. This DAC integration mitigates the requirement for a separate modulation-encoding multiplexor thus extending the power consumption, footprint, exibility and reliability advantages.
    HIDAT[1023:0]

    AVDDAC18

    AVDNEG

    AVDDAC

    AVD18

    DAC DIGITAL

    AVDRF

    VSS VDD

    AVD

    I DAC

    HIOP HION HQOP HQON

    DAC Macro Features


    HQDAT[1023:0]

    Q DAC

    Fujitsu 40nm Technology Resolution : 8-Bit 4 Channels (2 x IQ pairs) Sampling Rate : 55 65 GS/s Power Supply : 1.8V, 0.9V, -0.9V Power Consumption : 0.75W/ch ENOB: 6.5 (-6dBFS sinewave at ~8GHz) Output current: 6mA > 13GHz -3dB Output Bandwidth 2s Complement Data Format Digital Input: 128 x 8-bit data words (1024 bit) @ FS/128 per DAC FS/128 output clock to core 2GHz Input Reference Clock Internal offset cancellation at start-up Designed for ip-chip packages

    XRST EN SPI_OUT SPI_IN XSS RDY CLKO SPI_CLK

    CAPLF CAPAAC

    PLL 4

    REFCLKP REFCLKN BGAP RREF

    DAC DIGITAL

    VIDAT[1023:0]

    I DAC

    VIOP VION VQOP VQON

    VQDAT[1023:0]

    Q DAC

    Full DAC macro block diagram

    Page 1 of 2

    Factsheet Fujitsu LEIA55 65 GSa/s 8-bit Digital to Analog Converter

    Applications

    40G/100/200G Communications Systems Test Equipment

    Four DAC Channels 8-bit x 256K samples memory space per DAC channel SPI Interface

    The kit includes everything needed to minimise the time taken to get started. A USB interface is provided on the evaluation board for easy connection to a PC. Part Numbers

    Test Chip (Leia) Test chips for the 55-65 GSa/s 8-bit DAC (codenamed Leia) will be available providing all 4 channels of the 40nm CMOS DAC macro. Each of these channels has RAM at its input which is used to store 256K X 8 bit samples to the DAC channel. This RAM can be loaded with user dened waveform data to send through the DAC channels. Control / programming functions and RAM read/write operations are all performed via an SPI interface. There are several storage modes available which enable control of the RAMS from external triggers.

    Development Kits (Leia-DK) A development kit to accompany the Leia test chip will be available for the evaluation of the DAC IP (codenamed Leia-DK). Each kit includes: Evaluation board with choice of test chip being solder mounted or with socket for easy replacement Mains power supply and voltage regulator board Interconnect leads/boards Windows GUI Software Access to DAC outputs via SMPM connectors On-board programmable clock distribution circuitry

    LEIA-ES DAC macro test chips LEIA-DK This evaluation board is supplied with a solder-mounted LEIA-ES test chip. LEIA-DK-SOCKET This evaluation board is supplied with low inductance sockets tted This allows easy replacement or swapping of LEIA-ES test chips. The LEIA-ES test chips are sold separately.

    All company and product trade marks and registered trade marks used throughout this literature are acknowledged as the property of their respective owners.

    web.comms.fseu@de.fujitsu.com http://emea.fujitsu.com/semiconductor
    FSEU-C60-29MAR2012

    Page 2 of 2

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