Conclusion: Preliminary experiments with an externallymodulated injection-locked diode array show no degradation

Acknowledgments: It is a pleasure to acknowledge stimulating conversations with D. M. Boroson, E. S. Kintzer, and E. A.

to diagnostics

data out

Fig. 3 Schematic diagram of heterodyne experimental apparatus

-r
. . . .
I

Swanson of MIT Lincoln Laboratory. This work was sponsored by the Department of the Air Force.
J. C. LIVAS
5th April 1991

B. ALEXANDER R. S . BONDURANT J. E. KAUFMANN M. L. STEVENS

Lincoln Laboratory Massachusetts Institute of Technology 224 Wood Street Lexington, Massachusetts 02173-9108, USA

m
0 -

..............................

References
GOLDBERG, L., TAYUJR, H.F., WELLER, J . F., and SCIFRES, D. R.: Injection locking of coupled-stripe diode laser arrays, Appl. Phys. Lett., 1985,46, pp. 236238 2 LUCENTE, M., KINZTEER, E. S., ALBXANDER, S. B., FUJIMOTO, J. G., and CHAN, v. w . s.: Coherent optical communication with injectionlocked high-power semiconductor array, Electron. Lett., 1989, 25, pp. 1112-1113 3 ABBAS, G. L., YANG, s., CHAN, v. w. s., and FUJIMOTO, J. G.: Injection behavior and modeling of IoOmW broad area diode lasers, IEEE J . Quantum Electron., 1988, QE-24, pp. W-617

.............................
...........................

. . . . . .

IO 12
1

I
. I

100

e(

valent p h o t o n / blt

Fig. 4 Heterodyne results __ zero linewidth DPSK

~ _ _ 15MHzlinewidth theory _
2
~

1 length PRS:

HIGH-DRIVE CMOS BUFFER FOR LARGE CAPACITIVE LOADS

Square wave:
0 baseline 0 array

+ array

0 baseline

1Gbit/s data rate 15MHz IF linewidth n modulation depth in BER performance when compared to the performance of the same system with the array optically bypassed. The comparison was performed with a selfhomodyne configuation which eliminated the effects of laser linewidth and with a heterodyne configuration which was a more realistic approximation of a coherent communications link. Some pattern-dependent behaviour in the modulation/demodulation electronics is evident, independent of the array.
1044

sented. The objective of the design is a high-power, areaeffcient buffer to be used in very large scale analogue applications. The buffer can deliver a slew rate of 1.2V/ps to capacitive loads in excess of 5000pF. It has a total harmonic distortion of less than 3% at 20kHz. At stand by, it consumes only 125pA (0,625mW). The buffer occupies 100mils of die area in a 3pm technology.
Introduction: The subject of opamp design using CMOS tech-

nology has been under study for some time. The design methodology and tradeoffs in cases with low, predetermined capacitive loads are well known. This includes amplifiers
ELECTRONICS L E P E R S

6rh June 1991 Vol. 2 7 No. 12

used in switched capacitor filtering and a variety of other applications where the amplifier has only to drive another circuit within the interior of the chip. Output buffers, however, should be able to handle large and sometimes variable capacitive loads from output pads, leads, IC pins, PCB wiring, and other loading at the output. Some examples of CMOS power amplifier design have appeared in the literature during the past few In addition to these requirements, if the buffer is to be used in a very large scale application, it should occupy a small portion of the chip. The application leading to this design is a multilayered analogue neural network where the number of output pins is relatively large. This application emphasises the need for buffers that consume a small portion of chip area and power. The available designs, with area consumptions of up to thousands of mils' are not suitable for this purpose. In this Letter, a high-drive buffer for large capacitive loads is presented. The buffer operates on a single 5V supply and occupies only 100mils' of die area.
Circuit description: The schematic diagram of the circuit is

Dominant poles and zeros of the circuit are given in Table 1 for load conditions of

R , = lOkR
R, = lOkR

C, = 500pF C, = 5000pF

In both cases, the moduli of the closest pole (zero) to those in the Table are at least 5 (3) octaves higher. With the 5000pF load, the complex conjugate poles have a quality factor of
5

> O

p(--I
2 1

O given in Fig. 1. The transistors Ml-M5 and M9-Ml3 form

i
time,

ps

EE

O
= 5000pF

Fig. 2 Pulse response o buffer with capacitive load o C f f ,

5
4

.3
ut

a2
1

M3 1
Fig. 1 Schematic diagram o buffer f

M5 1

4
VCC

2
Vin

4
=5

5
M

1565111

.a.,

Fig. 3 Transfer characteristics with R ,

two complementary differential stages. The inputs of these stages are connected in parallel. Each of them drives one half of the output common source push-pull stage. By using two input stages in parallel, the intermediate level-shifting stage, normally needed to feed a push-pull output stage, is eliminated. The drawback of this approach is that it slightly increases the harmonic distortion. This increase in distortion is tolerated for our applications; the alternative is to include compensation capacitors, which will significantly increase buffer area. Transistors MI4 and M15 are connected as resistors. Their function is to decrease the impedance at the gates of output transistors M16 and M17 and act as frequency compensation capacitors.
Performance analysis: The pulse response of the buffer with a

0.003 ,

Fig. 4 Normalised harmonics of output at ZOkHz with Vin = 2 V peak

10
m O

5000pF capacitive load is shown in Fig. 2. Slew rates of 1.2 V/ p and 0 5 % settling time of 3ps have been achieved with this load. Fig. 3 shows the transfer characteristic of the buffer. Output voltage span is 94% of the supply range with a 5 kR load and rail to rail for R, z IOkR. Although the input circuitry is design in two half parts, total harmonic distortion is less than 3% at 20 kHz. Normalised harmonics of the input at this frequency for a 2 V peak to peak signal are given in Fig. 4; the quiescent current is only 125pA. The frequency response of the buffer is shown in Fig. 5. Table 1 POLE-ZERO CONFIGURATIONS Poles Load
C, = 500pF R , = 500pF C, = 5000pF R , = lOkR

6-10 U 2 -20
C

$-30 E -40
-50

io1

lo3 105 frequency, Hz

lo&
= 5,wO pF,

Fig. 5 Frequency response o buffer with C, f

R , = IO M

Zeros
Imaginary Real -3.369 x lo6 -1.467 x I' O -1.758 x lo8 -3,369 x lo6 -1.467 x IO8 -1.758 x 1 0 ' Imaginary

Real -1.344 x lo6 -1.344 x lo6 -3.369 x lo6 -1.675 x lo6 -1.675 x lo6 -3.370 x lo6

1.991 x lo7 -1.991 x lo7

0
6.123 x lo6 -6.123 x lo6

0 0 0
0 0 0

ELECTRONICS LETTERS 6th June 1991 Vol. 27 No. 12

1045

Q = 1.75, and with C , = 500pF, Q = 7.38. The circuit operates acceptably over an order of magnitude variation of the capacitive load.
Summary: A CMOS buffer suitable for driving very large capacitive loads has been presented. The buffer is capable of driving 5000pF loads with an output slew rate of 1.2V/p. The quiescent current is 125pA, and the THD is 3% at 20 kHz. The buffer occupies 100 mils of die area and works acceptably over an order of magnitude variation in capacitive load.

A. NOSRATINIA M. AHMADI G. A. JULLIEN Department o Electrical Engineering f Uniuersity o Windsor f Windsor, Ontario N9B 3P4, Canada

10th April 1991

M. SHRIDHAR
Department o Electrical Engineering f University o Michigan f Dearborn, Michigan 48128, U S A

References
1
GRAY, P R., .

and MEYER, R.

G.:

MOS operational amplifier desip-

a tutorial overview, IEEE J. Solid-state Circuits, 1982, SC-17, pp. 969-982 w.: A high dynamic range CMOS op 2 STEYAERT, M., and SAN, amp with low-distortion output structure, lEEE J . Solid-state Circuits, 1987, SC-22, pp. 1204-1207 3 FISHER,I. A., and KOCH, R.: A highly linear CMOS buffer amplifier, IEEE J. Solid-state Circuits, 1987, SC-22, pp. 33&334 4 BABANEZHAD, 1. N.: rail-to-rail CMOS op amp, IEEE J. SolidA State Circuits, 1988,23, pp. 1414-1417 5 NAGARAI, K.: Large-swing CMOS buffer amplifier, IEEE J. SolidState Circuits, 1989, SC-W pp. 181-183 F N. L., et al.: A CMOS large-swing lowdistortion . 6 OPT EWE, three-stageclass AB power amplifier,lEEE J . Solid-state Circuits, 1990, SC-25, pp. 265-273 A 7 PARODEN, M. D.,and DEGRAUWF, M. G.: rail-to-rail input/output CMOS amplifier, IEEE J. Solid-state Circuits, 1990, SC-25, pp.
501-504

CALLEWART, L. G. A.,

and SANSBN, w. M. c.: Class AB CMOS amplifiers with high eficiency,IEEE J. Solid-State Circuits, 1990, SC-25, pp. 684-691

ULTRATHIN STACKED Si,N,/SiO, GATE DIELECTRICS PREPARED BY RAPID THERMAL PROCESSING

rapid thermal processing (RTP) have been studied as a possible substitute of pure thermal SiO, for gate dielectric applications. The top nitride thickness has been scaled down to 30A such that charge trapping can be minimised. Results show that the stacked dielectrics exhibit comparable charge trapping and leakage current as compared with pure thermal SiO, of similar thickness, but have far fewer medium- and low-field breakdown In this study, single-wafer RTP was used exclusively for gate dielectrics formation. The bottom oxide was prepared hy RTO and the top nitride was deposited by RTP-CVD. These techniques allow high-temperature processing without an excessive thermal budget. The starting materials were lightly boron-doped Si (100) substrates. The bottom oxide and the control oxide were both prepared by RTO in 0, at 1050C. The top nitride of the stacked N O dielectrics was deposited by using SiH, and NH, (flow rate ratio 1 : 4 )diluted in N,. The deposition pressure 0 was 1 torr and the temperature was 850C. The nitride was deposited by an RTP-CVD system that uses tungsten-halogen lamps as the heat source. The nominal bottom oxide thickness was 40A and the top nitride thickness was 30A. No annealing or reoxidation was performed after top nitride formation. The dielectric thicknesses were all oxide-equivalent and were derived by measuring the high-frequency (1 MHz) capacitances of MOS capacitors in the accumulation regime, assuming a dielectric constant of 3.9. LP-CVD polysilicon was deposited to a thickness of 4000A immediately after dielectric formation, followed by POCI, doping, photolithography and RIE. A forming gas anneal at 450C concluded the device fabrication. The capacitor I/V characteristics of both the control oxide and the stacked layers are plotted in Fig. 1. Stacked NO layers, especially reoxidised nitride/oxide layers (ONO) are known to exhibit lower leakage current as compared with pure oxide at high fields? Several factors contribute to the current reduction. The top and/or bottom oxides of stacked O N O and NO layers force electron conduction through the nitride, in which the electron mobility is now due to the presence of deep electron traps., Space charge at the nitride/ oxide interface also reduces the electric fields at the carrier-injection electrodes, which further decreases the leakage current? In Fig. 1, however, the leakage current of the control oxide and the stacked nitride/oxide exhibits comparable leakage at low fields and the stacked layer shows even slightly higher current at high fields. The dark current in CVD Si,N, has been found to increase with decreasing thickness at constant electric field~..~The increase in conductivity has been attributed to diminished electron trapping in thin nitride films or to thickness f l u ~ t u a t i o n . ~ . ~ case, the top nitride was In our very thin and consequently highly conductive. Such a thin top nitride cannot reduce leakage currents by charge trapping and is not resistant even to a reoxidation in dry oxygen at 1050C for 30s. As will be shown later, the advantage of adopting this thin top nitride is to reduce defect density while maintaining low charge trapping rates rather than reduce leakage current.

Ultrathin (58 A equivalent oxide thickness) stacked Si,NJSiO, (NO) films with the bottom oxide prepared by rapid thermal oxidation (RTO) in 0, and the top nitride deposited by rapid thermal processing chemical vapour deposition (RP-CVD) were fabricated and studied. Results show that the charge trapping and leakage current of the stacked films are comparable to those of pure SiO, and lowfield breakdown events are significantly reduced. By scaling down the top nitride thickness the commonly observed flathand voltage instability of MNOS devices was minimised, hut the lowdefect property was still preserved. Stacked nitride/oxide (NO) films have received much attention recently due to their low defect density, low leakage current, diffusion barrier property, and excellent long-term reliabilit^.'-^ However, efforts have been focused on using these dielectrics as storage dielectrics on either Si or polysilicon electrodes. The flatband voltage instability resulting from charge trapping in the nitride layer or at the nitride/oxide interface. has limited the application of these films to memory element^.^,^,^ In this work, stacked NO films prepared by
1046

c
.
0

..
2
4 6

/
8

controi oxlde

10 12 14 - E , MVIcm

16

18

20

Fig. 1 Current density (J) against electric field ( E ) of pure SiO, and stacked N O layers Electric field is calculated in terms of oxide-equivalent thickness

ELECTRONICS LETERS

6th June 1991

Vol. 27 No. 12