Elkadig Slide
Elkadig Slide
Textbooks
DeMassa and Ciccone, Digital Integrated Circuits, John Wiley & Sons. Taub and Schilling, Digital Integrated Electronics, McGraw-Hill
Contents
Basic Properties of Digital Integrated Circuits Diode Digital Circuits BJT Digital Circuits
Ebers & Moll equations Transistor modelling State of transistor in a circuit
Resistor-Transistor Logic (RTL) Diode-Transistor Logic (DTL) Transistor-Transistor Logic (TTL) Schottky Transistor Transistor Logic (STTL) Different TTL Gates Emitter-Coupled Logic (ECL) MOS Digital Circuits NMOS Gates CMOS Gates
Propagation Delays
Power dissipation
PD = PDISS(avg) x tP(avg)
Diodes
Shockleys Eq
I D = IS (e VD /VT 1)
IV Characteristics
SPICE model
ID = IS (e VD /VT 1)
Clamping Diodes
10
BJT Transistors
NPN BJT
Reciprocity theorem
IS = F I ES = R I CS
transport saturation current
(a) Cutoff
I C = F I B
R =
1R
(c) Saturation
IV Characteristics
Modes of Operation
Examples
F = 65 IC, IB = ?
INVERTER
VIL = VBE ( FA )
FR C
RB
NAND
NOR
RTL Fan-out
Maximum fan-out?
I N = OUT I IN
I OUT =
VCC VOUT RC
I IN =
VOUT = VIH
VCC VCE (SAT )
FR C
RB
10
RTL NONINVERTER
11
AND
OR
12
I OUT = I EP
I N = OH I IH
I IN =
FR C
RB
DTL Fan-out
Cascaded DTL
I OL = I C,O (SAT ) I RC
I B,O = I E ,L I RD
I N = OL I IL
I RC =
I RD =
Path 2
I E ,L I IL =
VBE ,O (SAT ) RD
R B
RB
Path 3
Power Dissipation
Example: Calculate the average power dissipation for the above example?
VIL = VBE,S(FA) VCE,I(SAT)) VIH = VBE,O(SAT) + VBE,S(SAT) VCE,I(SAT) VIB = VBE,O(FA) + VBE,S(FA) VCE,I(SAT)
TTL Fan-out
Cascaded TTL
Path 1
I IL = VCC VBE ,I (SAT ) VCE ,O (SAT ) RB
I N = OL I IL
Path 2
Example (TTL Fan-out) Example: Calculate the TTL fan-out for F = 25, = 0.85 and R = 0.1
IRB(OL) = 675 A IRC(OL) = 2.5 mA IIL= IRB(OH) = 1 mA IOL= 51.9 mA
I N = OL = 51 I IL
Example (Power Dissipation) Example: Calculate the average power dissipation for the above example?
PCC(avg) = 10.4 mW
10
Open-Collector TTL
Mostly used in data busses where multiple gate outputs must be ANDed.
This can be accomplished by using a single pull-up resistor with open-collector TTL gates This type of connection is referred to as wired-AND.
LTTL Example
Compare the power dissipation of the LTTL and TTL gates. IRB(OL) = 67.5 A IRC(OL) = 200 A TTL vs LTTL power dissipation ratio = 10.4 / 0.919 = 11.3 IRB(OH) = 100 A PCC(avg) = 919 W
Example (SBJT)
Example: Draw the VTC graph of the SBJT inverter shown below
STTL Fan-out
Cascaded STTL
Path 1
I IL = VCC VBE ,I ( HARD) VCE ,O ( HARD) RB
RC I N = OL I B,O ( HARD) = I E ,S( HARD) I C,D ( HARD) Path 2, 3 I B,S = I C,I ( RS) = ISBD I IL V V
I C ,D ( HARD ) =
BE ,O ( HARD ) CE , D ( HARD )
R CD
ISBD =
Example (TTL Fan-out) Example: Calculate the STTL maximum fan-out for F = 49.
IRB(OL) = 1.11 mA IRC(OL) = 4.11 mA IRCD(OL) = 1.20 mA IE,S(OL) = 4.22 mA IR,O(OL) = 4.02 mA IOL= 197 mA IIL= IRB(OH) = 1.32 mA
I N = OL = 149 I IL
Example (Power Dissipation) Example: Calculate the average power dissipation for the above example?
IE,P(OL) = 0.182 mA IE,P(OH) = 1.3 mA PCC(avg) = 20.05 mW
Accomplished by 1. Increasing the resistance value 2. Diode input section 3. Pull-down enhancements
LSTTL Example
Compare the power dissipation of the LSTTL and STTL gates. IRB(OL) = 170 A IRC(OL) = 463 A STTL vs LSTTL power dissipation ratio = 20.05 / 2.11 = 9.5 IRB(OH) = 210 A PCC(avg) = 2.11 mW
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ALSTTL
ALSTTL VTC
VOH = VCC VBE,P(FA) VOL = VCE,O(HARD) VIL = VBE,O(FA) + VEB,IPA(FA) VIH = VBE,O(HARD) + VBE,S(HARD) + VBE,SB(HARD) VBE,IPA(FA)
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ALSTTL VTC
FAST
12
FAST VTC
VOH = VCC VBE,P(FA) VOL = VCE,O(HARD) VIL = VBE,O(FA) + VBE,S(FA) + VBE,SB(FA) VD,IA(ON) VIH = VBE,O(HARD) + VBE,S(HARD) + VBE,SB(HARD) VD,IA(ON)
ASTTL
13
ASTTL
14
AND gates NOR gates OR gates AND-OR-INVERT (AOI) gates XOR gates Schmitt Trigger Inverters and NAND gates Tri-State buffers
TTL OR gate
Complex Logic TTL Gate Design 1. ANDing of signals Multi-emitter input BJT sections 2. ORing of signals Multiple input sections (QI and RB) Multiple drive splitting BJTs (QS) 3. If non-inverting ORing is desired Addional logic inversion circuitry 4. Totem-pole output branch
Example Design a complex logic TTL gate that VOUT = VAVB + VC + VDVEVF
Example Design a complex logic TTL gate that VOUT = VAVB + VC + VDVEVF
Hysteresis
VOHS = VCC
VCC VBE (SAT ) VCC VCE (SAT ) VOLS = R eq + VCE (SAT ) R CS1 R CS2
VCC VBE (SAT ) VCC VCE (SAT ) R eq + VBE ,S1( FA ) VIUS = R CS1 R CS2
VIDS =
R eq = R CS1 || R CS 2 || R E
Example
Find the VOHS, VOLS, VIUS and VIDS points where RCS1 = 4k, RCS2 = 2.5k, and RES = 1k.
VOHS = 5V
VOLS = 2V
Example
Find the VOH, VOL, VIU and VID points where RCS1 = 4k, RCS2 = 2.5k, and RES = 1k.
10
11
R CI VS =
R CI ( V BE ( SAT ) V EE ) RE R 1 + CI RE
Example
Calculate the critical VTC points for the ECL current switch VCC = 5V, VEE = 0V, VBB = 2.6V, RCI = RCR = RE = 1k, VBE(ECL) = 0.75V, VBE(SAT) = 0.8V, VBC(SAT) = 0.6V
VOH = 5V VOL = 3.10V VIL = 2.55V VIH = 2.65V VS = 3.2V VINV (VIN = VS) = 2.6V
V OH = V OL =
V EE V BE ( ECL ) R CI + ( F + 1) R DN RE
R CI V BE ( ECL ) R CI V BE ( ECL )
V IH V BE ( ECL ) + V EE
Example
Find the logical swing, noise margins and noise immunities for the MECL I circuit above. F = 49, VBE(ECL) = 0.75V, VBE(FA) = 0.75V, VBE(SAT) = 0.8V, VBC(SAT) = 0.6V VOH = 0.76V VOL = 1.55V VLS = 0.79V VIL = 1.225V VIH = 1.125V VNMH = 0.365V VNML = 0.325V VNIH = 0.53V VNIL = 0.475V VS = 0.29V
MECL I Fanout
I OH = I E ,BN ( FA ) I RDN
I N = OH I IH
I RDN =
VOH + VEE R DN I E ,BN ( FA ) = ( F + 1)I B,BN VOH VBE ,BN ( ECL ) I B,BN = R CI
I IH = I RE =
I RE F +1 VE + VEE RE
Fan-out Example
Find the maximum fan-out for the MECL I circuit above F = 49, VBE(ECL) = 0.75V, VBE(FA) = 0.75V, VBE(SAT) = 0.8V, VBC(SAT) = 0.6V Assume load gates reduce VOH by 0.03 volts. VOH = 0.79V IRDN = 2.205 mA IB,BN = 148 A IE,BN = 7.4 mA IOH = 5.2 mA VE = -1.54 V IRE = 2.95 mA IIH = 59 A
I N = OH = 87 I IH
Find the average power dissipated in the MECL I circuit above IRE(NOH) = 2.64 mA IRDN(NOH) = 2.22 mA IRDO(NOH) = 1.825 mA IEE(NOH) = 6.685 mA IRE(NOL) = 2.98 mA IRDN(NOL) = 1.825 mA IRDO(NOL) = 2.22 mA IEE(NOL) = 7.035 mA PEE(avg) = 35.6 mW
DeMorgans Theorems
NOR and OR using ANDs and NANDs NOR: OR:
A + B = AB
A + B = AB
AB = A + B
Example
Implement the following logic using only ECL gates
(A + B)(C + D)
Solution:
(A + B)(C + D) (A + B) + (C + D)
Example
10
Example
11
12
MOS Logic
MOS Logic
NMOS gates Fabrication Modes of operation NMOS Inverters and Analysis General NMOS Inverter Resistor Loaded NMOS Inverter E-MOSFET loaded NMOS Inverter D-MOSFET loaded NMOS Inverter
IV Characteristics
Load capacitance
Power dissipation
(a) Static power dissipation PDD = VDD (IDD(OH) + IDD(OL)) / 2 VDD IDD(OL) / 2 PTOTAL = PDD + PD (b) Transient power dissipation PD = CL V2DD : frequency at which the gate is switched
Propagation Delay
Fall time
NMOS Gates
Symbol Shorthands
10
NOR Gate
NOR Gates
11
NAND Gate
WO kO = L +L B A
OR Gates
12
AND Gates
Example
13
Examples
14
XOR/XNOR Gates
Hysteresis
15
Schmitt Trigger
Transmission Gate
16
CMOS Logic
17
CMOS Inverter
CMOS Inverter
18
19
20
CMOS Gates
Symbol Shorthands
21
22
23
24
25
26
Example
27
Example
28
XOR Gate
29