RISC vs CISC

System Bus
System Bus
A bunch of parallel wires
Transfer data among the components
Address bus (determine the amount of physical memory
addressable)
Data bus (indicate the size of the data transferred)
Control bus (consists of control signals:
memory/IO read/write, interrupt, bus
request/grand)

Every different processor has its own design
(different registers, buses, micro-operations, machine instructions, etc)
Program
A sequence of (machine) instructions
(Machine) Instruction
A group of bits that tell the computer to perform a specific operation (a sequence of micro-operation)
The Input Register (INPR) holds an 8 bit character gotten from an
input device
The Output Register (OUTR) holds an 8 bit character to be send to
an output device

CPU
CISC vs. RISC
SIX Instruction Set Design Issues
Number of Addresses
Flow of Control
Operand Types
Addressing Modes
Instruction Types
Instruction Formats



Processor
RISC and CISC designs
Reduced Instruction Set Computer (RISC)
Simple instructions, small instruction set
Operands are assumed to be in processor registers
Not in memory
Simplify design (e.g., fixed instruction size)
Examples: ARM (Advanced RISC Machines),
DEC Alpha (now Compaq)
Complex Instruction Set Computer (CISC)
Complex instructions, large instruction set
Operands can be in registers or memory
Instruction size varies
Typically use a microprogram
Example: Intel 80x86 family
CISC Methodology: Use additional hardware to perform
code translation and optimization.
Complex instructions written in a high
level language translate directly into
exactly one instruction in assembler.
Complex Instructions:

To multiply two numbers,
first load each operand from
a location in main memory
(locations 1:1 through 6:4)
into one of the six registers
(A, B, C, D, E, or F). Once
loaded, they can be
multiplied by the execution
unit (or ALU).

1. LOAD [A, 2:3]
2. LOAD [B, 5:2]
3. MULT [A, B]
4. STORE [2:3, A]

Complex Instructions:

CISC rolls up this
instruction set into one
compact instruction to
be handled by the
decoder.
MULT [2:3, 5:2]
Microcode engine
within the CPU
decodes the complex
instructions and
executes microcode
programs to carry out
the task
Pros and Cons of CISC:
Pro:
Complex instructions operate
directly on main memory.
Programmer is no longer
required to do a direct call to
LOAD and STORE operations
as they are now handled by
hardware.
Compiler has less work to
translate statements in a high
level language to assembly
language.
Con:
Microcode became more
difficult to test and debug as
systems became more
complex requiring numerous
patches to fix bugs.
Processor (cont.)
Processor (cont.)
Variations of the ISA-level can be implemented
by changing the microprogram
Instruction Set Design Issues
Number of Addresses
Flow of Control
Operand Types
Addressing Modes
Instruction Types
Instruction Formats
Number of Addresses
Four categories
3-address machines
2 for the source operands and one for the result
2-address machines
One address doubles as source and result
1-address machine
Accumulator machines
Accumulator is used for one source and result
0-address machines
Stack machines
Operands are taken from the stack
Result goes onto the stack
Number of Addresses (cont.)
Three-address machines
Two for the source operands, one for the
result
RISC processors use three addresses
Sample instructions
add dest,src1,src2
; M(dest)=[src1]+[src2]
sub dest,src1,src2
; M(dest)=[src1]-[src2]
mult dest,src1,src2
; M(dest)=[src1]*[src2]
Number of Addresses (cont.)
Example
C statement
A = B + C * D E + F + A
Equivalent code:
mult T,C,D ;T = C*D
add T,T,B ;T = B+C*D
sub T,T,E ;T = B+C*D-E
add T,T,F ;T = B+C*D-E+F
add A,T,A ;A = B+C*D-E+F+A
Number of Addresses (cont.)
Two-address machines
One address doubles (for source operand & result)
Last example makes a case for it
Address T is used twice
Sample instructions
load dest,src ; M(dest)=[src]
add dest,src ; M(dest)=[dest]+[src]
sub dest,src ; M(dest)=[dest]-[src]
mult dest,src ; M(dest)=[dest]*[src]
Number of Addresses (cont.)
Example
C statement
A = B + C * D E + F + A
Equivalent code:
load T,C ;T = C
mult T,D ;T = C*D
add T,B ;T = B+C*D
sub T,E ;T = B+C*D-E
add T,F ;T = B+C*D-E+F
add A,T ;A = B+C*D-E+F+A
Number of Addresses (cont.)
One-address machines
Use special set of registers called accumulators
Specify one source operand & receive the result
Called accumulator machines
Sample instructions
load addr ; accum = [addr]
store addr ; M[addr] = accum
add addr ; accum = accum + [addr]
sub addr ; accum = accum - [addr]
mult addr ; accum = accum * [addr]
Number of Addresses (cont.)
Zero-address machines
Stack supplies operands and receives the result
Special instructions to load and store use an address
Sample instructions
push addr ; push([addr])
pop addr ; pop([addr])
Load/Store Architecture
Instructions expect operands in internal processor registers
Special LOAD and STORE instructions move data between
registers and memory
RISC uses this architecture
Reduces instruction length

Load/Store Architecture (cont.)
Sample instructions
load Rd,addr ;Rd = [addr]
store addr,Rs ;(addr) = Rs
add Rd,Rs1,Rs2 ;Rd = Rs1 + Rs2
sub Rd,Rs1,Rs2 ;Rd = Rs1 - Rs2
mult Rd,Rs1,Rs2 ;Rd = Rs1 * Rs2

Flow of Control
Default is sequential flow
Several instructions alter this default
execution
Branches
Unconditional
Conditional
Delayed branches
Flow of Control (cont.)
e.g., Pentium e.g., SPARC
Operand Types
Instructions support basic data types
Characters
Integers
Floating-point
Instruction overload
Same instruction for different data types
Example: Pentium
mov AL,address ;loads an 8-bit value
mov AX,address ;loads a 16-bit value
mov EAX,address ;loads a 32-bit value

Addressing Modes
How the operands are specified
Operands can be in three places
Registers
Register addressing mode
Part of instruction
Constant
Immediate addressing mode
All processors support these two addressing modes
Memory
Difference between RISC and CISC
CISC supports a large variety of addressing modes
RISC follows load/store architecture
Instruction Types
Several types of instructions
Data movement
mov dest,src
add Rdest,Rsrc,0 ;Rdest = Rsrc+0
Arithmetic and Logical
Arithmetic
Integer and floating-point, signed and unsigned
add, subtract, multiply, divide
Logical
and, or, not, xor
Instruction Types (cont.)
Flow control and I/O instructions
Branch
Interrupts
I/O instructions
Memory-mapped I/O
Most processors support memory-mapped I/O
No separate instructions for I/O
in AX,io_port ;read from an I/O port
out io_port,AX ;write to an I/O port
Instruction Formats
Two types
Fixed-length
Used by RISC processors
32-bit RISC processors use 32-bits wide instructions
Examples: SPARC, MIPS, PowerPC
Variable-length
Used by CISC processors
Memory operands need more bits to specify