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    VHDL Processes: Cwru Eecs 318

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    KarThik
    The assignment involves designing an RTL diagram, opcode formats, and opcode bits for a Harvard architecture CPU with the following specifications: - 16-bit instruction memory and 8-bit data memory using ROM and RAM respectively. - Eight 8-bit registers and an ALU that sets flags for arithmetic instructions. - The instruction set includes arithmetic, logical, load, store, branch, and jump instructions. - An RTL diagram of the CPU architecture is required showing the data path and control signals. - Opcode formats must be defined to specify the operation and registers/addresses. - Opcode bits need to

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    VHDL Processes: Cwru Eecs 318

    Uploaded by

    KarThik
    34 views24 pages
    The assignment involves designing an RTL diagram, opcode formats, and opcode bits for a Harvard architecture CPU with the following specifications: - 16-bit instruction memory and 8-bit data memory using ROM and RAM respectively. - Eight 8-bit registers and an ALU that sets flags for arithmetic instructions. - The instruction set includes arithmetic, logical, load, store, branch, and jump instructions. - An RTL diagram of the CPU architecture is required showing the data path and control signals. - Opcode formats must be defined to specify the operation and registers/addresses. - Opcode bits need to

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    Original Title

    eecs_318_8

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    The assignment involves designing an RTL diagram, opcode formats, and opcode bits for a Harvard architecture CPU with the following specifications: - 16-bit instruction memory and 8-bit data memory using ROM and RAM respectively. - Eight 8-bit registers and an ALU that sets flags for arithmetic instructions. - The instruction set includes arithmetic, logical, load, store, branch, and jump instructions. - An RTL diagram of the CPU architecture is required showing the data path and control signals. - Opcode formats must be defined to specify the operation and registers/addresses. - Opcode bits need to

    Copyright:

    © All Rights Reserved
    Download as PPT, PDF, TXT or read online from Scribd
    Download as ppt, pdf, or txt
    34 views24 pages

    VHDL Processes: Cwru Eecs 318

    Uploaded by

    KarThik
    The assignment involves designing an RTL diagram, opcode formats, and opcode bits for a Harvard architecture CPU with the following specifications: - 16-bit instruction memory and 8-bit data memory using ROM and RAM respectively. - Eight 8-bit registers and an ALU that sets flags for arithmetic instructions. - The instruction set includes arithmetic, logical, load, store, branch, and jump instructions. - An RTL diagram of the CPU architecture is required showing the data path and control signals. - Opcode formats must be defined to specify the operation and registers/addresses. - Opcode bits need to

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    © All Rights Reserved
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    of 24

    EECS 318 CAD

    Computer Aided Design

    LECTURE 8:
    VHDL PROCESSES
    Instructor: Francis G. Wolff
    wolff@eecs.cwru.edu
    Case Western Reserve University
    This presentation uses powerpoint animation: please viewshow

    2-to-1 Multiplexor: and Datapath multiplexor


    a

    behavioral

    Y
    b

    n
    n

    0
    n

    Datapath
    Datapathis
    isnnbits
    bitswide
    wide

    WITH
    WITHssSELECT
    SELECT
    YY<=
    <=aa WHEN
    WHEN0,
    0,
    bb WHEN
    WHENOTHERS;
    OTHERS;

    WITH
    WITHss SELECT
    SELECT
    YY<=
    <= aaWHEN
    WHEN0,
    0,
    bb WHEN
    WHENOTHERS;
    OTHERS;

    Where
    Whereis
    isthe
    the difference?
    difference?

    Generic 2-to-1 Datapath Multiplexor Entity


    a

    LIBRARY IEEE;
    USE IEEE.std_logic_1164.all;
    USE IEEE.std_logic_arith.all;

    n
    n

    0
    1

    ENTITY Generic_Mux IS
    S
    GENERIC (n: INTEGER);
    PORT (Y:
    OUT std_logic_vector(n-1 downto 0);
    a:
    IN
    std_logic_vector(n-1 downto 0);
    b:
    IN
    std_logic_vector(n-1 downto 0);
    S:
    IN
    std_logic_vector(0 downto 0)
    );
    END ENTITY;

    Generic 2-to-1 Datapath Multiplexor Architecture


    ARCHITECTURE Generic_Mux_arch OF Generic_Mux IS
    BEGIN
    WITH S SELECT
    Y <= a WHEN "1",
    b WHEN OTHERS;
    END ARCHITECTURE;
    CONFIGURATION Generic_Mux_cfg OF Generic_Mux IS
    FOR Generic_Mux_arch
    END FOR;
    Configurations
    Configurationsare
    are
    END CONFIGURATION;
    require
    requirefor
    forsimulation
    simulation

    Structural SR Flip-Flop (Latch)


    R

    Q
    Q

    R
    0
    0
    1
    1

    NAND
    S Qn+1
    0 U
    1 1
    0 0
    1 Qn

    ENTITY Latch IS
    PORT(R, S: IN std_logic; Q, NQ: OUT std_logic);
    END ENTITY;
    ARCHITECTURE latch_arch OF Latch IS
    BEGIN
    Q
    <= R NAND NQ;
    NQ
    <= S NAND Q;
    END ARCHITECTURE;

    Inferring Behavioral Latches: Asynchronous


    Sensitivity
    Sensitivitylist
    list of
    of signals:
    signals:
    Every
    Everytime
    timeaachange
    changeof
    of
    state
    stateor
    orevent
    event occurs
    occurson
    on
    these
    thesesignals
    signalsthis
    this
    process
    processwill
    willbe
    becalled
    called

    NAND
    R S Qn+1
    R
    Q
    0 0 U
    0 1 1
    1 0 0
    Q
    S
    1 1 Qn
    ARCHITECTURE Latch2_arch OF Latch IS Sequential
    Sequential
    Statements
    BEGIN
    Statements
    PROCESS (R, S) BEGIN
    IF R= 0 THEN
    Q <= 1; NQ<=0;
    ELSIF S=0 THEN
    Q <= 0; NQ<=1;
    END IF;
    END PROCESS;
    END ARCHITECTURE;

    Gated-Clock SR Flip-Flop (Latch Enable)


    S
    Q
    LE
    Q

    R
    ARCHITECTURE Latch_arch OF GC_Latch IS BEGIN
    PROCESS (R, S, LE) BEGIN
    IF LE=1 THEN
    IF R= 0 THEN
    Q <= 1; NQ<=0;
    ELSIF S=0 THEN
    Q <= 0; NQ<=1;
    END IF;
    END IF;
    END PROCESS;
    END ARCHITECTURE;

    Inferring D-Flip Flops: Synchronous


    Notice
    Noticethe
    theProcess
    Process
    does
    does not
    notcontain
    contain D:
    D:
    ARCHITECTURE Dff_arch OF Dff IS PROCESS(Clock,
    PROCESS(Clock,D)
    D)
    BEGIN
    Sensitivity
    Sensitivitylists
    lists
    contain
    contain signals
    signalsused
    used
    in
    inconditionals
    conditionals(i.e.
    (i.e. IF)
    IF)
    PROCESS (Clock) BEGIN
    IF ClockEVENT AND Clock=1 THEN
    Q <= D;
    END IF;
    END PROCESS;
    END ARCHITECTURE;
    ClockEVENT
    ClockEVENTis
    iswhat
    what
    distinguishes
    distinguishes aaDDFlipFlip
    FlipFlipfrom
    fromaaLatch
    Latch

    Inferring D-Flip Flops: rising_edge


    ARCHITECTURE Dff_arch OF Dff IS BEGIN
    PROCESS (Clock) BEGIN
    IF ClockEVENT AND Clock=1 THEN
    Q <= D;
    Alternate
    Alternateand
    and
    END IF;
    more
    morereadable
    readableway
    wayis
    is
    END PROCESS;
    to
    touse
    usethe
    the
    END ARCHITECTURE;
    rising_edge
    rising_edgefunction
    function
    ARCHITECTURE dff_arch OF dff IS BEGIN
    PROCESS (Clock) BEGIN
    IF rising_edge(Clock) THEN
    Q <= D;
    END IF;
    END PROCESS;
    END ARCHITECTURE;

    Inferring D-Flip Flops: Asynchronous Reset


    ARCHITECTURE dff_reset_arch OF dff_reset IS BEGIN
    PROCESS (Clock, Reset) BEGIN
    IF Reset= 1 THEN -- Asynchronous Reset
    Q <= 0
    ELSIF rising_edge(Clock) THEN --Synchronous
    Q <= D;
    END IF;
    END PROCESS;
    END ARCHITECTURE;

    Inferring D-Flip Flops: Synchronous Reset


    PROCESS
    PROCESS(Clock,
    (Clock,Reset)
    Reset) BEGIN
    BEGIN
    IF
    IFrising_edge(Clock)
    rising_edge(Clock) THEN
    THEN
    Synchronous
    Reset
    Synchronous
    Reset
    IF
    IFReset=1
    Reset=1THEN
    THEN
    Q
    Synchronous
    Q <=
    <= 0
    0
    Synchronous FF
    FF
    ELSE
    ELSE
    Q
    Q <=
    <= D;
    D;
    END
    ENDIF;
    IF;
    END
    ENDIF;
    IF;
    END
    ENDPROCESS;
    PROCESS;
    PROCESS
    PROCESS(Clock,
    (Clock,Reset)
    Reset) BEGIN
    BEGIN
    Asynchronous
    AsynchronousReset
    Reset
    IF
    IFReset=1
    Reset=1THEN
    THEN
    Synchronous
    Synchronous FF
    FF
    Q
    Q <=
    <= 0
    0
    ELSIF
    ELSIF rising_edge(Clock)
    rising_edge(Clock) THEN
    THEN
    Q
    Q <=
    <= D;
    D;
    END
    ENDIF;
    IF;
    END
    ENDPROCESS;
    PROCESS;

    D-Flip Flops: Asynchronous Reset & Preset

    PROCESS
    PROCESS(Clock,
    (Clock,Reset,
    Reset, Preset)
    Preset) BEGIN
    BEGIN
    IF
    IFReset=1
    Reset=1 THEN
    THEN--highest
    --highestpriority
    priority
    Q
    Q <=
    <= 0;
    0;
    ELSIF
    ELSIF Preset=1
    Preset=1 THEN
    THEN
    Q
    Q <=
    <= 0;
    0;
    ELSIF
    ELSIF rising_edge(Clock)
    rising_edge(Clock) THEN
    THEN
    Q
    Q <=
    <= D;
    D;
    END
    ENDIF;
    IF;
    END
    ENDPROCESS;
    PROCESS;

    RTL Multi-cycle Datapath: with controller


    PCWriteCond

    PCSource

    PCWrite
    ALUOp
    Outputs
    IorD
    ALUSrcB
    MemRead
    ALUSrcA
    Control
    MemWrite
    RegWrite
    MemtoReg
    Op
    RegDst
    IRWrite
    [5 0]

    26

    Instruction [25 0]

    PC

    0
    M
    u
    x
    1

    Instruction
    [31-26]
    Address
    Memory
    MemData
    Write
    data

    Instruction
    [25 21]

    Read
    register 1

    Instruction
    [20 16]

    Read
    Read
    register 2 data 1
    Registers
    Write
    Read
    register data 2

    Instruction
    [15 0]
    Instruction
    register
    Instruction
    [15 0]
    Memory
    data
    register

    0
    M
    Instruction u
    x
    [15 11]
    1
    0
    M
    u
    x
    1

    B
    4

    16

    Sign
    extend

    32

    Shift
    left 2

    Jump
    address [31-0]

    Zero
    ALU ALU
    result

    0
    1 M
    u
    2 x
    3

    ALU
    control

    Instruction [5 0]

    Register
    RegisterTransfer
    TransferLevel
    Level(RTL)
    (RTL)View
    View

    ALUOut

    1 u
    x

    PC [31-28]

    0
    M
    u
    x
    1

    Write
    data

    Shift
    left 2

    28

    CPU controller: Finite State Machine


    ALUzero
    PCWriteEnable

    PCWriteCond
    PCWrite
    MemRead
    MemWrite
    IorDMux FSM
    IRWrite

    Clock Reset

    PCSourceMux
    ALUOp
    ALUSrcAMux
    ALUSrcBMux
    RegWrite
    RegDstMux
    MemtoReg

    IRopcode

    CPU Controller: Entity


    ENTITY cpu_controller is PORT(
    CLK, RST
    :IN std_logic;
    IRopcode
    :IN std_logic_vector(5 downto 0);
    ALUzero
    :IN std_logic;
    PCWriteEnable
    :OUT std_logic;
    PCSourceMux
    :OUT std_logic_vector(1 downto 0);
    MemRead, MemWrite :OUT std_logic;
    IorDMux
    :OUT std_logic;
    IRWrite
    :OUT std_logic;
    RegWrite
    :OUT std_logic;
    RegDstMux
    :OUT std_logic;
    MemtoRegMux
    :OUT std_logic;
    ALUOp
    :OUT std_logic_vector(2 downto 0)
    ALUSrcAMux
    :OUT std_logic;
    ALUSrcBMux
    :OUT std_logic_vector(1 downto 0);
    ); END ENTITY;

    CPU controller: R-Format State Machine


    Cycle 1 Cycle 2

    R-Format

    Clock=1

    Ifetch

    Reg/Dec

    Exec

    Decode

    Wr

    Clock=1

    Exec
    Rtype

    Fetch

    Clock=1

    Cycle 3 Cycle 4

    Write
    Rtype

    Clock=1

    CPU Controller: Current State Process


    ARCHITECTURE cpu_controller_arch OF cpu_controller IS
    TYPE CPUStates IS (Fetch, Decode, ExecRtype, WriteRtype);
    SIGNAL State, NextState :CPUStates;
    BEGIN
    PROCESS (State) BEGIN
    CASE State IS
    WHEN Fetch=> NextState <= Decode;
    WHEN Decode
    => NextState <= ExecRtype;
    WHEN ExecRtype => NextState <= WriteRtype;
    WHEN WriteRtype => NextState <= Fetch;
    WHEN OTHERS => NextState <= Fetch;
    END CASE;
    END PROCESS;

    CPU controller: NextState Clock Process

    PROCESS (CLK, RST) BEGIN


    IF RST='1' THEN -- Asynchronous Reset
    State <= Fetch;
    ELSIF rising_edge(CLK) THEN
    State <= NextState;
    END IF;
    END PROCESS;
    END ARCHITECTURE;

    T1 Fetch: State machine


    Cycle 1 Cycle 2

    Start

    R-Format

    Ifetch

    Cycle 3 Cycle 4

    Reg/Dec

    MemRead=1,
    MemRead=1, MemWrite=0
    MemWrite=0
    IorD=1
    (MemAddrPC)
    IorD=1
    (MemAddrPC)
    IRWrite=1
    (IRMem[PC])
    IRWrite=1
    (IRMem[PC])
    ALUOP=ADD
    ALUOP=ADD (PC4+PC)
    (PC4+PC)
    ALUSrcA=0
    ALUSrcA=0 (=PC)
    (=PC)
    ALUSrcB=1
    ALUSrcB=1 (=4)
    (=4)
    PCWrite=1,
    PCWrite=1,PCSource=1
    PCSource=1(=ALU)
    (=ALU)
    RegWrite=0,
    RegWrite=0,
    RegDst=X,
    RegDst=X, MemtoReg=X
    MemtoReg=X
    Instruction Fetch

    Exec

    Wr

    Decode

    Exec

    Write
    Reg

    T1 Fetch: VHDL with Moore Output States


    MemRead=1,
    MemRead=1, MemWrite=0
    MemWrite=0
    PROCESS (State) BEGIN
    IorD=1
    (MemAddrPC)
    IorD=1
    (MemAddrPC)
    CASE State IS
    IRWrite=1
    (IRMem[PC])
    IRWrite=1
    (IRMem[PC])
    WHEN Fetch =>
    ALUOP=ADD
    ALUOP=ADD (PC4+PC)
    (PC4+PC)
    NextState
    <= Decode;
    ALUSrcA=0
    ALUSrcA=0 (=PC)
    (=PC)
    ALUSrcB=1
    MemRead
    <= '1';
    ALUSrcB=1 (=4)
    (=4)
    PCWrite=1,
    PCWrite=1,PCSource=1
    PCSource=1(=ALU)
    (=ALU)
    MemWrite
    <= '0';
    RegWrite=0,
    RegWrite=0,
    IorD
    <= '1'
    RegDst=X,
    RegDst=X, MemtoReg=X
    MemtoReg=X
    IRWrite
    <= '1';
    Instruction Fetch
    ALUOp
    <= "010;
    --add
    ALUSrcAMux <= '1';
    --PC
    'D'
    'D'for
    for Dont
    DontCare
    Care
    ALUSrcBMux <= "01";
    --4
    PCWriteEnable<= '1';
    PCSourceMux <= "00"; --ALU (not ALUOut)
    RegWrite
    <= '0';
    RegDstMux
    <= 'D'; MemtoReg <= 'D';

    VHDL inferred Latches: WARNING


    In VHDL case statement
    The same signal must be defined for each case
    Otherwise that signal will be inferred as a latch
    and not as combinatorial logic!
    For example,
    Even though RegDstMux <= 'D' is not used
    and was removed from the Decode state
    This will result in a RegDstMux
    being inferred as latch not as logic
    even though in the WriteRtype state it is set

    Assignment #3: CPU Architecture design (1/3)


    Cyber Dynamics Corporation (18144 El Camino Real, SVale
    California) needs the following embedded model 101
    microprocessor designed by Thursday October 5, 2000 with
    the following specifications
    16 bit instruction memory using ROM
    8 bit data memory using RAM
    There are eight 8-bit registers
    The instruction set is as follows
    All Arithmetic and logical instructions set a Zero one-bit flag
    (Z) based on ALU result
    add, adc, sub, sbc set the Carry/Borrow one-bit Flag (C)
    based on ALU result

    Assignment #3: CPU Architecture design (2/3)


    Arithmetic and logical instructions
    add $rt,$rs
    #$rt = $rt +$rs; C=ALUcarry; Z=$rt
    adc $rt, $rs
    #$rt = $rt +$rs+C; C=ALUcarry; Z;
    sub $rt, $rs
    #$rt = $rt - $rs; C=ALUborrow; Z;
    sub $rt, $rs
    #$rt = $rt - $rs - borrow; C; Z;
    and $rt, $rs
    #$rt = $rt & $rs;
    C=0; Z=$rt;
    or $rt, $rs
    #$rt = $rt | $rs;
    C=0; Z=$rt;
    xor $rt, $rs
    #$rt = $rt ^ $rs;
    C=1; Z=$rt;
    Other Instructions continued):
    lbi
    $r, immed #$r = immediate
    lbr
    $rt,$rs
    #$rt = Mem[$rs]
    lb
    $r, address #$r = Mem[address]
    stb $r, address #Mem[address]=$r
    bz
    address
    #if zero then pc=pc+2+addr
    bc
    address
    #if carry then pc=pc+2+addr
    j
    address
    #pc = address
    jr
    $r
    #pc = $r

    Assignment #3: CPU Architecture design (2/3)


    (1a) Design an RTL diagram of the model 101 processor and
    (1b) Opcode formats and
    (1c) Opcode bits of a Harvard Architecture CPU (determine
    your own field sizes).
    (1d) What is the size of the Program Counter?
    (2) Write the assembly code for a 32 bit add Z=X+Y located in
    memory address for @X = 0x80 @Y = 0x84 and @Z=0x88
    (3) Draw the state diagram for your FSM controller
    (4) Write the VHDL code for the FSM controller

    Note: this will be part of your final project report

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