Scan Chain Reorder

Sying-Jyan Wang
Department of Computer Science
National Chung-Hsing University

NCHUCS

Outline

Overview
Scan chain order: does it matter?
Cluster-based reordering for lowpower BIST
Experimental results
Future work

NCHUCS

Outline

Overview
Scan chain order: does it matter?
Cluster-based reordering for lowpower BIST
Experimental results
Future work

NCHUCS

Digital Testing

To detect manufacturing defects

Apply test patterns and observe
output responses
Test patterns generated for targeted
fault models

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Scenario for Manufacture Test

TEST VECTORS

MANUFACTURED
CIRCUIT

CORRECT
RESPONSES

CIRCUIT RESPONSE

COMPARATOR

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PASS/FAIL

Scan Test (1)

A structural design-for-testability
technique
Storage elements are not directly
accessible
Scan test provides an easy way for
test access

Apply test patterns to circuit under test

(CUT)
Read output responses from CUT
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Scan Test (2)

Sequential circuit

FFs are neither controllable nor observable

Primary
Input

Combinational Logic

Primary
Output

F
F
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Scan Test (3)

Normal signal path: parallel load

Primary
Input

Combinational Logic

Primary
Output

F
F
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Scan Test (4)

In scan mode: a shift register

Primary
Input

Combinational Logic

Primary
Output

Scan out
(SO)

F
F
Scan in
(SI)

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Scan Test (5)

To enable scan test

Each scan cell has two inputs

Normal input

Scan input
All scan cells are connected into a shift register
(scan chain)

Turn a sequential test into a combinational

one

Apply test patterns directly

Observe test results directly
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Scan Chain

Normally constructed when

placement and routing are done
The order does not matter
Find out the shortest scan chain order

Traveling salesman problem (TSP)

Asymmetric TSP (ATSP)

SI and SO of a scan cell are not at the

same location

NP-complete
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Outline

Overview
Scan chain order: does it matter?
Cluster-based reordering for lowpower BIST
Experimental results
Future work

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Scan Test for Stuck-at Faults

Order does not matter

As long as we can scan in test patterns
and scan out test responses

CUT

1010

1100

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Minimum Wirelength Routing

Use a TSP/ATSP solver

Slow

Wirelength can be 10x with random

order

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Low-Power Testing

A great concern in recent years

Need to reduce signal transitions

The source of dynamic power in CMOS

Usually the dominant factor

Reorder scan chain to reduce

switching activity

1010

1100

1 transition only

3 transitions
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Delay Testing (1)

Require two-pattern tests

First pattern: initialization

Second pattern: launch transition

Delay test with simple scan chain

Broadside

The output response of the 1st pattern are

captured in the scan chain and become the 2nd
pattern
Skewed load

The 2nd pattern is the result of 1-bit shift of the

1st pattern
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Delay Test (2)

Broadside test

Eg. Apply v1=(1010), v2=(0100)

Primary
Input

Combinational Logic

1
0
1
0

0
1
0
0

0
1
0
0

Primary
Output

F
F
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Delay Test (3)

Skewed load

Not all test pairs possible

2n2n possible 2-pattern combinations
Only 22n possible with single scan chain

1010
0110

Reorder scan chain to achieve higher

fault coverage

1100

NOT POSSIBLE!!
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18

Hold Time Violation

Not enough propagation delay

between adjacent flip-flops in a
sequential circuit

Double latching

Possible solution

Reorder scan cells to introduce extra

delay
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Outline

Overview
Scan chain order: does it matter?
Cluster-based reordering for
lower-power BIST
Experimental results
Future work

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Overview

Goal: Reduce BIST power

Approach

Include a smoother to reduce switching

activity in test pattern generator (TPG)
Use scan chain reordering to recover lost
fault coverage

Simple reordering algorithm

Wirelength should not increase too much

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Overall Architecture
Single scan chain

PRPG

Smoother

Internal scan chain

TPG

multiple scan chain

P
R
P
G

ORA

CUT

P
h
a
s
e
s
h
i
f
t
e
r

Smoother

Internal scan chain 1

Smoother

Internal scan chain 2

.
.
.
.

Smoother

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.
.
.
.

O
R
A

Internal scan chain k

22

Smoother
4-state (2bit)
smoother

n-state smoother

8-state (3bit)
smoother
1/1
1/0

1/1

0/1

S1

S5
S0

1/0

0/1

1/1

0/1

0/0

S2

1/0

0/0
0/0

S4

S0
0/1
0/0

0/0

0/1

1/1

S2

1/0

S0

S1

S3
0/1

S6
0/0

Sn/2

.
.
.

1/0

1/1

0/0

1/1

1/0
1/0

0/0

0/1

.
.
.

1/1

0/1

0/0

0/1

1/1

Sn/21

Sn1

S3

S7

1/0

1/0

1/1

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A Simple Implementation of the

n-state smother

in

C0

C
Divide-by-n/2
Up-Down Counter

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q
T
q

24

Estimation of Power Reduction

Probability of signal transition of an

n-state smoother
P( 01) (10 )

2
2

n2 n

Compute from Markov chain model

Estimation of dynamic power

2-bit (4-state ) smoother: 1/3

3-bit (8-state) smoother: 1/10
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Fault Coverage

Smoothed patterns are less random

May create repeated patterns and reduce

fault coverage
PRPG

101010100101100

2-bit smoother

000000011110000

3-bit smoother

000000000000000

Required test cube:

Reorder scan chain:

xxxxx01xxxxxxxx

xxxxx0x1xxxxxxx

NO MATCH!

MATCH
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2-bit smoother
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Cluster-Based Scan Chain Reorder

Layout surface divided into clusters

Reorder limited in single cluster
Snake-like global routing
Single scan chain

Multiple scan chains

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Example

Routing s15850

611 scan cells

1 cluster

256 clusters

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Silicon Ensemble

28

Optimal Cluster Size

Is there an optimal cluster size?

Observation

Large clusters--long vertical connection

Small clusters--more horizontal crossings

How to find optimal cluster size

Find an expression of total wirelength

Take its derivative with respect to cluster
size c
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Estimate Wirelength in a Cluster

(1)

Two types of order

Random order
CL2

CL1

sc4
sc1
sc5

sc2
sc3

Sorted according to x-cooridnate

CL1
sc1
sc2
sc3

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Estimate Wirelength in a Cluster

(2)

How to estimate the distance

between two cells

Manhattan distance
Horizontal and vertical distances are
independent
Assuming cells are randomly distributed
w
sc1(X1, Y1)
h
sc2(X2, Y2)
(0, 0)

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Estimate Wirelength in a Cluster

(3)

Expected vertical distance between

two cells
E Y1 Y2

1
h
y1 y2 2 dy2 dy1
h
3

Expected horizontal distance between

two cells

Random order: w/3

Sorted order

Summation of all horizontal distances: w

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Estimate Wirelength in a Cluster

(4)

Random order

N: # cells, c2: #clusters

1
l 2 w
2

h N

1
2

3 c

1
H N

W 2 1
c
3 c

wh

W H

3c

Sorted order

1 h N
h
N H W
l 2 2 1 w 2

c
3
c 3c
2 3 c
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Optimal Number of Clusters (1)

Random order
N
2W

2
W H
c

Assuming H W, N/c2 1

Sorted order
N 3W

2
H
c

Assuming H W, N/c2 3
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Optimal Number of Clusters (2)

Reordering algorithm

Larger clusters give better results

Almost no reordering when N/c2 1
Choose sorted order if no special order is
preferred

Optimal cluster size

2 N/c2 3

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Outline

Overview
Scan chain order: does it matter?
Cluster-based reordering for lowpower BIST
Experimental results
Future work

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Experimental ResultsWire Length

(1)

2-bit smoother

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Experimental ResultsWire Length

(2)

3-bit smoother

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Experimental ResultsFault
Coverage (1)

2-bit smoother

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Experimental ResultsFault
Coverage (2)

3-bit smoother

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Optimal Number of Cells per

Cluster
Circuit

WL (mm)
-- SE

#cluster

S641

2.71

36

S713

2.67

S953

#cells/cluster

2-bit smoother

3-bit smoother

GS

WL (mm)

Red (%)

GS

WL (mm)

Red (%)

1.50

2.83

-4.24

2.84

-4.58

36

1.50

2.90

-7.93

10

2.90

-7.93

3.30

16

2.81

3.68

-10.33

3.69

-10.57

S1196

4.74

16

2.00

5.08

-6.69

5.09

-6.88

S1423

5.70

36

2.53

6.04

-5.53

6.04

-5.63

S5378

14.57

100

2.14

15.78

-7.67

15.77

-7.61

S9234

22.68

100

2.47

23.21

-2.28

23.75

-4.51

S13207

45.22

256

2.73

44.74

1.06

45.49

-0.59

S15850

53.40

256

2.39

10

51.97

2.68

50.98

4.53

S38417

136.94

576

2.89

123.3

9.96

125.72

8.19

S38584

187.89

576

2.54

10

177.82

5.36

178.14

5.19

SE: Silicon Ensemble

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Test Efficienct
Circuit

TL

Test Efficiency (%)

Markov
Source
BIST

LFSR

2-bit smoother

3-bit smoother

SE

Optimal Cluster

SE

Optimal Cluster

S9234

72848

98.52

95.02

93.46

95.47

83.39

92.00

S13207

40677

97.88

98.90

92.73

97.84

83.64

87.72

S15850

37767

98.31

96.41

93.47

97.69

90.62

92.79

S38417

81984

95.42

97.20

94.79

95.96

93.5

94.47

S38584

82055

98.36

99.76

95.29

99.23

90.35

95.82

Average

97.70

97.46

93.95

97.24

88.3

92.56

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Comparison of Average Power

Circuit

#scan
cells

TL

FC
(
%
)
LFSR

2-bit smoother*
FC

FC
(
%
)

(
%
)

SE

Opt.
cluster

3-bit smoother*

AP
Red
(%)

FC

FC
(
%
)

(
%
)

SE

Opt.
cluster

LT-RTPG (k=3)

AP
Red
(%)

FC
(
%
)

AP
Red
(%)

S641

54

4096

97.42

94.19

95.91

57.41

87.31

90.75

85.65

89.64

36.9

S713

54

4096

91.94

87.99

89.88

58.15

83.70

83.70

86.36

93.34

37.8

S953

45

8192

98.99

86.41

97.97

55.47

54.26

80.17

84.95

85.61

58.7

S1196

32

4096

95.49

82.63

92.71

56.58

59.40

78.72

85.40

95.87

30.2

S1423

91

4096

97.89

95.40

98.59

57.25

88.75

96.29

85.09

97.08

49.7

S5378

214

65536

98.96

97.91

98.56

58.51

90.26

95.50

84.75

97.08

44.0

S9234

247

131072

89.67

87.91

91.40

59.37

77.49

86.78

85.53

91.63

55.7

S13207

700

40677

97.42

91.25

96.37

62.67

82.17

86.24

87.39

S15850

611

37767

93.06

90.12

94.43

58.21

87.27

89.44

84.96

S38417

1664

81984

96.67

94.26

95.42

60.73

92.97

93.93

84.93

S38584

1464

82055

95.70

91.05

95.00

60.87

86.14

91.58

84.81

Average
95.75
90.83
95.11
*Full scan; : only state vectors are scanned

58.66

80.88

88.46

85.44

92.89

44.71

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Peak Power

Capture-cycle power is not reduced

Still provide some improvement
Circuit

PP Red (%)
2-bit smoother

3-bit smoother

S5378

13.31

11.64

S9234

13.75

16.68

S13207

12.65

19.96

S15850

13.60

20.23

S38417

13.78

19.24

S38584

13.12

18.01

Average

13.37

17.63

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Outline

Overview
Scan chain order: does it matter?
Cluster-based reordering for lowpower BIST
Experimental results
Future work

NCHUCS

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Conclusion

Scan chain reorder is very effect to

deal with

Test power
Scan-based delay test
Fault coverage in BIST

Need to consider

Physical design infromation

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Future Work

Fast reordering algorithm for delay

test
Integrate reordering algorithm,
considering

Test power
Delay test coverage
Wire length
Other issues
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THE END

Thank You!

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