Design Rules

 Design rules are a set of geometrical

specifications that dictate the design of the
layout masks
 A design rule set provides numerical values
 For minimum dimensions
 For minimum line spacings
 Design rules must be followed to insure
functional structures on the fabricated chip
 Design rules change with technological
advances (www.mosis.org)
Silicon Foundry
 A standard
 A foundry allows designers to submit designs
using a state-of-the-art process
 Each foundry state simpler set of design rules
called lambda design rules
 All widths, spacings, and distances are
written in the form
 Value = m 
 TSMC (Thailand Semiconductor Manufacturing
Corporation)
Design Rules Classification

 Minimum width
 Minimum spacing
 Surround
 Extension
Physical Limitations

 Line width limitation of an imaging system

 The reticle shadow projected on the photoresist
does not have sharp edges due to optical
diffraction
 Etching process problem
 Undercutting of the resist due to lateral etching
decreases the resolution
Etching Process Problem

Vertical etching
Lateral
Etching

Substrate Substrate

Isotropic etch
Depletion Region

 If depletion regions of adjacent pn junctions

touch, then
 The current blocking characteristics are altered
 Current can flow between the two

Spacing

n+ n+
Substrate

Limits on n+ spacing
Electrical Capacitive Coupling

 This occurs between closely spaced

conducting lines
 This leads to a problem called crosstalk
 A portion of the electrical energy is coupled to
another causing noise
 This is a major problem in high-density design
Electrical Rules

 An example of an electrical rule is the

allowed width of a metal interconnect line
 To avoid electromigration effects
 The design rule set will stipulate the maximum
current flow level permitted
3D Perspective

Polysilicon Aluminum
Design rules and Layout

 Why we use design rules?

 Interface between designer and process
engineer
 Guidelines for constructing process masks
Design Rules
Minimum length or width of a feature on a layer is 2

Why?
To allow for shape contraction
Minimum separation of features on a layer is 2

Why?
To ensure adequate continuity of the intervening
materials.
Design Rules
Minimum width of PolySi and diffusion line 2
Minimum width of Metal line 3 as metal lines run over a more uneven
surface than other conducting layers to ensure their continuity

Metal

Diffusion


  Polysilicon
Design Rules
PolySi – PolySi space 2
Metal - Metal space 2
Diffusion – Diffusion 3 To avoid the possibility of their associated
regions overlapping and conducting current

Metal

Diffusion

  Polysilicon
Design Rules
Diffusion – PolySi  To prevent the lines overlapping to form
unwanted capacitor
Metal lines can pass over both diffusion and polySi without
electrical effect. Where no separation is specified, metal lines
can overlap or cross

Metal

Diffusion

 Polysilicon
Metal Vs PolySi/Diffusion
 Metal lines can pass over both diffusion
and polySi without electrical effect
 It is recommended practice to leave 
between a metal edge and a polySi or
diffusion line to which it is not
electrically connected
Metal


Polysilicon
Review:
 poly-poly spacing 2

 diff-diff spacing 3
(depletion regions tend to spread outward)

 metal-metal spacing 2

 diff-poly spacing 
Note

Two Features on different mask layers can be

misaligned by a maximum of 2 on the wafer.
 If the overlap of these two different mask layers
can be catastrophic to the design, they must be
separated by at least 2
 If the overlap is just undesirable, they must be
separated by at least
When a transistor is formed?

Gate is formed where polySi crosses diffusion with

thin oxide between these layers.

Design rules
min. line width of polySi and diffusion 2
drain and source have min. length and width of 2
And
PolySi extends in the gate region…

The polySi of the gate extends 2 beyond the gate area

on to the field oxide to prevent the drain and source from
shorting.

diffusion
short

• Diffusion Problems

no overlap overlap
Depletion Transistor
We need depletion implant

An implant surrounding the Transistor by 2

Ensures that no part of the transistor remains

in the enhancement mode

A separation of 2 from the gate of an

enhancement transistor avoids affecting 2

the device.
Depletion Transistor

Implants are separated by 2to prevent them from merging

2
Butting Contact

The gate and source of a depletion device can be connected

by a method known as butting contact. Here metal makes
contact to both the diffusion forming the source of the
depletion transistor and to the polySi forming this device’s
gate.

Advantage:
No buried contact mask required and avoids
associated processing.
Butting Contact
Problem: Metal descending the hole has a tendency to
fracture at the polySi corner, causing an open circuit.
Metal

Insulating
Oxide
n+ n+

Gate Oxide PolySi

Buried Contact

It is a preferred method. The buried contact window

defines the area where oxide is to be removed so that
polySi connects directly to diffusion.
Contact Area must be a min. of 2*2to ensure
adequate contact area.

2
Contact Area

2
Buried Contact

The buried contact window surrounds this contact by in all

directions to avoid any part of this area forming a transistor.

Separated from its related transistor gate by  to prevent gate

area from being reduced.


Buried Contact

Here gate length is depend upon the alignment of the

buried contact mask relative to the polySi and therefore
vary by .

PolySi
 2  Channel length 

Buried contact 2

Diffusion
Contact Cut
Metal connects to polySi/diffusion by contact cut.
Contact area: 22
Metal and polySi or diffusion must overlap this contact area
by so that the two desired conductors encompass the contact
area despite any mis-alignment between conducting layers
and the contact hole

4
Contact Cut
Contact cut – any gate: 2apart
Why? No contact to any part of the gate.

4

2
Contact Cut

Contact cut – contact cut: 2apart

Why? To prevent holes from merging.

2
Rules for CMOS layout
Similar to those for NMOS except No
1. Depletion implant
2. Buried contact

Additional rules
1. Definition of n-well area
2. Threshold implant of two types of transistor
3. Definition of source and drains regions for the
NMOS and PMOS.
Rules for CMOS layout

To ensure the separation of the PMOS and NMOS devices,

n-well supporting PMOS is 6away from the active
area of NMOS transistor.

Why?
Avoids overlap n+ n-well
6
of the associated
regions
Rules for CMOS layout

2

N-well must completely

surround the PMOS 2
device’s active area by 2
Rules for CMOS layout

2
The threshold implant
mask covers all n-well
2
and surrounds the n-well
by 
Rules for CMOS layout
The p+ diffusion mask
defines the areas to
2
receive a p+ diffusion.
It is coincident with the
threshold mask 2
surrounding the PMOS
transistor but excludes
the n-well region to be
connected to the supply.
Rules for CMOS layout
A p+ diffusion is required to effect the ground connection
to the substrate. Thus mask also defines this substrate
region. It surrounds the conducting material of this
contact by 

4
Rules for CMOS layout

Total contact area = 24

Neither NMOS nor CMOS usually allow contact cuts

to the gate of a transistor, because of the danger of
etching away part of the gate
Thank You