UNIT-2

MOS and Bi-CMOS Circuit Design Processes

 MOS Layers
• MOS design is aimed at turning a specification into
masks for processing silicon to meet the specification
• We have seen that MOS circuits are formed on four
basic layers which are isolated from one another by
thick or thin silicon dioxide insulating layers.
• They are 1.n‐diffusion
2.p‐diffusion
3.polysilicon
4.metal
• Thin oxide mask region includes n-diffusion / p-
diffusion and transistor channel
 Stick diagrams
• VLSI design aims to translate circuit concepts onto
silicon
• Stick diagrams are a means of capturing topography
(the arrangement of the natural and artificial features
of an area) and layer information using simple
diagrams.
• Stick diagrams may be used to convey layer
information through the use of a color code.
• Acts as an interface between symbolic circuit and the
actual layout.
• Does show all components/vias.Via is used to
connect higher level metals from metal connection
 Stick diagrams
Stick diagram shows relative placement of
components.
• Goes one step closer to the layout
• Helps plan the layout and routing
• A stick diagram is a cartoon of a layout.
Stick diagram Does not show
• Exact placement of components
• Transistor sizes
• Wire lengths, wire widths, tub boundaries
• Any other low level details such as parasitics
Encodings for NMOS process
Encodings for NMOS process
Encodings for CMOS process
Encodings for CMOS process
Encoding for BJT and MOSFETs
 Stick Diagrams Rules
Rule 1: When two or more ‘sticks’ of the same
type cross or touch each other that represents
electrical contact.

Rule 2:When two or more sticks of different type

cross or touch each other there is no electrical
contact.(If electrical contact is needed we have to
show the connection explicitly).
 Stick Diagrams Rules
Rule 3: When a poly crosses diffusion it represents a
transistor.
Note: If a contact is shown then it is not a transistor.

Rule 4:In CMOS a demarcation line is drawn to avoid

touching of p-diff with n-diff. All PMOS must lie on
one side of the line and all NMOS will have to be
on the other side.

Demarcation Line
STICK DIAGRAM OF INVERTER
SCHEMATIC AND LAYOUT OF INVERTER
 DESIGN RULES
Why we use design rules?
– Interface between designer and process engineer
• Historically, the process technology referred to the
length of the silicon channel between the source and
drain terminals in field effect transistors.
• The sizes of other features are generally derived as a
ratio of the channel length, where some may be
larger than the channel size and some smaller.
– For example, in a 90 nm process, the length of the
channel may be 90nm, but the width of the gate
terminal may be only 50 nm.
 DESIGN RULES
• Allow translation of circuits (usually in stick
diagram or symbolic form) into actual geometry in
silicon
• Interface between circuit designer and fabrication
engineer
• Circuit designer in general want tighter, smaller layouts
for improved performance and decreased silicon area.
• On the other hand, the process engineer wants design
rules that result in a controllable and reproducible
process.
• Generally we find there has to be a compromise for a
competitive circuit to be produced at a reasonable cost.
 DESIGN RULES
We have two types of Layout Design Rules:
1.Industry Standard: Micron Rule
2.λ Based Design Rules
• Design rules represents a tolerance which insures very
high probability of correct fabrication
– scalable design rules: lambda parameter
– absolute dimensions (micron rules)
Industry Standard: Micron Rule
• All device dimensions are expressed in terms of absolute
dimension(μm/nm). All minimum sizes and spacing
specified in microns.
• These rules will not support proportional scaling.
rules don't have to be multiples of λ
• Can result in 50% reduction in area over λ based rules
 Lambda-based Design Rules
• Lambda-based (scalable CMOS) design rules define
scalable rules based on λ (which is half of the minimum
channel length)
• Developed by Mead and Conway.
• All device dimensions are expresses in terms of a scalable
parameter λ.
• λ = L/2; L = The minimum feature size of transistor.L = 2 λ
• These rules support proportional scaling.
• They should be applied carefully in sub-micron CMOS
process.
• In MOS, the minimum feature size of Tr is:
• (L/W)n = 1/1 = 2 λ/2 λ
• Active area = L*W = 4 λ2
 Lambda-based Design Rules
• In CMOS, the minimum feature size of Tr is:
(L/W)n = 1/1.5 = 2 λ/3 λ Active area = L*W = 6 λ2
• Minimum length or width of a feature on a layer is 2λ. To
allow for shape contraction.
• Minimum separation of features on a layer is 2λ
Lambda-based Design Rules
Lambda-based Design Rules
Via and Contact Cut
 Interlayer Contacts
Interconnection between poly and diffusion is done by
contacts.
1.Metal contact--poly. to metal then metal to diff
2.Butting contact- poly. to diff. using metal
3.Buried contact- a buried contact poly. to diff
Butting Contact:
• The gate and source of a depletion device can be
connected by a method known as butting contact. Here
metal makes contact to both the diffusion forming the
source of the depletion transistor and to the polySi
forming this device’s gate.
• Advantage:No buried contact mask required and avoids
associated processing.
 Butting Contact

Problem: Metal descending the hole has a tendency to

fracture at the polySi corner, causing an open circuit.
Metal

Insulating
Oxide
n+ n+

Gate Oxide PolySi

 Buried Contact
Buried contact is the most widely used giving economy in space and
a reliable contact.

In buried contact basically, layers are joined over a 2λ. x 2λ. area
with the buried contact cut extending by 1λ, in all directions around
the contact area except that the contact cut extension is increased to 2λ.
in diffusion paths leaving the contact area.Here gate length is depend
upon the alignment of the buried contact mask relative to the polySi
and therefore vary by  as shown in figure below
Contacts poly-silicon to diffusion
Via and Contact Cut
Cross Section Showing of Via and Contact Cut
 CMOS Lambda-based Design Rules
• The CMOS fabrication process is more complex than nMOS
fabrication . In a CMOS process, there are nearly 100 actual set of
industrial design rules .The additional rules are concerned with those
features unique to p-well CMOS, such as the p-well and p+ mask and
the special 'substrate' contacts.

In the diagram above each of the arrangements can be merged into single
split contacts.
• P-well-P-plus mask- 
• P-well-Contact cut-3
• P-plus mask-Contact cut- 2
 CMOS Lambda-based Design Rules

From the above diagram it is also clear that split contacts may also be
made with separate cuts
 Particular rules for p-well CMOS Process
P-well and P+ Mask Rules

The CMOS rules are designed based on the extensions of the Mead and Conway
concepts and also by excluding the butting and buried contacts the new rules for
CMOS design are formed. These rules for CMOS design are implemented in the
above diagrams
 Double metal MOS process rules
• In the MOS design rules a powerful design process is
achieved by adding a second metal layer.This gives a much
greater degree of freedom, in distributing global VDDand
Vss(GND)rails in a system.
• From the overall chip inter-connection aspect, the second
metal layer in particular is important and, although the use of
such a layer is readily predict, its disposition relative to its
connection to other layers using metal1 to metal2 contacts,
called vias,can be readily established .
• Usually, second level metal layers are coarser(rough) than the
first (conventional) layer and the isolation layer between the
layers may also be of relatively greater thickness.
 Double metal MOS process rules
• To distinguish contacts between first and second metal
layers, they are known as vias rather than contact cuts.
The second metal layer representation is color coded
dark blue (or purple).
The important process steps for a two-metal layer process
• The oxide below the first metal layer is deposited by
atmospheric chemical vapor deposition (CVD) and the
oxide layer between the metal layers is applied in a
similar manner.
• Depending on the process, removal of selected areas of
the oxide is accomplished by plasma etching, which is
designed to have a high level of vertical ion
bombardment to allow for high and uniform etch rates.
• Similarly, the bulk of the process steps for a double polysilicon
layer process are similar in nature to those already described,
except that a second thin oxide layer is grown after depositing
and patterning the first polysilicon layer (Poly.1) to isolate it
from the now to be deposited second poly. layer (Poly.2).
• The presence of a second poly. layer gives greater flexibility in
interconnections and also allows Poly.2 transistors to be formed
by intersecting Poly. 2 and diffusion.
The important features of double metal process
• Uses the second level metal for the global distribution of power
buses, that is, VDD and GND ( Vss),and for clock lines.
• Use the first level metal for local distribution of power and for
signal lines.
• Lay out the two metal layers so that the conductors are mutually
orthogonal wherever possible.
General Observations on the Design Rules
 General Observations on the Design Rules
• The microscopic dimensions of Silicon circuits always cause
some problems in the design process.The major problem is
presented by possible deviation in line widths and in
interlayer registration. If the line widths are too small, it is
possible for lines to be discontinuous in places. If separate
paths in a layer are placed too close together, it is possible
that they will merge in places or interfere with each other.
• The consequence of using the lambda-based concept is that
every dimension must be rounded up to whole λ values and
this leads to layouts which do not fully exploit the
capabilities of the process.
• The establishment of 'micron-based' rule sets, but actual
dimensions are given so that full advantage can be taken of
the fabrication line capabilities and tighter layouts result.
• Layout rules, therefore, provide strict guidelines for
preparing the geometric layouts which will be used to
configure the actual masks used during fabrication and can
be regarded as the main communication link between
circuit/systems designers and the process engineers engaged
in manufacture.
• The goal of any set of design rules should give optimize
yield while keeping the geometry as small as possible
without compromising the reliability of the finished circuit.
• In our proposed scheme of events in creating stick layouts
for CMOS, it is assumed that poly. and metal can both
freely cross well boundaries and this is indeed the case, but
we should be careful to try to exclude poly. from areas
which lie within p+ mask areas where possible. The reason
for this is that the resistance of the poly.
 General Observations on the Design Rules
• The 3λ. metal width rule is a conservative one but is
implemented to allow for the fact that the metal layer is
deposited after the others and on top of them and
several layers of silicon dioxide, so that the surface on
which it sits is quite 'mountainous' . The metal layer is
also light-reflective and these factors combine to result
in poor edge definition.
• In double metal the second layer of metal has an even
more uneven terrain on which to be deposited and
patterned. Hence metal 2 is often wider than metal 1.
• Metal to metal separation is also large and is brought
about mainly by difficulties in defining metal edges
accurately during masking operations on the highly
reflective metal.
 General Observations on the Design Rules
• All diffusion processes are such that lateral diffusion
occurs as well as impurity penetration from the
surface. Hence the separation rules for diffusion
allow for this and relatively large separations are
specified. This is particularly the case for the p-well
diffusions which are deep diffusions and thus have
considerable lateral spread.
• Transitions from thin gate oxide to thick field oxide
in the oxidation process also use up space and this is
another reason why the lambda-based rules require a
minimum separation between thinox regions of 3λ. In
effect, this implies that the minimum feature size for
thick oxide is 3λ.
 General Observations on the Design Rules
• The simplicity of the lambda-based rules makes this
approach to design an appropriate one for the novice chip
designer and also, perhaps, for those applications in which
we are not trying to achieve the absolute minimum area and
the absolute maximum performance. Because lambda-based
rules try 'to be all things to all people', they do suffer from
least common denominator effects and from the upward
rounding of all process line dimension parameters into
integer values of lambda.
• In order to properly represent these important aspects,we
have Orbit Semiconductor ‘s 2µm feature size double
metal,double poly nmos,CMOS rules which also offer a
Bi-CMOS Capability
 2μm Double Metal,Double Poly,
CMOS/BiCMOS rules
• In order to accommodate the additional features in this
technology, it is necessary to extend the range of color and
monochrome encodings previously used for double metal
p-well cmos.
• The following extensions/additions are made
N.well-brown same as p-well
Poly1-red
Poly2-orange
N-diffusion(n –active)-Green
P-diffusion(p-active)-Yellow
For BiCMOS:Burried N-plus sub-collector-Pale Green
P-Base-Pink
2μm Double Metal,Double Poly,
CMOS/BiCMOS rules
2μm Double Metal,Double Poly,
CMOS/BiCMOS rules
2μm Double Metal,Double Poly,
CMOS/BiCMOS rules
2μm Double Metal,Double Poly,
CMOS/BiCMOS rules
2μm Double Metal,Double Poly,
CMOS/BiCMOS rules
2μm Double Metal,Double Poly,
CMOS/BiCMOS rules
1.2μm Double Metal,Double Poly,
CMOS/BiCMOS rules
1.2μm Double Metal,Double Poly, CMOS/BiCMOS rules
1.2μm Double Metal,Double Poly, CMOS/BiCMOS rules
1.2μm Double Metal,Double Poly, CMOS/BiCMOS rules
1.2μm Double Metal,Double Poly, CMOS/BiCMOS rules