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    Roba Multiplier: A Rounding-Based Approximate Multiplier For High-Speed Yet Energy-Efficient Digital Signal Processing

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    RatnakarVarun
    This document proposes a rounding-based approximate multiplier that can perform both signed and unsigned operations in a single design. Existing multipliers require separate designs for signed and unsigned, increasing area, power, and delay. The proposed multiplier aims to reduce these costs by supporting both data types in one implementation. It will be used to design FIR filters, with the goal of improving efficiency over traditional multipliers and common approaches like multiple constant multiplication.

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    Roba Multiplier: A Rounding-Based Approximate Multiplier For High-Speed Yet Energy-Efficient Digital Signal Processing

    Uploaded by

    RatnakarVarun
    96 views9 pages
    This document proposes a rounding-based approximate multiplier that can perform both signed and unsigned operations in a single design. Existing multipliers require separate designs for signed and unsigned, increasing area, power, and delay. The proposed multiplier aims to reduce these costs by supporting both data types in one implementation. It will be used to design FIR filters, with the goal of improving efficiency over traditional multipliers and common approaches like multiple constant multiplication.

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    This document proposes a rounding-based approximate multiplier that can perform both signed and unsigned operations in a single design. Existing multipliers require separate designs for signed and unsigned, increasing area, power, and delay. The proposed multiplier aims to reduce these costs by supporting both data types in one implementation. It will be used to design FIR filters, with the goal of improving efficiency over traditional multipliers and common approaches like multiple constant multiplication.

    Copyright:

    © All Rights Reserved
    Download as PPTX, PDF, TXT or read online from Scribd
    Download as pptx, pdf, or txt
    96 views9 pages

    Roba Multiplier: A Rounding-Based Approximate Multiplier For High-Speed Yet Energy-Efficient Digital Signal Processing

    Uploaded by

    RatnakarVarun
    This document proposes a rounding-based approximate multiplier that can perform both signed and unsigned operations in a single design. Existing multipliers require separate designs for signed and unsigned, increasing area, power, and delay. The proposed multiplier aims to reduce these costs by supporting both data types in one implementation. It will be used to design FIR filters, with the goal of improving efficiency over traditional multipliers and common approaches like multiple constant multiplication.

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    RoBA Multiplier: A Rounding-Based Approximate

    Multiplier for High-Speed yet Energy-Efficient Digital


    Signal Processing
    Abstract
    • In FIR filter designed, will used design any multipliers, if last frequent
    years, the MCM technique will used, as a proposed of FIR filter
    design, but the drawback is MCM technique will not work both thing
    of signed and un-signed operation, so it will we need to design
    separate MCM for signed and unsigned multiplication. So here, we
    are proposed a MCM with Rounded based approximate multiplier
    that includes both signed and unsigned operation in single multiplier,
    this multiplier will implemented in FIR Filter, and shown the efficiency
    of area, power and delay.
    Introduction
    • Multipliers are one the most important component of many systems. In high speed digital signal processing
    (DSP) and image processing multiplier play a vital role. Multipliers and adders are the key element of the
    arithmetic units as they lie in the critical path. With the recent advances in technology, many researchers
    have tried to implement increasingly efficient multiplier. They aim at offering low power consumption, high
    speed and reduced delay. Digital signal Processing (DSP) is finding its way into more applications , and its
    popularity has materialized into a number of commercial processors [18]. Digital signal processors have
    different architectures and features than general purpose processors, and the performance gains of these
    features largely determine the performance of the whole processor. Basic operation found in MAC is the
    binary addition. Besides of the simple addition of two numbers, addition forms the basis for many
    processing operations, from counting to multiplication to filtering. But also simpler operations like
    incrimination and magnitude comparison based on binary addition. Therefore, binary addition is the most
    important arithmetic operation. It comparison based on binary addition. It is also a very critical one if
    implemented in hardware because it involves an expensive carry-propagation step, the evaluation time of
    which is dependent on the operand word length.
    Block diagram
    Existing System:
    • Filter coefficients very often remain constant and known a priori in signal processing applications. This feature has been
    utilized to reduce the complexity of realization of multiplications. Several designs have been suggested by various
    researchers for efficient realization of FIR filters (having fixed coefficients) using distributed arithmetic (DA) and multiple
    constant multiplication (MCM) methods. DA-based designs use lookup tables (LUTs) to store pre computed results to
    reduce the computational complexity. The MCM method on the other hand reduces the number of additions required for
    the realization of multiplications by common sub expression sharing, when a given input is multiplied with a set of
    constants. The MCM scheme is more effective, when a common operand is multiplied with more number of constants.
    Therefore, the MCM scheme is suitable for the implementation of large order FIR filters with fixed coefficients. But, MCM
    blocks can be formed only in the transpose form configuration of FIR filters.
    • Block-processing method is popularly used to derive high-throughput hardware structures. It not only provides
    throughput-scalable design but also improves the area-delay efficiency. The derivation of block-based FIR structure is
    straightforward when direct-form configuration is used [16], whereas the transpose form configuration does not directly
    support block processing. But, to take the computational advantage of the MCM, FIR filter is required to be realized by
    transpose form configuration. Apart from that, transpose form structures are inherently pipelined and supposed to offer
    higher operating frequency to support higher sampling rate.
    Disadvantages:
    • Separate Multiplier design for Signed and Unsigned Operation
    • More logic size
    • More Power and delay
    Proposed System:
    • Finite Impulse response (FIR) digital filter is widely used in several digital signal processing application, such as speech
    processing, loud speaker equalization, echo cancellation, adaptive noise cancellation, and various communication
    application, including software-define radio (SDR) and so on. Many of these application require FIR filter of large order to
    meet the stringent frequency specification. Very often these filters need to support high sampling rate for high-speed
    digital communication. The number of multiplication and additions required for each filter output, however, increases
    linearly with the filter order. Since there is no redundant computation available in the FIR filter algorithm, real-time
    implementation of a large order FIR filter in a resource constrained environment is a challenging task. Filter coefficients
    very often remain constant and known a priori in signal processing application. This feature has been utilized to reduced
    the complexity of realization of multiplications.
    • In FIR filter designed, will used design any multipliers, if last frequent years, the MCM technique will used, as a proposed
    of FIR filter design, but the drawback is MCM technique will not work both thing of signed and un-signed operation, so it
    will we need to design separate MCM for signed and unsigned multiplication. So here, we are proposed a MCM with
    Rounded based approximate multiplier that includes both signed and unsigned operation in single multiplier, this
    multiplier will implemented in FIR Filter, and shown the efficiency of area, power and delay.
    Advantages:
    • Common Multiplier design for Signed and Unsigned Operation
    • Less Logic size
    • Less Power and delay
    Software
    • Xilinx ise 14.5
    • Vhdl / Verilog

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