CMOS Inverter: Ankur R Changela
CMOS Inverter: Ankur R Changela
CMOS Inverter: Ankur R Changela
Ankur R Changela
Chapter Outline
• Basic Concept of a CMOS inverter
• Power Dissipation
Dynamic Power
Static Power
• The Static Behavior of the CMOS inverter
Switching Threshold
Noise Margins
• The Dynamic Behavior of the CMOS inverter
Propagation Delay: First order Analysis
Propagation Delay: Design Perspective
Basic Inverter Concept
Resistive Load Inverter
Disadvantages:
•Rise Time
•Power Dissipation across RL
The CMOS Inverter: A First Glance
V DD
V in V out
CL
CMOS Inverter
N Well VDD
VDD PMOS 2l
Contacts
PMOS
In Out
In Out
Metal 1
Polysilicon
NMOS
NMOS
GND
Two Inverters
Share power and ground
VDD
Connect in Metal
CMOS Inverter
FirstOrder DC Analysis
V DD V DD
Rp VOL = 0
VOH = VDD
VM = f(Rn, Rp)
V out
V out
Rn
V in = V DD V in = 0
CMOS Inverter: Transient Response
V DD V DD
Rp tpHL = f(R on .C L )
= 0.69 R on C L
V out
V out
C L C L
Rn
V in 5 0 V in 5 V DD
(a) Low-to-high (b) High-to-low
Voltage Transfer
Characteristic
PMOS Load Lines
I Dn
V in = V DD +V GSp
I Dn = - I Dp
V out = V DD +V DSp
V out
I Dp IDn I Dn
V in =0 V in =0
V in =1.5 V in =1.5
V GSp =-2.5
V in = V DD +V GSp V out = V DD +V DSp
I Dn = - I Dp
CMOS Inverter Load Characteristics
ID n
Vin = 0 Vin = 2.5
Vout
CMOS Inverter VTC
Vout NMOSoff
PMOSres
2.5
NMOSsat
0.5 1 1.5 2 PMOSres
NMOSsat
PMOS sat
NMOSres
PMOS sat NMOSres
PMOSoff
0 .5 1 1 .5 2 2 .5 Vin
Sources Of Power Dissipation
• Switching Power(Due to transitions) Dynamic Power
“nodes” in digital CMOS circuit transition back and forth between the logic levels and due to
this capacitance associated with the nodes get charged and discharged.
Due to Glitches
As input change, voltage at node may change to 0 and in this case stored charge at that
particular node has to be discharged and electric energy will be converted into heat energy.
• Due to Short Circuit Current
Short Circuit Current flows directly from the supply to the ground terminal when the pull up
(psubnetwork) and pull down(nsubnetwork) networks conduct simultaneously.
Due to rise and fall time of the input
Static Power
• Leakage Current
Leakage current flows when Input(s) to gate are not changing and therefore output(s) are not
changing.
Dynamic Dissipation
Switching Power:
VDD
ic(t)
vi (t) vo(t)
CL
Ground
Dynamic Dissipation
Switching Power:
Power Dissipated per transition is given by, Power Dissipated to charge the CL is given by,
1 1
PT I (t )VDDdt PC I (t )Voutdt
T 0 T 0
VDD dVout 1 dVout
C L dt CL Voutdt
T 0 dt T 0 dt
VDD VDD
VDDCL CL
T dV
0
out
T V
0
dVout
out
T
Suppose there are Ns out of N transitions are going to dissipate power then total power dissipated
is given by,
Switching Power can be reduced
• By scaling down the supply voltage(VDD) but to maintain
the high performance threshold voltage has to be scaled
down which leads to high leakage current.
= Switching Factor • By reducing switching activity( )
= Frequency of operation
Switching Factor
a b Out
Pa=probability that input a is high=0.5 0 0 0
Pb=probability that input b ish igh=0.5
0 1 0
Now, Out will be high when both input go high
Pout=probability that output is high =PaPb=0.25 1 0 0
1 1 1
Dynamic power will be dissipated when output is zero and
it goes high and probability of this transition is given by , Truth table of AND Gate
=P0P1=PaPb(1PaPb)
Gate α
OR (1Pa)(1Pb)(1(1Pa)(1Pb))
XOR [1(Pa+Pb2PaPb)][Pa+Pb2PaPb]
Input Ordering
(10.5x0.2)*(0.5x0.2)=0.09 (10.2x0.1)*(0.2x0.1)=0.0196
0.5 0.2
A B X
X
B C
F 0.1 A F
0.2 C
0.1 0.5
(10.5x0.02)*(0.5x0.02)=0.0198
(10.09x0.1)*(0.09x0.1)=0.0819
AND: P01 = (1 PAPB) * PAPB
AND: P01 = P0 * P1 = (1 PAPB) * PAPB
3/16
0.5 A Y
0.5 (10.25)*0.25 = 3/16
A 15/256
W 7/64 = 0.109 0.5 B
B X F
15/256 0.5
0.5 C C
0.5 D F
0.5 0.5 D Z
3/16 = 0.188
Chain implementation has a lower overall switching activity than tree
implementation for random inputs
BUT: Ignores glitching effects
Dynamic Dissipation
Short Circuit Power Dissipation:
VDD
isc(t)
vi (t) vo(t)
CL
Ground
• Short Circuit current flows from VDD to ground when both PMOS and NMOS networks are on simultaneously
• Power will be dissipated across both on resistor of NMOS and PMOS.
Dynamic Dissipation
Short Circuit Power Dissipation:
• When VTn Vin VDD VTp , both NMOS and
PMOS subnetwork are on and current flows
from VDD to GND
•The Short Circuit Power is given by,
ImeanVDD
•For Simplicity, a symmetrical inverter (i.e.
βN= βP and VTn=VTp) and a symmetrical input
signal (i.e. rise time = fall time) are
considered.
•As, for the NMOS if VDS>VGSVTn MOSFET
will be in saturation
Leakage Power
VDD • A reverse bias PN junction leakage
Ground IG • Subthreshold Leakage
Gate
• Gate oxide leakage
Source Drain
• Gate Induced drain leakage
n+ Isub n+
• Channel Punch through current
IPT
Bulk Si (p) I ID
GIDL
nMOS Transistor
Static Leakage
• A reverse bias PN junction leakage
Minority carrier drift /diffusion current near the edge of depletion region.
Electron hole pair generation in the depletion region.
Significant effect if n and p regions are heavily doped.
• Subthreshold Leakage
Due to weak inversion layer.
Current flow is due to minority carrier.
Isub = μ0 Cox (W/L) Vt2 exp{(VGS –VTH ) / nVt }
Static Leakage
• Gate oxide leakage
Smaller gate oxide thickness results in increase in electric field across oxide(as E=V/d) and this results in
electron tunneling from substrate to gate and vice versa.
Local electric field is perpendicular to gate known as direct tunneling.
Local electric field is parallel to gate oxide known as Hot carrier injection
Majority current is due to electron as effective weight of electron is lower than hole.
• Gate Induced drain leakage
Gateinduced drain leakage (GIDL) is caused by high field effect in the drain junction of MOS transistors.
When the gate is biased zero or negative voltage, It attracts hole from the substrate at the gate surface and it
acts like heavily doped P type region compare to substrate which results narrowing the depletion region at
the surface and due to this very high electric field will be generated near the surface area.
• Channel Punch through current
When reverse bias across the junction is increased, distance between depletion regions of drainsubstrate and
source substrate also gets decreased.
When this two regions gets merged, channel punch through is said to be occurred
Significant in short channel and heavily doped device.