Designing Combinational

Logic Circuits

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Combinational vs. Sequential Logic

Combinational Sequential

Output = f(In) Output = f(In, Previous In)

Static CMOS Circuit
At every point in time (except during the switching
transients) each gate output is connected to either
VDD or Vss via a low-resistive path.
The outputs of the gates assume at all times the value
of the Boolean function, implemented by the circuit
(ignoring, once again, the transient effects during
switching periods).
This is in contrast to the dynamic circuit class, which
relies on temporary storage of signal values on the
capacitance of high impedance circuit nodes.

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CMOS Circuit Styles
‰ Static complementary CMOS - except during switching,
output connected to either VDD or GND via a low-
resistance path
λ high noise margins
- full rail to rail swing
- VOH and VOL are at VDD and GND, respectively
λ low output impedance, high input impedance
λ no steady state path between VDD and GND (no static power
consumption)
λ delay a function of load capacitance and transistor resistance
λ comparable rise and fall times (under the appropriate transistor
sizing conditions)

‰ Dynamic CMOS - relies on temporary storage of signal

values on the capacitance of high-impedance circuit
nodes
λ simpler, faster gates
λ increased sensitivity to noise
Static Complementary CMOS
‰ Pull-up network (PUN) and pull-down network (PDN)
VDD
PMOS transistors only
In1
pull-up: make a connection from VDD to F
In2 PUN
…
when F(In1,In2,…InN) = 1
InN
F(In1,In2,…InN)
In1
pull-down: make a connection from F to
In2 PDN
…

GND when F(In1,In2,…InN) = 0

InN
NMOS transistors only

PUN and PDN are dual logic networks

One and only one of the networks is conducting in steady state
Threshold Drops

VDD VDD
PUN

VDD

0→ 0→

CL CL

PDN VDD → VDD →

CL CL
VDD
Threshold Drops

VDD VDD
PUN
S D
VDD

D 0 → VDD S 0 → VDD - VTn

VGS
CL CL

PDN VDD → 0 VDD → |VTp|

VGS
D CL S CL
VDD

S D
NMOS Transistors
in Series/Parallel Connection
Transistors can be thought as a switch controlled by its gate signal
NMOS switch closes when switch control input is high
A B

X Y Y = X if A and B

X B Y = X if A OR B
Y

NMOS Transistors pass a “strong” 0 but a “weak” 1

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PMOS Transistors
in Series/Parallel Connection
PMOS switch closes when switch control input is low

A B

X Y Y = X if A AND B = A + B

X B Y = X if A OR B = AB
Y

PMOS Transistors pass a “strong” 1 but a “weak” 0

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Construction of PDN
‰ NMOS devices in series implement a NAND function

A•B
A

‰ NMOS devices in parallel implement a NOR function

A+B
A B
Dual PUN and PDN
‰ PUN and PDN are dual networks
λ DeMorgan’s theorems

A+B=A•B
A•B=A+B

λ a parallel connection of transistors in the PUN corresponds to a

series connection of the PDN

‰ Complementary gate is naturally inverting (NAND,

NOR, XNOR)
‰ Number of transistors for an N-input logic gate is 2N
Complementary CMOS Logic Style
PUN
CMOS NAND

VDD
A B F
0 0 1
A B
0 1 1
1 0 1
A•B
1 1 0
A

A
B
CMOS NOR

VDD
A B F
B
0 0 1
A 0 1 0
1 0 0
A+B
1 1 0
A B

A
B
Complex CMOS Gate

F=D+A•(B+C)
A
D
B C
Complex CMOS Gate
VDD

B
A
C
SN4
D
SN1
OUT=D+A•(B+C)
A
D SN2
B C SN3
VTC is Data-Dependent
VDD 0.5µ/0.25µ NMOS
3
0.75µ /0.25µ PMOS

A M3 B M4
2 A,B: 0 -> 1
B=1, A:0 -> 1
F= A • B A=1, B:0->1
D weaker
A M2 1 PUN
S
VGS2 = VA –VDS1 D
Cint
B M1
S 0
VGS1 = VB
0 1 2

‰ The threshold voltage of M2 is higher than M1 due to the

body effect (γ)
VTn1 = VTn0
VTn2 = VTn0 + γ(√(|2φF| + Vint) - √|2φF|)
since VSB of M2 is not zero (when VB = 0) due to the presence of Cint
 Switch Delay Model
A Req
A

Rp
Rp Rp
B
A B Rp
A Rp Cint
Rn CL A
A Rn CL
A Rn Rn CL
Rn
Cint
A B
B
NOR2
NAND2 INV
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 Input Pattern Effects on Delay

‰ Delay is dependent on
Rp Rp the pattern of inputs
A B ‰ Low to high transition
ƒ both inputs go low
Rn CL – delay is 0.69 (Rp/2) CL
A ƒ one input goes low
– delay is 0.69 Rp CL
Rn
Cint ‰ High to low transition
B
ƒ both inputs go high
– delay is 0.69 2Rn CL

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Adding devices in series slows down the circuit, and devices
must be made wider to avoid performance penalty.
When sizing the transistors in a gate with multiple inputs,
we should pick the combination of inputs that triggers the
worst case conditions.
For the NAND gate to have the same pull-down delay (tphl)
with an inverter, the NMOS devices in the PDN stack must
be made twice as wide (2.5 times, if velocity saturation is
effective). PMOS devices can remain unchanged.
(Extra capacitance introduced by widening is ignored here,
which is not a good assumption)
 Delay Dependence on Input Patterns
NAND Gate
3
Input Data Delay
2.5 A=B=1→0
Pattern (psec)
2 A=B=0→1 69
A=1 →0, B=1
A=1, B=0→1 62
Voltage [V]

1.5

1 A=1, B=1→0 A= 0→1, B=1 50

0.5 A=B=1→0 35

0 A=1, B=1→0 76
0 100 200 300 400
-0.5 A= 1→0, B=1 57

time [ps] NMOS = 0.5µm/0.25 µm

PMOS = 0.75µm/0.25 µm
CL = 100 fF 30
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 Transistor Sizing

Rp Rp Rp
2 A B 2 4 B

Rn Rp Cint
CL 4
2 A
B

Rn Rn Rn CL
2 Cint
1
A A B 1

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 Transistor Sizing a Complex
CMOS Gate
B 8 6
A 4 3
C 8 6

D 4 6
OUT = D + A • (B + C)
A 2
D 1
B 2C 2

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 Fan-In Considerations

A B C D
Distributed RC model
A CL (Elmore delay), assuming all
NMOS devices of equal size
B C3
C tpHL = 0.69 Reqn(C1+2C2+3C3+4CL)
C2
D C1 Propagation delay deteriorates
rapidly as a function of fan-in –
quadratically in the worst case.

t pHL = 0.69 [ R1C1 + ( R1 + R2 )C2 + ( R1 + R2 + R3 )C3 + ( R1 + R2 + R3 + R4 )CL ]

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 tp of CMOS NAND as a Function of Fan-In
(Assuming a fixed fan out of one inverter)
1250
quadratic
1000

Gates with a
750
fan-in
tp (psec)

tpHL tp greater than

500
4 should be
250 ttpLH avoided.
pLH
linear
0
2 4 6 8 10 12 14 16

fan-in

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 tp as a Function of Fan-Out

All gates
tpNOR2 tpNAND2 have the
same drive
tpINV current.
tp (psec)

Slope is a
function of
“driving
strength”
2 4 6 8 10 12 14 16
eff. fan-out

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tp as a Function of Fan-In and Fan-Out

‰ Fan-in: quadratic due to increasing

resistance and capacitance
‰ Fan-out: each additional fan-out gate
adds two gate capacitances to CL

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 Fast Complex Gates:
Design Technique 1
‰ Transistor sizing
ƒ as long as fan-out capacitance dominates
‰ Progressive sizing
Distributed RC line
InN MN CL
M1 > M2 > M3 > … > MN
(the fet closest to the
In3 M3 C3 output is the smallest)

In2 M2 C2 Can reduce delay by more than

In1 M1
20%; decreasing gains as
C1
technology shrinks
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 Fast Complex Gates: Design Technique 2
‰ Transistor ordering
An input signal is called “critical” if it is the last signal to
assume a stable value, the path which determines the
ultimate speed is called “critical path”

critical path critical path

charged 0→1
In3 1 M3 CL In1 M3 CLcharged

In2 1 M2 In2 1 M2 C2 discharged

C2 charged
In1 In3 1 M1 C1 discharged
M1 C1 charged
0→1

delay determined by time to delay determined by time to

discharge CL, C1 and C2 discharge CL
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 Fast Complex Gates:
Design Technique 3
‰ Alternative logic structures
F = ABCDEFGH

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 Fast Complex Gates:
Design Technique 4
‰ Isolating fan-in from fan-out using buffer
insertion

CL CL

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 Logical Effort
tp = tp0 (1 + Cext/ γCg) = tp0 (1 + f/γ)
tp =tp0 (p + gf/γ)
p – ratio of the intrinsic (unloaded delays of the complex gate
and the simple inverter
g – logical effort – how much more input capacitance a gate
presents to deliver the same output current as an inverter
(how much worse it is at producing output current than an
inverter)
f – effective fanout (Cext/Cg) (electrical effort)

Normalize everything to an inverter: ginv =1, pinv = 1

P = n for n input NAND and NOR gates
Assume γ = 1.
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 Logical Effort

‰ Inverter has the smallest logical effort and

intrinsic delay of all static CMOS gates
‰ Logical effort of a gate presents the ratio of its
input capacitance to the inverter capacitance
when sized to deliver the same current
‰ Logical effort increases with the gate
complexity

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 Delay in a Logic Gate
Gate delay:
d=h+p
effort delay intrinsic delay
Effort delay (gate effort):
h=gf

logical effective fanout = Cout/Cin

effort
Logical effort is a function of topology, independent of sizing
Effective fanout (electrical effort) is a function of load/gate size
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 Logical Effort
Assuming PMOS/NMOS ratio of 2, the input capacitance of a minimum
sized symmetrical inverter equals 3 times the gate capacitance of a
minimum sized NMOS (called Cunit)

g=1 g = 4/3 g = 5/3

(3 Cunit) (4 Cunit) (5 Cunit)
Intrinsic Delay Term, p
‰ The more involved the structure of the complex gate, the
higher the intrinsic delay compared to an inverter

Gate Type p
Inverter 1
n-input NAND n
n-input NOR n
n-way mux 2n
XOR, XNOR n 2n-1

Ignoring second order

effects such as internal
node capacitances
 Logical Effort

For the same input capacitance, 2 input NAND and NOR

gates have 4/3 and 5/3 less driving strength than the inverter

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 Logical Effort of Gates

Normalized delay (d)

t pNAND
g = 4/3 t pINV
p=2
d = (4/3)f+2
g=1
p=1
d = f+1
3
2
1

1 2 3 4 5 6 7
Fan-out (f)

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 Delay as a Function of Fan-Out
2 • The slope of the line is
= the logical effort of the
, p
7 4/3 gate (d = p + fg)
g=
2 : • The y-axis intercept is
6
N D p =1
, the intrinsic delay
normalized delay

A 1
5 N : g=
INV
4 • Can adjust the delay by
adjusting the effective
3
effort delay fan-out (by sizing) or by
2
choosing a gate with a
1
intrinsic delay different logical effort
0 • Gate effort: h = fg
0 1 2 3 4 5
fan-out f
 Multistage Networks
N N
⎛ fjgj ⎞
Total delay of a path: t p = ∑ t p, j = t p0 ∑ ⎜ p j + ⎟
j =1 j =1 ⎝ γ ⎠

Using a similar procedure with the sizing of the inverter chain

(finding N-1 partial derivatives and equating to zero), we find
that each stage should bear the same gate effort:
f1g1=f2g2=...=fNgN
Here we have some definitions:
Path effective fan-out (Path electrical effort): F = CL/Cg1
N
Path logical effort: G = g1g2…gN G = ∏ gi
1

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 Branching effort of a logical gate on a path:
Con − path + Coff − path
b=
Con − path
N
Path branching effort: B = ∏ bi
1

The path electrical effort can now be related to the

electrical and branching efforts:

fi ∏ fi
N
F =∏ =
1 bi B

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Finally the total path effort H can be defined:

N N
H = ∏ hi =∏ gi fi = GFB
1 1

From here on, the analysis can be carried out as in the case
of inverter chain. The gate effort that minimizes the path
delay is:
h= H N

And the minimum delay through the path is:

⎛ N
D = t p0 ⎜ ∑ p j +
(
N NH ⎞
⎟
)
⎜ j =1 γ ⎟
⎝ ⎠
We assume that a unit-size gate has a driving capability equal
to a minimum-size inverter. This means that its input
capacitance is g times larger than that of the reference inverter
(Cref). With s1 the sizing factor of the first gate in the chain, the
input capacitance of the chain can be written as:
Cg1 = g1s1Cref
Including the branching effort, the input capacitance of gate 2
will be f1/b1 times larger:

⎛ f1 ⎞
g 2 s2Cref = ⎜ ⎟ g1s1Cref For gate i in the chain:
⎝ b1 ⎠
⎛ g1s1 ⎞ i −1 ⎛ f j ⎞
si = ⎜ ⎟ ∏ ⎜⎜ ⎟⎟
⎝ gi ⎠ j =1 ⎝ b j ⎠
 Example: Optimize Path
1 b c
a
5
g=1 g = 5/3 g = 5/3 g=1

Effective fanout, F = 5
G = 1x(5/3)x(5/3)x1 = 25/9
H = GFB (no branching)=125/9 = 13.9
h = 4 H = 1.93
since f1g1=f2g2=f3g3=f4g4 = h:
f1=1.93, f2=1.93x(3/5)=1.16, f3=1.16, f4=1.93
a = s2 = f1g1/g2 = 1.16
b = s3 = f1f2g1/g3 = 1.34
c = s4 = f1f2f3g1/g4 = 2.60
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 Path Logical Effort Variation With Restructuring
(8 – input AND)

G=3.33 G=3.33 G=2.96

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Dynamic Power Consumption is Data Dependent
‰ Switching activity, P0→1, has two components
λ A static component – function of the logic topology
λ A dynamic component – function of the timing behavior (glitching)
Pdyn = C LV D2D f 0 → 1 = C LV D2D P0 → 1 f = C E F F V D2D f

Static transition probability

2-input NOR Gate P0→1 = Pout=0 x Pout=1
A B Out = P0 x (1-P0)
0 0 1
With input signal probabilities
0 1 0
PA=1 = 1/2
1 0 0 PB=1 = 1/2
1 1 0
NOR static transition probability
= 3/4 x 1/4 = 3/16
N0 and N1 are the number of zero and number of one entries
in the output column of the truth table of the function.
Assuming that the N inputs are independent and uniformly
distributed (the four possible states are equally likely):

N 0 N1 N0 ( 2N − N0 )
P0→1 = N N = 2N
2 2 2
NOR Gate Transition Probabilities
‰ Switching activity is a strong function of the input signal
statistics
λ PA and PB are the probabilities that inputs A and B are one

0
A B
CL PA
1 0 1
PB

P1 = (1-PA)(1-PB)
P0→1 = P0 x P1 = (1-(1-PA)(1-PB)) (1-PA)(1-PB)
Transition Probabilities for Some Basic Gates

P0→1 = Pout=0 x Pout=1

NOR (1 - (1 - PA)(1 - PB)) x (1 - PA)(1 - PB)
OR (1 - PA)(1 - PB) x (1 - (1 - PA)(1 - PB))
NAND PAPB x (1 - PAPB)
AND (1 - PAPB) x PAPB
XOR (1 - (PA + PB- 2PAPB)) x (PA + PB- 2PAPB)
X
0.5 A
Z
0.5 B

For X: P0→1 = P0 x P1 = (1-PA) PA

= 0.5 x 0.5 = 0.25
For Z: P0→1 = P0 x P1 = (1-PXPB) PXPB
= (1 – (0.5 x 0.5)) x (0.5 x 0.5) = 3/16
Inter-signal Correlations
‰ Determining switching activity is complicated by the fact
that signals exhibit correlation in space and time
If B is not connected to A: P(Z=1) = P(B=1,C=1)=1/4

A C

B Z

Reconvergent fan-out

P(Z=1) = P(C=1)|B=1) & P(B=1) = 0

‰ Have to use conditional probabilities

Glitching in a chain of NAND gates
Balanced Delay Paths to Reduce Glitching
‰ Glitching is due to a mismatch in the path lengths in
the logic network; if all input signals of a gate change
simultaneously, no glitching occurs

0 0
0 F1 1 0 F1 1
0 F2 2
F3
0 F3 0
0 F2 1

So equalize the lengths of timing paths through logic

 Logic Restructuring
‰ Logic restructuring: changing the topology of a logic
network to reduce transitions
AND: P0→1 = P0 x P1 = (1 - PAPB) x PAPB
3/16
0.5 A Y
0.5 (1-0.25)*0.25 = 3/16
A W 7/64 0.5 B 15/256
B X F
15/256 0.5
0.5 C C
0.5 D F
0.5 0.5 D Z
3/16

Chain implementation has a lower overall switching activity

than the tree implementation for random inputs
Ignores glitching effects
Input Ordering

PX = PX =
(1-0.5x0.2)x(0.5x0.2)=0.09 (1-0.2x0.1)x(0.2x0.1)=0.0196
0.5 0.2
A B X
X
B C
F 0.1 A F
0.2 C
0.1 0.5

Beneficial to postpone the introduction of signals with a

high transition rate (signals with signal probability
close to 0.5)
Ratioed Logic

VDD VDD VDD

Resistive Depletion PMOS

Load RL Load VT < 0 Load
VSS
F F F
In1 In1 In1
In2 PDN In2 PDN In2 PDN
In3 In3 In3

VSS VSS VSS

(a) resistive load (b) depletion load NMOS (c) pseudo-NMOS

Nominal VOH = VDD but nominal VOL ≠ 0

Goal: to reduce the number of devices over complementary CMOS

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Ratioed Logic
VDD

• N transistors + Load
Resistive
Load • VOH = V DD
RL

• VOL = RPN
VDD
F RPN + RL

In1 • Assymetrical response

In2 PDN
In3 • Static power consumption

• tpL= 0.69 RLCL

VSS

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 Pseudo-NMOS
Pseudo-NMOS NOR Gate

Smaller area & Load but

Static power dissipation!!!

To obtain VOL, equate the currents at load (PMOS) and driver

(NMOS), when Vin = VDD It is reasonamble to assume NMOS at
linear (output should be close to 0V), PMOS at saturation
VGS VDS VGS
⎛ V 2OL ⎞ ⎛ V 2 DSATp ⎞
kn ⎜ (VDD − VTn ) VOL − ⎟ + k p ⎜⎜ ( −VDD − VTp ) VDSATp − ⎟⎟ = 0
⎝ 2 ⎠ ⎝ 2 ⎠
Assuming that VOL << (VDD-VT), VDSATp << (VDD-VT)
and |VTn| = |VTp|

k p (VDD + VTp )VDSATp µ pW p

VOL ≈ ≈ VDSATp
kn (VDD − VTn ) µ nWn

In order to make VOL small, PMOS must be sized much smaller

than NMOS. But this has negative effecton the propagation
delay. Amajor disadvantage of the psuedo-NMOS is the static
power dissipation when the output is low

⎛ V 2 DSATp ⎞
Pstatic = VDD I low ≈ VDD k p ⎜ ( −VDD − VTp ) VDSATp − ⎟⎟
⎜ 2
⎝ ⎠
 W/Lp VoL P (µW) tplh(ps)

Pseudo-NMOS VTC
4 0.69 564 14
2 0.27 298 56
1 0.13 160 123
INVERTER
0.5 0.06 80 268
0.25 0.03 41 569
3.0

2.5

2.0 W/Lp = 4

1.5
Vout [V]

W/Lp = 2
1.0

W/Lp = 0.5 W/Lp = 1

0.5

W/Lp = 0.25
0.0
0.0 0.5 1.0 1.5 2.0 2.5
Vin [V]

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Improved Loads (2)
VDD VDD

ON OFF
M1 M2
OFF ON

Out 1
0
Out
0 1
A
OFF A ON
B PDN1 PDN2
ON B OFF

VSS VSS

Differential Cascode Voltage Switch Logic (DCVSL)

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DCVSL Example
VDD

Out

Out

B B B B

A A
Out = AB+A’B’
Out’ = AB’+A’B

XOR-NXOR gate
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NMOS Transistors in Series/Parallel

‰ Primary inputs drive both gate and source/drain

terminals
‰ NMOS switch closes when the gate input is high

A B
X = Y if A and B
X Y
A

B X = Y if A or B
X Y

‰ Remember - NMOS transistors pass a strong 0 but a

weak 1
PMOS Transistors in Series/Parallel

‰ Primary inputs drive both gate and source/drain

terminals
‰ PMOS switch closes when the gate input is low
A B
X = Y if A and B = A + B
X Y
A

B X = Y if A or B = A • B
X Y

‰ Remember - PMOS transistors pass a strong 1 but a

weak 0
Pass-Transistor Logic

Switch Out A
Out
Inputs

Network B
B

• N transistors
• No static consumption

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 Example: AND Gate

Requires 4 transistors (including the inverter for B’)

AND function requires 6 transistors in CMOS (NAND-INVERT)
Pass Transistor (PT) Logic

B
B
A A
F=A•B B
B
0 F=A•B
0

‰ Gate is static – a low-impedance path exists to both

supply rails under all circumstances
‰ N transistors instead of 2N
‰ No static power consumption
‰ Ratioless
‰ Bidirectional (versus undirectional)
NMOS Only PT Driving an Inverter

In = VDD
Vx = M2
VGS
A = VDD VDD-VTn
D S
B M1

‰ Vx does not pull up to VDD, but VDD – VTn

‰ Threshold voltage drop causes static power

consumption (M2 may be weakly conducting forming a
path from VDD to GND)
‰ Notice VTn increases of pass transistor due to body
effect (VSB)
Voltage Swing of PT Driving an Inverter

3
In
In = 0 → VDD
1.5/0.25 2
x = 1.8V

Voltage, V
x
S
D
VDD Out
0.5/0.25
1
B 0.5/0.25
Out
0
0 0.5 1 1.5 2
Time, ns

‰ Body effect – large VSB at x - when pulling high (B is

tied to GND and S charged up close to VDD)
‰ So the voltage drop is even worse
Vx = VDD - (VTn0 + γ(√(|2φf| + Vx) - √|2φf|))
 Cascaded NMOS Only PTs

B = VDD B = VDD C = VDD

G
M1 x M2 y Out
M1 A = VDD
A = VDD x = VDD - VTn1
S
G
M2 y Out
C = VDD
S

Swing on y = VDD - VTn1 - VTn2 Swing on y = VDD – VTn2

λ Pass transistor gates should never be cascaded as on

the left
λ Logic on the right suffers from static power dissipation
and reduced noise margins
 VTC of the pass transistor AND gate

Assuming VM (of the inverter) = VDD/2

Pure pass-transistor gate is not regenerative
Differential PT Logic (CPL)
A
A PT Network
B F
B
F

A
A Inverse PT F
B Network F
B

B B B B B B

A A A

B F=AB B F=A+B A F=A⊕B

A A A
F=AB F=A+B F=A⊕B
B B A
AND/NAND OR/NOR XOR/XNOR
 4-input AND/NAND gate in CPL

1
4 3 12 11 7 8
2

9
3
2 6 4 10
5
1 10 9 5 11
6 12

7
8
 LEVEL RESTORATION

When A goes high, all nodes are either 0 or VDD. To pull node
X down, Mn need to be stronger than Mr. That requires careful
transistor sizing (if Rr is too small with respect to Rn, it is
impossible to bring Vx below the switching treshold of the
inverter).
 Transmission Gates (TGs)
‰ Most widely used
C C
solution for level
restoration A B
A B C

C = GND C = GND

A = VDD B A = GND B

C = VDD C = VDD

‰ Full swing bidirectional switch controlled by the gate

signal C, A = B if C = 1
Transmission gate 2-input inverting multiplexer

= (AS + BS′)′
Trannsmission gate XOR

F = A′B + AB′
CPL Properties

‰ Differential so complementary data inputs and outputs

are always available (so don’t need extra inverters)
‰ Still static, since the output defining nodes are always
tied to VDD or GND through a low resistance path
‰ Design is modular; all gates use the same topology, only
the inputs are permuted.
‰ Simple XOR makes it attractive for structures like adders
‰ Fast (assuming number of transistors in series is small)
‰ Additional routing overhead for complementary signals
‰ Still have static power dissipation problems