VLSI DESIGN

COMBINATIONAL MOS
LOGIC CIRCUITS

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COMBINATIONAL VS. SEQUENTIAL LOGIC

In Out
Combinational Combinational
In Logic Out Logic
Circuit Circuit

State

Combinational Sequential

Output = f(In ) Output = f (In, Previous In)

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STATIC CMOS CIRCUIT

At every point in time (except during the switching

transients) each gate output is connected to either
VDD or Vss via a low-resistive path.
The outputs of the gates assume at all times the value
of the Boolean function, implemented by the circuit
(ignoring, once again, the transient effects during
switching periods).
This is in contrast to the dynamic circuit class, which
relies on temporary storage of signal values on the
capacitance of high impedance circuit nodes.

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STATIC COMPLEMENTARY CMOS
VDD

In1
PMOS only
In2 PUN

…
InN
F(In1,In2,…InN)
In1
In2 PDN
…

NMOS only
InN

PUN and PDN are dual logic networks

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THRESHOLD DROPS
VDD VDD
PUN
S D
VDD

D 0  VDD S 0  VDD - VTn

VGS
CL CL

PDN VDD  0 VDD  |VTp|

VGS
D CL S CL
VDD

S D

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NMOS TRANSISTORS
IN SERIES/PARALLEL CONNECTION

Transistors can be thought as a switch controlled by its gate signal

NMOS switch closes when switch control input is high
A B

X Y Y=X if AandB

X B Y=Xif AORB
Y

NMOSTransistors pass a“strong”0but a“weak”1

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PMOS TRANSISTORS
IN SERIES/PARALLEL CONNECTION
PMOS switch closes when switch control input is low

A B

X Y Y= X if AANDB =A+ B

X B Y= Xif AORB= AB
Y

PMOS Transistors pass a “strong” 1 but a “weak” 0

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EXAMPLE GATE: NAND

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EXAMPLE GATE: NOR

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 OUT = D + A • (B + C)
COMPLEX CMOS GATE
COMPLEX CMOS GATE

B
A
C

D
OUT = D + A • (B + C)
A
D
B C

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CONSTRUCTING A COMPLEX GATE
VDD VDD

C
SN1 F SN4 A
F
SN2 B
A A
D D SN3

B C B C D
F

(a) pull-down network (b) Deriving the pull-up network A

hierarchically by identifying
D
sub-nets
B C

(c) complete gate

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STATIC PROPERTIES OF COMPLEMENTARY CMOS GATES

(a) A = B = 0  1 (Strong Pull up)

(b) A = 1, B = 0 1

(c) B = 1, A = 0 1 13
SWITCH DELAY MODEL
A Req
A

Rp
Rp Rp
B
A B Rp
A Rp Cint
Rn CL A
B Rn CL
A Rn Rn CL
Rn
Cint
A B
A
NOR2
NAND2 INV

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 DELAY DEPENDENCE ON INPUT PATTERNS
Input Data Delay
Pattern (psec)
Rp Rp A=B=01 67
A B A=1, B=01 64

A= 01, B=1 61
Rn CL
A=B=10 45
B
A=1, B=10 80
Rn
Cint A= 10, B=1 81
A

 Low to high transition

 both inputs go low - delay is 0.69 Rp/2 CL
 one input goes low - delay is 0.69 Rp CL
 High to low transition
 both inputs go high - delay is 0.69 2Rn CL
 To reduce the resistances, devices must be made wider 15
TRANSISTOR SIZING
Minimum size inverter (W/L) = 2/1

Rp Rp Rp
2 A B 2 4 B

Rn Rp Cint
CL 4
2 A
B

Rn Rn Rn CL
2 Cint
1
A A B 1

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TRANSISTOR SIZING A COMPLEX CMOS GATE

B 8 6
A 4 3
C 8 6

D 4 6
OUT = D + A • (B + C)
A 2
D 1
B 2C 2

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 Stick Diagram
 Stick Diagram is a simple sketch of the layout that can easily be
changed/modified/redrawn with minimal effort.

 Shows only active, poly, metal, contact, and n-well layers

 Each layer is color coded (typically use colored pencils or pens)

 Active, poly, metal traces are drawn with lines (not rectangles)

 Contacts are marked with an X —Typically only need to show contacts

between metal and active.

 N-well are indicated by a rectangle around PMOS transistors — Typically

using dashed lines

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STICK DIAGRAMS
 VLSI design aims to translate circuit concepts onto
silicon
 stick diagrams are a means of capturing topography and
layer information - simple diagrams
 Stick diagrams convey layer information through colour
codes (or monochrome encoding
 Used by CAD packages, including Microwind

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 Stick Diagram - Symbols

Metal

poly

ndiff

pdiff

Buried Contact

Contact Cut

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 Stick Diagrams

STICK DIAGRAMS – SOME RULES

Rule 1.
When two or more ‘sticks’ of the same type
cross or touch each other that represents
electrical contact.

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 Stick Diagrams

STICK DIAGRAMS – SOME RULES

Rule 2.
When two or more ‘sticks’ of different type
cross or touch each other there is no electrical
contact.
(If electrical contact is needed we have to show the connection explicitly).

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 Stick Diagrams

STICK DIAGRAMS – SOME RULES

Rule 3.
When a poly crosses diffusion it represents a
transistor.

Note: If a contact is shown then it is not a transistor.

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 Stick Diagrams

STICK DIAGRAMS – SOME RULES

Rule 4.
In CMOS a demarcation line is drawn to
avoid touching of p-diff with n-diff. All
pMOS must lie on one side of the line and all
nMOS will have to be on the other side.

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Stick Diagram – MOS Devices

N+ N+

P+ P+

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STICKS DIAGRAM…… INVERTER
VDD
V DD
PMOS
In Out
In Out
NMOS

• Dimensionless layout entities

• Only topology is important
GND • Final layout generated by
“compaction” program
Stick diagram of inverter
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 Stick Diagrams

HOW TO DRAW STICK DIAGRAMS

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Stick Diagram NAND

Circuit

Layer Design

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STICK DIAGRAM – NAND GATE

V DD

GND

In1 In2
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Stick Diagram NOR

Circuit

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 SCALING

Full Scaling (Constant –field) : preserve the magnitude of internal electric

fields while scaling down the dimensions and voltages - Greater Area, higher
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performance (Intrinsic delay) and reduced power consumption