Lecture 4

Digital Integrated
Circuits
A Design Perspective
Jan M. Rabaey
Anantha Chandrakasan
Borivoje Nikolić
Designing Combinational
Logic Circuits
November 2002.
1
© Digital
EE141 Integrated Circuits 2nd
Combinational Circuits
Combinational vs. Sequential Logic
In Out
Combinational Combinational
In Logic Out Logic
Circuit Circuit
State
Combinational Sequential
Output = f(In ) Output = f (In, Previous In )
2
© Digital
Static CMOS Circuit
At every point in time (except during the switching
transients) each gate output is connected to either
VDD or Vss via a low-resistive path.
The outputs of the gates assume at all times the value
of the Boolean function, implemented by the circuit
(ignoring, once again, the transient effects during
switching periods).
This is in contrast to the dynamic circuit class, which
relies on temporary storage of signal values on the
capacitance of high impedance circuit nodes.
3
© Digital
Static Complementary CMOS
VDD
In1
PMOS only
In2 PUN
…
InN
F(In1,In2,…InN)
In1
In2 PDN
…
NMOS only
InN
PUN and PDN are dual logic networks
4
© Digital
NMOS Transistors
in Series/Parallel Connection
Transistors can be thought as a switch controlled by its gate signal
NMOS switch closes when switch control input is high
A B
X Y Y = X if A and B
X B Y = X if A OR B
Y
NMOS Transistors pass a “strong” 0 but a “weak” 1

5
© Digital
PMOS Transistors
in Series/Parallel Connection
PMOS switch closes when switch control input is low
A B
X Y Y = X if A AND B = A + B
X B Y = X if A OR B = AB
Y
PMOS Transistors pass a “strong” 1 but a “weak” 0

6
© Digital
Threshold Drops
VDD VDD
PUN
S D
VDD
D 0  VDD S 0  VDD - VTn

VGS
CL CL
PDN VDD  0 VDD  |VTp|

VGS
D CL S CL
VDD
S D
7
© Digital
Complementary CMOS Logic Style
8
© Digital
Example Gate: NAND Using De Morgan’s
theorems ((A + B) =
A·B and A·B = A + B), it
can be shown that
the pull-up and pull-
down networks of a
complementary CMOS
structure are dual
networks. This means
that a parallel
connection of
transistors in the pull-up
network
corresponds to a series
connection of the
corresponding devices
in the pull-down and
vice versa.
9
© Digital
Example Gate: NOR
10
© Digital
Using complementary CMOS
Complex CMOS Gate logic, consider the synthesis
of a complex CMOS gate
whose
function is F = D + A· (B +C).
The first step in the synthesis
B of the logic gate is to derive
A the
pull-down network as shown
C
in Figure 6.6a by using the
fact that NMOS devices in
D series.
implements the AND function
OUT = D + A • (B + C) and parallel device
A implements the OR function.
The next step
D is to use duality to derive the
B C PUN in a hierarchical fashion
Break network into sub-nets.
11
© Digital
Constructing a Complex Gate
VDD VDD
C
SN1 F SN4 A
F
SN2 B
A A
D D SN3
B C B C D
(a) pull-down network (b) Deriving the pull-up network A

hierarchically by identifying
D
sub-nets
B C
(c) complete gate
12
© Digital
Cell Design
 Standard Cells
 General purpose logic
 Can be synthesized
 Same height, varying width
 Datapath Cells
 For regular, structured designs (arithmetic)
 Includes some wiring in the cell
 Fixed height and width
13
© Digital
Properties of Complementary CMOS Gates
Snapshot
High noise margins:

VOH and VOL are at VDD and GND, respectively.
No static power consumption:
There never exists a direct path between VDD and
VSS (GND) in steady-state mode.
Comparable rise and fall times:
(under appropriate sizing conditions)
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© Digital
CMOS Properties
 Full rail-to-rail swing; high noise margins
 Logic levels not dependent upon the relative
device sizes; ratioless
 Always a path to Vdd or Gnd in steady state;
low output impedance
 Extremely high input resistance; nearly zero
steady-state input current
 No direct path steady state between power and
ground; no static power dissipation
 Propagation delay function of load capacitance
and resistance of transistors
15
© Digital
Switch Delay Model
A Req
A
Rp
Rp Rp
B
A B Rp
A Rp Cint
Rn CL A
B Rn CL
A Rn Rn CL
Rn
Cint
A B
A
NOR2
NAND2 INV
16
© Digital
Input Pattern Effects on Delay
 Delay is dependent on
Rp Rp the pattern of inputs
A B  Low to high transition
 both inputs go low
Rn CL – delay is 0.69 Rp/2 CL
B  one input goes low
– delay is 0.69 Rp CL
Rn
Cint
A
 High to low transition
 both inputs go high
– delay is 0.69 2Rn CL
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© Digital
Transistor Sizing
Rp Rp Rp
2 A B 2 4 B
Rn Rp Cint
CL 4
2 A
B
Rn Rn Rn CL
2 Cint
1
A A B 1
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© Digital
Transistor Sizing a Complex CMOS
Gate
B 8 6
A 4 3
C 8 6
D 4 6
OUT = D + A • (B + C)
A 2
D 1
B 2C 2
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© Digital
Fan-In Considerations
A B C D
A CL
B C3 tpHL = 0.69 Reqn(C1+2C2+3C3+4CL)
C C2
Propagation delay deteriorates
D C1 rapidly as a function of fan-in –
quadratically in the worst case.
20
© Digital
tp as a Function of Fan-In
1250
quadratic
1000
Gates with a
750
fan-in
tp (psec)
tpHL tp greater than

500
4 should be
250 tpLH avoided.
linear
0
2 4 6 8 10 12 14 16
fan-in
21
© Digital
tp as a Function of Fan-Out
All gates
tpNOR2 tpNAND2 have the
same drive
tpINV current.
tp (psec)
Slope is a
function of
“driving
strength”
2 4 6 8 10 12 14 16
eff. fan-out
22
© Digital
tp as a Function of Fan-In and Fan-Out
 Fan-in: quadratic due to increasing

resistance and capacitance
 Fan-out: each additional fan-out gate
adds two gate capacitances to CL
tp = a1FI + a2FI2 + a3FO

23
© Digital
Fast Complex Gates:
Design Technique 1
 Transistor sizing
 as long as fan-out capacitance dominates
 Progressive sizing
Distributed RC line
InN MN CL
M1 > M2 > M3 > … > MN
(the fet closest to the
In3 M3 C3 output is the smallest)
In2 M2 C2 Can reduce delay by more than

In1 20%; decreasing gains as
M1 C1
technology shrinks
24
© Digital
Fast Complex Gates:
Design Technique 2
 Transistor ordering
critical path critical path
charged 01
In3 1 M3 CL In1 M3 CLcharged
In2 1 M2 In2 1 M2 C2 discharged

C2 charged
In1 In3 1 M1 C1 discharged
M1 C1 charged
01
delay determined by time to delay determined by time to

discharge CL, C1 and C2 discharge CL
25
© Digital
Fast Complex Gates:
Design Technique 3
 Alternative logic structures
F = ABCDEFGH
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© Digital
Fast Complex Gates:
Design Technique 4
 Isolating fan-in from fan-out using buffer
insertion
CL CL
27
© Digital
Fast Complex Gates:
Design Technique 5
 Reducing the voltage swing
tpHL = 0.69 (3/4 (CL VDD)/ IDSATn )
= 0.69 (3/4 (CL Vswing)/ IDSATn )

 linear reduction in delay
 also reduces power consumption
 But the following gate is much slower!
 Or requires use of “sense amplifiers” on the
receiving end to restore the signal level
(memory design)
28
© Digital
Buffer Example
In Out
1 2 N CL
N
Delay    pi  g i  f i  (in units of inv)
i 1
For given N: Ci+1/Ci = Ci/Ci-1

To find N: Ci+1/Ci ~ 4
How to generalize this to any logic path?
29
© Digital
Logical effort of a gate presents the r
Logical Effort

input capacitance to the inverter cap
when sized to deliver the same curre
p – intrinsic delay
g – logical effort (kRunitCunit)
f – effective fanout The factor g is called
the logical effort, and
Normalize everything to an inverter: represents the fact
that, for a given load,
ginv =1, pinv = 1 complex gates have to
work harder than an
inverter to produce a
Divide everything by tpinv
similar response if
(everything is measured in unit delays tpinv) input cap = inverter
cap.
Assume = 1.2nd 30
© Digital
EE141 Integrated Circuits
Delay in a Logic Gate
Gate delay:
d=h+p
effort delay intrinsic delay
Effort delay:
h=gf
logical effective fanout =

effort Cout/Cin
Logical effort is a function of topology, independent of sizing
Effective fanout (electrical effort) is a function of load/gate size
31
© Digital
Logical Effort
Logical effort is the ratio of input capacitance of a gate to the input
capacitance of an inverter with the same output current
VDD VDD VDD
A 2 A 2 B 2 B 4
F
F
A 4
A 2
A 1 F
A 1 B 1
B 2
Inverter 2-input NAND 2-input NOR
g=1 g = 4/3 g = 5/3

32
© Digital
Logical Effort of Gates
a fixed PMOS/NMOS ratio for p.
t pNAND
Normalized delay (d)
g = 4/3 t pINV
p=2
d = (4/3)h+2
g=1
p=1
d = h+1
F(Fan-in)
1 2 3 4 5 6 7
Fan-out (h)
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© Digital
Logical Effort of Gates
2
=
p
3;
4/
5 1
=
p=
Normalized Delay
g
D:
4 AN 1;
g =
:
tN
e r
rt
pu
3 v e
In
in
Effort
2-
Delay
2
1
Intrinsic
Delay
1 2 3 4 5
Fanoutf
34
© Digital
Multistage Networks
N
Delay    pi  g i  f i 
i 1
Stage effort: hi = gifi

Path effective fan-out: F = Cout/Cin
Path logical effort: G = g1g2…gN
Path effort: H = GF
Path delay D = di = pi + hi
35
© Digital
Optimum Effort per Stage
When each stage bears the same effort:

hN  H F = f1f2…fN = CL / Cg1
G = g1g2…gN
hN H
Stage efforts: g1f1 = g2f2 = … = gNfN
Effective fanout of each stage: f i  h g i
Minimum path delay
Dˆ   g i f i  pi   NH 1/ N  P
36
© Digital
Example: Optimize Path
1 b c
a
5
g=1 g = 5/3 g = 5/3 g=1
f=a f = b/a f = c/b f = 5/c
Effective fanout, F =
G=
H=
h=
a=
b=
37
© Digital
Example: Optimize Path
1 b c
a
5
g=1 g = 5/3 g = 5/3 g=1
f=a f = b/a f = c/b f = 5/c
Effective fanout, F = 5
G = g1*g2*g3*g4 = 25/9
H = G*F=125/9 = 13.9
h = (H)1/4 =1.93 f1=h/g1=1.93, f2=h/g2=1.158
f3=h/g3=1.158, f4=1.93
a = f1/g2=1.16
b = f1*f2/g3 = 1.34 Electrical effort / logical effort=sizing
38
c =
© Digital f1*f2*f3/g
EE141 Integrated Circuits
3 =
2nd 5g4 /f = 2.59 Combinational Circuits
Example – 8-input AND (assignment)
39
© Digital

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Digital Integrated

Output = f(In ) Output = f (In, Previous In )

PUN and PDN are dual logic networks

NMOS Transistors pass a “strong” 0 but a “weak” 1

PMOS Transistors pass a “strong” 1 but a “weak” 0

D 0  VDD S 0  VDD - VTn

PDN VDD  0 VDD  |VTp|

Break network into sub-nets.

(a) pull-down network (b) Deriving the pull-up network A

(c) complete gate

High noise margins:

tpHL tp greater than

 Fan-in: quadratic due to increasing

tp = a1FI + a2FI2 + a3FO

In2 M2 C2 Can reduce delay by more than

In2 1 M2 In2 1 M2 C2 discharged

delay determined by time to delay determined by time to

= 0.69 (3/4 (CL Vswing)/ IDSATn )

For given N: Ci+1/Ci = Ci/Ci-1

logical effective fanout =

Inverter 2-input NAND 2-input NOR

g=1 g = 4/3 g = 5/3

Stage effort: hi = gifi

When each stage bears the same effort:

Minimum path delay

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