L6201

® L6202 - L6203

DMOS FULL BRIDGE DRIVER

SUPPLY VOLTAGE UP TO 48V

MULTIPOWER BCD TECHNOLOGY
5A MAX PEAK CURRENT (2A max. for L6201)
TOTAL RMS CURRENT UP TO
L6201: 1A; L6202: 1.5A; L6203/L6201PS: 4A
RDS (ON) 0.3 Ω (typical value at 25 °C)
CROSS CONDUCTION PROTECTION
TTL COMPATIBLE DRIVE Powerdip 12+3+3 SO20 (12+4+4)
OPERATING FREQUENCY UP TO 100 KHz
THERMAL SHUTDOWN
INTERNAL LOGIC SUPPLY
HIGH EFFICIENCY
Multiwatt11 PowerSO20

DESCRIPTION ORDERING NUMBERS:

L6201 (SO20)
The I.C. is a full bridge driver for motor control ap- L6201PS (PowerSO20)
plications realized in Multipower-BCD technology L6202 (Powerdip18)
which combines isolated DMOS power transistors L6203 (Multiwatt)
with CMOS and Bipolar circuits on the same chip.
By using mixed technology it has been possible to ing speeds. All the logic inputs are TTL, CMOS
optimize the logic circuitry and the power stage to and µC compatible. Each channel (half-bridge) of
achieve the best possible performance. The the device is controlled by a separate logic input,
DMOS output transistors can operate at supply while a common enable controls both channels.
voltages up to 42V and efficiently at high switch- The I.C. is mounted in three different packages.

BLOCK DIAGRAM

July 2003 1/20

This is advanced information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
L6201 - L6202 - L6203

PIN CONNECTIONS (Top view)

SO20 POWERDIP

GND 1 20 GND
N.C. 2 19 N.C.
N.C. 3 18 N.C.
OUT2 4 17 ENABLE
VS 5 16 SENSE
OUT1 6 15 Vref
BOOT1 7 14 BOOT2
IN1 8 13 IN2
N.C. 9 12 N.C.
GND 10 11 GND

D95IN216

PowerSO20

MULTIWATT11

2/20
 L6201 - L6202 - L6203

PINS FUNCTIONS
Device
Name Function
L6201 L6201PS L6202 L6203
1 16 1 10 SENSE A resistor Rsense connected to this pin provides feedback for
motor current control.
2 17 2 11 ENAB When a logic high is present on this pin the DMOS POWER
LE transistors are enabled to be selectively driven by IN1 and IN2.
3 2,3,9,12, 3 N.C. Not Connected
18,19
4,5 – 4 GND Common Ground Terminal
– 1, 10 5 6 GND Common Ground Terminal
6,7 – 6 GND Common Ground Terminal
8 – 7 N.C. Not Connected
9 4 8 1 OUT2 Ouput of 2nd Half Bridge
10 5 9 2 Vs Supply Voltage
11 6 10 3 OUT1 Output of first Half Bridge
12 7 11 4 BOOT1 A boostrap capacitor connected to this pin ensures efficient
driving of the upper POWER DMOS transistor.
13 8 12 5 IN1 Digital Input from the Motor Controller
14,15 – 13 GND Common Ground Terminal
– 11, 20 14 6 GND Common Ground Terminal
16,17 – 15 GND Common Ground Terminal
18 13 16 7 IN2 Digital Input from the Motor Controller
19 14 17 8 BOOT2 A boostrap capacitor connected to this pin ensures efficient
driving of the upper POWER DMOS transistor.
20 15 18 9 Vref Internal voltage reference. A capacitor from this pin to GND is
recommended. The internal Ref. Voltage can source out a
current of 2mA max.

ABSOLUTE MAXIMUM RATINGS

Symbol Parameter Value Unit

Vs Power Supply 52 V
VOD Differential Output Voltage (between Out1 and Out2) 60 V
VIN, VEN Input or Enable Voltage – 0.3 to + 7 V
Io Pulsed Output Current for L6201PS/L6202/L6203 (Note 1) 5 A
– Non Repetitive (< 1 ms) for L6201 5 A
for L6201PS/L6202/L6203 10 A
DC Output Current for L6201 (Note 1) 1 A
Vsense Sensing Voltage – 1 to + 4 V
Vb Boostrap Peak Voltage 60 V
Ptot Total Power Dissipation:
Tpins = 90°C for L6201 4 W
for L6202 5 W
Tcase = 90°C for L6201PS/L6203 20 W
Tamb = 70°C for L6201 (Note 2) 0.9 W
for L6202 (Note 2) 1.3 W
for L6201PS/L6203 (Note 2) 2.3 W
Tstg, Tj Storage and Junction Temperature – 40 to + 150 °C

Note 1: Pulse width limited only by junction temperature and transient thermal impedance (see thermal characteristics)
Note 2: Mounted on board with minimized dissipating copper area.

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L6201 - L6202 - L6203

THERMAL DATA
Value
Symbol Parameter Unit
L6201 L6201PS L6202 L6203
Rth j-pins Thermal Resistance Junction-pins max 15 – 12 –
Rth j-case Thermal Resistance Junction Case max. – – – 3 °C/W
Rth j-amb Thermal Resistance Junction-ambient max. 85 13 (*) 60 35
(*) Mounted on aluminium substrate.

ELECTRICAL CHARACTERISTICS (Refer to the Test Circuits; Tj = 25°C, VS = 42V, Vsens = 0, unless
otherwise specified).
Symbol Parameter Test Conditions Min. Typ. Max. Unit
Vs Supply Voltage 12 36 48 V
Vref Reference Voltage IREF = 2mA 13.5 V
IREF Output Current 2 mA
Is Quiescent Supply Current EN = H VIN = L 10 15 mA
EN = H VIN = H IL = 0 10 15 mA
EN = L ( Fig. 1,2,3) 8 15 mA
fc Commutation Frequency (*) 30 100 KHz
Tj Thermal Shutdown 150 °C
Td Dead Time Protection 100 ns
TRANSISTORS
OFF
IDSS Leakage Current Fig. 11 Vs = 52 V 1 mA
ON
RDS On Resistance Fig. 4,5 0.3 0.55 Ω
VDS(ON) Drain Source Voltage Fig. 9
IDS = 1A L6201 0.3 V
IDS = 1.2A L6202 0.36 V
IDS = 3A L6201PS/0 0.9 V
3
Vsens Sensing Voltage –1 4 V

SOURCE DRAIN DIODE

Vsd Forward ON Voltage Fig. 6a and b
ISD = 1A L6201 EN = L 0.9 (**) V
ISD = 1.2A L6202 EN = L 0.9 (**) V
ISD = 3A L6201PS/03 EN = 1.35(**) V
L
trr Reverse Recovery Time dif 300 ns
= 25 A/µs
dt
IF = 1A L6201
IF = 1.2A L6202
IF = 3A L6203
tfr Forward Recovery Time 200 ns
LOGIC LEVELS
VIN L, VEN L Input Low Voltage – 0.3 0.8 V
VIN H, VEN H Input High Voltage 2 7 V
IIN L, IEN L Input Low Current VIN, VEN = L –10 µA
IIN H, IEN H Input High Current VIN, VEN = H 30 µA

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 L6201 - L6202 - L6203

ELECTRICAL CHARACTERISTICS (Continued)

LOGIC CONTROL TO POWER DRIVE TIMING
Symbol Parameter Test Conditions Min. Typ. Max. Unit
t1 (Vi) Source Current Turn-off Delay Fig. 12 300 ns
t2 (Vi) Source Current Fall Time Fig. 12 200 ns
t3 (Vi) Source Current Turn-on Delay Fig. 12 400 ns
t4 (Vi) Source Current Rise Time Fig. 12 200 ns
t5 (Vi) Sink Current Turn-off Delay Fig. 13 300 ns
t6 (Vi) Sink Current Fall Time Fig. 13 200 ns
t7 (Vi) Sink Current Turn-on Delay Fig. 13 400 ns
t8 (Vi) Sink Current Rise Time Fig. 13 200 ns

(*) Limited by power dissipation

(**) In synchronous rectification the drain-source voltage drop VDS is shown in fig. 4 (L6202/03); typical value for the L6201 is of 0.3V.

Figure 1: Typical Normalized IS vs. Tj Figure 2: Typical Normalized Quiescent Current

vs. Frequency

Figure 3: Typical Normalized IS vs. VS Figure 4: Typical RDS (ON) vs. VS ~ Vref

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L6201 - L6202 - L6203

Figure 5: Normalized RDS (ON)at 25°C vs. Temperature Typical Values

Figure 6a: Typical Diode Behaviour in Synchro- Figure 6b: Typical Diode Behaviour in Synchro-
nous Rectification (L6201) nous Rectification (L6201PS/02/03)

Figure 7a: Typical Power Dissipation vs IL Figure 7b: Typical Power Dissipation vs IL
(L6201) (L6201PS, L6202, L6203))

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 L6201 - L6202 - L6203

Figure 8a: Two Phase Chopping

Figure 8b: One Phase Chopping

IN1 = H
IN 2 = H

EN = H

Figure 8c: Enable Chopping

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L6201 - L6202 - L6203

TEST CIRCUITS
Figure 9: Saturation Voltage

Figure 10: Quiescent Current

Figure 11: Leakage Current

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 L6201 - L6202 - L6203

Figure 12: Source Current Delay Times vs. Input Chopper

42V for L6201PS/02/03

Figure 13: Sink Current Delay Times vs. Input Chopper

42V for L6201PS/02/03

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L6201 - L6202 - L6203

CIRCUIT DESCRIPTION Figure 15: Current Typical Spikes on the Sens-

The L6201/1PS/2/3 is a monolithic full bridge ing Pin
switching motor driver realized in the new Mul-
tipower-BCD technology which allows the integra-
tion of multiple, isolated DMOS power transistors
plus mixed CMOS/bipolar control circuits. In this
way it has been possible to make all the control
inputs TTL, CMOS and µC compatible and elimi-
nate the necessity of external MOS drive compo-
nents. The Logic Drive is shown in table 1.

Table 1
Inputs
Output Mosfets (*)
IN1 IN2
L L Sink 1, Sink 2
VEN = H L H Sink 1, Source 2
H L Source 1, Sink 2
H H Source 1, Source 2
VEN = L X X All transistors turned oFF
TRANSISTOR OPERATION
L = Low H = High X = DON’t care ON State
(*) Numbers referred to INPUT1 or INPUT2 controlled output stages
When one of the POWER DMOS transistor is ON
it can be considered as a resistor RDS (ON)
Although the device guarantees the absence of throughout the recommended operating range. In
cross-conduction, the presence of the intrinsic di- this condition the dissipated power is given by :
odes in the POWER DMOS structure causes the PON = RDS (ON) ⋅ IDS2 (RMS)
generation of current spikes on the sensing termi-
nals. This is due to charge-discharge phenomena The low RDS (ON) of the Multipower-BCD process
in the capacitors C1 & C2 associated with the can provide high currents with low power dissipa-
drain source junctions (fig. 14). When the output tion.
switches from high to low, a current spike is gen-
erated associated with the capacitor C1. On the OFF State
low-to-high transition a spike of the same polarity
is generated by C2, preceded by a spike of the When one of the POWER DMOS transistor is
opposite polarity due to the charging of the input OFF the VDS voltage is equal to the supply volt-
capacity of the lower POWER DMOS transistor age and only the leakage current IDSS flows. The
(fig. 15). power dissipation during this period is given by :
POFF = VS ⋅ IDSS
The power dissipation is very low and is negligible
Figure 14: Intrinsic Structures in the POWER in comparison to that dissipated in the ON
DMOS Transistors STATE.

Transitions
As already seen above the transistors have an in-
trinsic diode between their source and drain that
can operate as a fast freewheeling diode in
switched mode applications. During recirculation
with the ENABLE input high, the voltage drop
across the transistor is RDS (ON) ⋅ ID and when it
reaches the diode forward voltage it is clamped.
When the ENABLE input is low, the POWER
MOS is OFF and the diode carries all of the recir-
culation current. The power dissipated in the tran-
sitional times in the cycle depends upon the volt-
age-current waveforms and in the driving mode.
(see Fig. 7ab and Fig. 8abc).
Ptrans. = IDS (t) ⋅ VDS (t)

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 L6201 - L6202 - L6203

Boostrap Capacitors APPLICATION INFORMATION

To ensure that the POWER DMOS transistors are Recirculation
driven correctly gate to source voltage of typ. 10 During recirculation with the ENABLE input high,
V must be guaranteed for all of the N-channel the voltage drop across the transistor is RDS
DMOS transistors. This is easy to be provided for (ON)⋅ IL, clamped at a voltage depending on the
the lower POWER DMOS transistors as their characteristics of the source-drain diode. Al-
sources are refered to ground but a gate voltage though the device is protected against cross con-
greater than the supply voltage is necessary to duction, current spikes can appear on the current
drive the upper transistors. This is achieved by an sense pin due to charge/discharge phenomena in
internal charge pump circuit that guarantees cor- the intrinsic source drain capacitances. In the ap-
rect DC drive in combination with the boostrap cir- plication this does not cause any problem be-
cuit. For efficient charging the value of the boos- cause the voltage spike generated on the sense
trap capacitor should be greater than the input resistor is masked by the current controller circuit.
capacitance of the power transistor which is
around 1 nF. It is recommended that a capaci-
tance of at least 10 nF is used for the bootstrap. If Rise Time Tr (See Fig. 16)
a smaller capacitor is used there is a risk that the When a diagonal of the bridge is turned on cur-
POWER transistors will not be fully turned on and rent begins to flow in the inductive load until the
they will show a higher RDS (ON). On the other maximum current IL is reached after a time Tr.
hand if a elevated value is used it is possible that The dissipated energy EOFF/ON is in this case :
a current spike may be produced in the sense re- EOFF/ON = [RDS (ON) ⋅ IL2 ⋅ Tr] ⋅ 2/3
sistor.

Load Time TLD (See Fig.16)

Reference Voltage
During this time the energy dissipated is due to
To by-pass the internal Ref. Volt. circuit it is rec- the ON resistance of the transistors (ELD) and due
ommended that a capacitor be placed between its to commutation (ECOM). As two of the POWER
pin and ground. A value of 0.22 µF should be suf- DMOS transistors are ON, EON is given by :
ficient for most applications. This pin is also pro-
tected against a short circuit to ground: a max. ELD = IL2 ⋅ RDS (ON) ⋅ 2 ⋅ TLD
current of 2mA max. can be sinked out. In the commutation the energy dissipated is :
ECOM = VS ⋅ IL ⋅ TCOM ⋅ fSWITCH ⋅ TLD
Dead Time Where :
To protect the device against simultaneous con- TCOM = TTURN-ON = TTURN-OFF
duction in both arms of the bridge resulting in a
rail to rail short circuit, the integrated logic control fSWITCH = Chopping frequency.
provides a dead time greater than 40 ns.
Fall Time Tf (See Fig. 16)
Thermal Protection It is assumed that the energy dissipated in this
A thermal protection circuit has been included part of the cycle takes the same form as that
that will disable the device if the junction tempera- shown for the rise time :
ture reaches 150 °C. When the temperature has EON/OFF = [RDS (ON) ⋅ IL2 ⋅ Tf] ⋅ 2/3
fallen to a safe level the device restarts the input
and enable signals under control.

Figure 16.

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L6201 - L6202 - L6203

Quiescent Energy motor.

The last contribution to the energy dissipation is The L6506 senses the voltage across the sense
due to the quiescent supply current and is given by: resistor RS to monitor the motor current: it com-
pares the sensed voltage both to control the
EQUIESCENT = IQUIESCENT ⋅ Vs ⋅ T speed and during the brake of the motor.
Between the sense resistor and each sense input
Total Energy Per Cycle of the L6506 a resistor is recommended; if the
ETOT = EOFF/ON + ELD + ECOM + connections between the outputs of the L6506
and the inputs of the L6203 need a long path, a
+ EON/OFF + EQUIESCENT resistor must be added between each input of the
The Total Power Dissipation PDIS is simply : L6203 and ground.
PDIS = ETOT/T A snubber network made by the series of R and C
Tr = Rise time must be foreseen very near to the output pins of
the I.C.; one diode (BYW98) is connected be-
TLD = Load drive time tween each power output pin and ground as well.
Tf = Fall time The following formulas can be used to calculate
Td = Dead time the snubber values:
T = Period R ≅ VS/lp
T = Tr + TLD + Tf + Td C = lp/(dV/dt) where:
VS is the maximum Supply Voltage foreseen on
the application;
Ip is the peak of the load current;
DC Motor Speed Control dv/dt is the limited rise time of the output voltage
Since the I.C. integrates a full H-Bridge in a single (200V/µs is generally used).
package it is idealy suited for controlling DC mo- If the Power Supply Cannot Sink Current, a suit-
tors. When used for DC motor control it performs able large capacitor must be used and connected
the power stage required for both speed and di- near the supply pin of the L6203. Sometimes a
rection control. The device can be combined with capacitor at pin 17 of the L6506 let the application
a current regulator like the L6506 to implement a better work. For motor current up to 2A max., the
transconductance amplifier for speed control, as L6202 can be used in a similar circuit configura-
shown in figure 17. In this particular configuration tion for which a typical Supply Voltage of 24V is
only half of the L6506 is used and the other half recommended.
of the device may be used to control a second
Figure 17: Bidirectional DC Motor Control

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 L6201 - L6202 - L6203

BIPOLAR STEPPER MOTORS APPLICATIONS As shown in Fig. 18 and Fig. 19, the controller
Bipolar stepper motors can be driven with one connect directly to the two bridge BCD drivers.
L6506 or L297, two full bridge BCD drivers and External component are minimalized: an R.C. net-
very few external components. Together these work to set the chopper frequency, a resistive di-
three chips form a complete microprocessor-to- vider (R1; R2) to establish the comparator refer-
stepper motor interface is realized. ence voltage and a snubber network made by R
and C in series (See DC Motor Speed Control).
Figure 18: Two Phase Bipolar Stepper Motor Control Circuit with Chopper Current Control

L6201
L6201PS
L6202
L6203

L6201
L6201PS
L6202
L6203

Figure 19: Two Phase Bipolar Stepper Motor Control Circuit with Chopper Current Control and Translator

L6201
L6201PS
L6202
L6203

L6201
L6201PS
L6202
L6203

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L6201 - L6202 - L6203

It could be requested to drive a motor at VS lower Figure 21: Typical RTh J-amb vs. "On Board"
than the minimum recommended one of 12V Heatsink Area (L6201)
(See Electrical Characteristics); in this case, by
accepting a possible small increas in the RDS (ON)
resistance of the power output transistors at the
lowest Supply Voltage value, may be a good solu-
tion the one shown in Fig. 20.

Figure 20: L6201/1P/2/3 Used at a Supply Volt-

age Range Between 9 and 18V

L6201
L6201PS
L6202
L6203 Figure 22: Typical Transient RTH in Single Pulse
Condition (L6201)

THERMAL CHARACTERISTICS
Thanks to the high efficiency of this device, often
a true heatsink is not needed or it is simply ob-
tained by means of a copper side on the P.C.B.
(L6201/2).
Under heavy conditions, the L6203 needs a suit-
able cooling.
By using two square copper sides in a similar way
as it shown in Fig. 23, Fig. 21 indicates how to
choose the on board heatsink area when the
L6201 total power dissipation is known since: Figurre 23: Typical RTh J-amb vs. Two "On Board"
RTh j-amb = (Tj max. – Tamb max) / Ptot Square Heatsink (L6202)

Figure 22 shows the Transient Thermal Resis-

tance vs. a single pulse time width.
Figure 23 and 24 refer to the L6202.
For the Multiwatt L6203 addition information is
given by Figure 25 (Thermal Resistance Junction-
Ambient vs. Total Power Dissipation) and Figure
26 (Peak Transient Thermal Resistance vs. Re-
petitive Pulse Width) while Figure 27 refers to the
single pulse Transient Thermal Resistance.

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 L6201 - L6202 - L6203

Figure 24: Typical Transient Thermal Resistance Figure 25: Typical RTh J-amb of Multiwatt
for Single Pulses (L6202) Package vs. Total Power Dissipation

Figure 26: Typical Transient Thermal Resistance Figure 27: Typical Transient Thermal Resistance
for Single Pulses with and without versus Pulse Width and Duty Cycle
Heatsink (L6203) (L6203)

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L6201 - L6202 - L6203

mm inch
DIM. OUTLINE AND
MIN. TYP. MAX. MIN. TYP. MAX. MECHANICAL DATA

a1 0.51 0.020

B 0.85 1.40 0.033 0.055

b 0.50 0.020

b1 0.38 0.50 0.015 0.020

D 24.80 0.976

E 8.80 0.346

e 2.54 0.100

e3 20.32 0.800

F 7.10 0.280

I 5.10 0.201

L 3.30 0.130
Powerdip 18
Z 2.54 0.100

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 L6201 - L6202 - L6203

mm inch
DIM. OUTLINE AND
MECHANICAL DATA
MIN. TYP. MAX. MIN. TYP. MAX.

A 2.35 2.65 0.093 0.104

A1 0.1 0.3 0.004 0.012

B 0.33 0.51 0.013 0.020

C 0.23 0.32 0.009 0.013

D 12.6 13 0.496 0.512

E 7.4 7.6 0.291 0.299

e 1.27 0.050

H 10 10.65 0.394 0.419

h 0.25 0.75 0.010 0.030

L 0.4 1.27 0.016 0.050

SO20
K 0˚ (min.)8˚ (max.)

L
h x 45˚

B e K A1 C
H

20 11

1 0
1

SO20MEC

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L6201 - L6202 - L6203

mm inch
DIM.
MIN. TYP. MAX. MIN. TYP. MAX. OUTLINE AND
A 3.6 0.142 MECHANICAL DATA
a1 0.1 0.3 0.004 0.012
a2 3.3 0.130
a3 0 0.1 0.000 0.004
Weight: 1.9gr
b 0.4 0.53 0.016 0.021
c 0.23 0.32 0.009 0.013
D (1) 15.8 16 0.622 0.630
D1 9.4 9.8 0.370 0.386
E 13.9 14.5 0.547 0.570
e 1.27 0.050
e3 11.43 0.450
E1 (1) 10.9 11.1 0.429 0.437
E2 2.9 0.114
E3 5.8 6.2 0.228 0.244
G 0 0.1 0.000 0.004
H 15.5 15.9 0.610 0.626
h 1.1 0.043 JEDEC MO-166
L 0.8 1.1 0.031 0.043
N 8˚ (typ.)
S 8˚ (max.)
T 10 0.394
(1) “D and E1” do not include mold flash or protusions.
PowerSO20
- Mold flash or protusions shall not exceed 0.15mm (0.006”)
- Critical dimensions: “E”, “G” and “a3”.

N N R

a2 A
c
a1
b e DETAIL B
DETAIL A E
e3
H DETAIL A
lead

D
a3 slug

DETAIL B

20 11 0.35
Gage Plane
-C-

S SEATING PLANE
L
G C
BOTTOM VIEW (COPLANARITY)
E2 E1

E3

1 10

PSO20MEC
D1
h x 45
0056635

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 L6201 - L6202 - L6203

mm inch
DIM.
MIN. TYP. MAX. MIN. TYP. MAX. OUTLINE AND
A 5 0.197 MECHANICAL DATA
B 2.65 0.104
C 1.6 0.063
D 1 0.039
E 0.49 0.55 0.019 0.022
F 0.88 0.95 0.035 0.037
G 1.45 1.7 1.95 0.057 0.067 0.077
G1 16.75 17 17.25 0.659 0.669 0.679
H1 19.6 0.772
H2 20.2 0.795
L 21.9 22.2 22.5 0.862 0.874 0.886
L1 21.7 22.1 22.5 0.854 0.87 0.886
L2 17.4 18.1 0.685 0.713
L3 17.25 17.5 17.75 0.679 0.689 0.699
L4 10.3 10.7 10.9 0.406 0.421 0.429
L7 2.65 2.9 0.104 0.114
M 4.25 4.55 4.85 0.167 0.179 0.191
M1 4.73 5.08 5.43 0.186 0.200 0.214
S 1.9 2.6 0.075 0.102
S1 1.9 2.6 0.075 0.102 Multiwatt11 V
Dia1 3.65 3.85 0.144 0.152

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L6201 - L6202 - L6203

Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is
granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specification mentioned in this publication are
subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products
are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.
The ST logo is a registered trademark of STMicroelectronics
© 2003 STMicroelectronics – Printed in Italy – All Rights Reserved
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