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    Pass-Transistor Logic: - N Transistors - No Static Consumption

    Uploaded by

    Alfred Kiruba Raj
    Pass-transistor logic uses transistors as switches to implement logic functions. It can reduce static power consumption compared to CMOS by eliminating the need for a pull-up network, but suffers from threshold voltage loss. Solutions to address threshold voltage loss include using a transmission gate composed of an NMOS and PMOS transistor (1), adding a level restoring transistor (2), or using complementary pass-transistor logic with both NMOS and PMOS networks (3). Complimentary pass-transistor logic can implement common logic functions like AND, OR, XOR without threshold voltage loss.

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    Pass-Transistor Logic: - N Transistors - No Static Consumption

    Uploaded by

    Alfred Kiruba Raj
    279 views15 pages
    Pass-transistor logic uses transistors as switches to implement logic functions. It can reduce static power consumption compared to CMOS by eliminating the need for a pull-up network, but suffers from threshold voltage loss. Solutions to address threshold voltage loss include using a transmission gate composed of an NMOS and PMOS transistor (1), adding a level restoring transistor (2), or using complementary pass-transistor logic with both NMOS and PMOS networks (3). Complimentary pass-transistor logic can implement common logic functions like AND, OR, XOR without threshold voltage loss.

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    Pass-transistor logic uses transistors as switches to implement logic functions. It can reduce static power consumption compared to CMOS by eliminating the need for a pull-up network, but suffers from threshold voltage loss. Solutions to address threshold voltage loss include using a transmission gate composed of an NMOS and PMOS transistor (1), adding a level restoring transistor (2), or using complementary pass-transistor logic with both NMOS and PMOS networks (3). Complimentary pass-transistor logic can implement common logic functions like AND, OR, XOR without threshold voltage loss.

    Copyright:

    © All Rights Reserved
    Download as PPT, PDF, TXT or read online from Scribd
    Download as ppt, pdf, or txt
    279 views15 pages

    Pass-Transistor Logic: - N Transistors - No Static Consumption

    Uploaded by

    Alfred Kiruba Raj
    Pass-transistor logic uses transistors as switches to implement logic functions. It can reduce static power consumption compared to CMOS by eliminating the need for a pull-up network, but suffers from threshold voltage loss. Solutions to address threshold voltage loss include using a transmission gate composed of an NMOS and PMOS transistor (1), adding a level restoring transistor (2), or using complementary pass-transistor logic with both NMOS and PMOS networks (3). Complimentary pass-transistor logic can implement common logic functions like AND, OR, XOR without threshold voltage loss.

    Copyright:

    © All Rights Reserved
    Download as PPT, PDF, TXT or read online from Scribd
    Download as ppt, pdf, or txt
    of 15

    Pass-Transistor Logic

    Switch Out A
    Out
    Inputs

    Network B
    B

    • N transistors
    • No static consumption
    NMOS-only switch

    C=5V C=5V
    M2
    A=5V A=5V B
    Mn
    B
    CL M1

    VB does not pull up to 5V, but 5V - VTN

    Threshold voltage loss causes


    static power consumption
    Solution 1: Transmission Gate

    C
    C

    A B A B

    C
    C

    C=5V
    A=5V
    B
    CL

    C=0V
    Resistance of Transmission Gate

    30000.0
    Rn
    (W/L)p =(W/L)n =
    1.8/1.2
    20000.0
    R (Ohm)

    Rp

    10000.0
    Req

    0.0
    0.0 1.0 2.0 3.0 4.0 5.0
    Vout
    Pass-Transistor Based Multiplexer

    S S
    VDD

    VDD
    S

    A
    M2

    S F

    M1
    B

    GND
    In1 S S In2
    Transmission Gate XOR

    B
    M2

    A
    A
    F
    M1 M3/M4
    B

    B
    Delay in Transmission Gate Networks

    5 5 5 5
    V1 Vi-1 Vi Vi+1 Vn-1 Vn
    In

    C C C C C
    0 0 0 0

    (a)

    Req Req Req Req


    V1 Vi Vi+1 Vn-1 Vn
    In

    C C C C C

    (b)
    m

    Req Req Req Req Req Req


    In
    C CC C C CC C

    (c)
    Elmore Delay (Chapter 8)

    Vin R1 1 R2 2 Ri-1 i-1 Ri i RN N

    C1 C2 Ci-1 Ci CN

    Assume All internal nodes are precharged to VDD and a step voltage is
    applied at the input Vin

    N N N i
    N =  Ri  C j =  C i  R j
    i=1 j=i i=1 j=1
    Delay Optimization
    Transmission Gate Full Adder

    P
    VDD
    VDD Ci
    A
    P S Sum Generation
    A A P Ci

    A P VDD
    B B
    VDD A
    P
    P Co Carry Generation
    Ci Ci Ci
    A
    Setup P
    (2) NMOS Only Logic: Level Restoring Transistor

    VDD
    Level Restorer VDD
    Mr
    B
    M2
    X
    A Mn Out
    M1

    • Advantage: Full Swing


    • Disadvantage: More Complex, Larger Capacitance
    • Other approaches: reduced threshold NMOS
    Level Restoring Transistor

    with
    5.0 5.0
    without
    Vout (V)

    3.0 3.0 without


    with

    VX
    VB
    1.0 1.0

    -1.00 2 4 6 -1.00 2 4 6
    t (nsec) t (nsec)
    (a) Output node (b) Intermediate node X
    Solution 3: Single Transistor Pass Gate with VT=0

    VDD

    VDD
    0V 5V

    VDD 0V Out

    5V

    WATCH OUT FOR LEAKAGE CURRENTS


    Complimentary Pass Transistor Logic

    A
    Pass-Transistor
    A F
    B Network
    B
    (a)
    A Inverse
    A Pass-Transistor F
    B
    B Network

    B B B B B B

    A A A

    B F=AB B F=A+B A F=AÝ

    A A A
    (b)

    B F=AB B F=A+B A F=AÝ

    AND/NAND OR/NOR EXOR/NEXOR


    4 Input NAND in CPL

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