ECE467: Introduction to VLSI Design

Lecture-7

Different Types of Inverter

Masud H. Chowdhury
Electrical and Computer Engineering
University of Illinois at Chicago
 CMOS Logic
Defining Characteristics:
• These logic circuits are built using both NMOS and
VDD
PMOS devices
• Consist of a pull-down network and a pull-up network
• Normally pull-down network is made of NMOS
Pull-up
device and pull-up network is made of PMOS device network Iup

• The pull-down network connects the gate output to

GND (‘0’) and the pull-up network connects the Vout
Vin
output to Vdd (‘1’)
• That’s why these type of logic is called
Pull-down Idown
complementary MOS logic network
CL

Selection of Device:
• Pull-down network: NMOS
– NMOS is a very good pull-down device
• Pull-up network: PMOS
– PMOS is very good pull-up device

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 Static CMOS Inverter
Definition:
• The inverter is the most fundamental logic gate that performs the Boolean
operation of inversion on a single input variable
Symbol and Logic Function:
Truth Table
A B
A B= A 0 1
1 0

Inverter From Electrical Point View:

• Both input and output variables are represented by node voltages, referenced to
ground potential
• Positive logic convention:
– Logic value of “1” or “high” is presented by VDD or supply level
– Logic value of “0” or “low” is represented by 0 or ground potential

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 Different Types of Inverter
Ratioless Inverter:
• Static CMOS Inverter
Ratioed Inverter:
• Resistive Load Inverter
• Active Load Inverter
– Enhancement-type Saturated Load MOS Inverter
– Depletion Load NMOS Inverter
– Pseudo NMOS Inverter
Ratioless Logic Circuit: The logic values do not depend on the relative size or the ratio
of the transistors in PUN and PDN
Ratioed Logic Circuit: The logic values depend on the relative size or the ratio of the
transistors in PUN and PDN
– In complimentary MOS design the purpose of PUN and PDN is to provide a
conditional connection between either VDD or GND
– In CMOS technique PUN is implemented with PMOS devices and PDN is
implemented using NMOS devices.
– In case of ratioed design technique, PDN is consists of NMOS transistors
that realize logic function, and the entire PUN is replaced by a single
unconditional load device that pulls up the output for high output as shown
in figure in next slide
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 Ratioed Logic

VDD VDD VDD VDD

Resistive Saturated Depletion PMOS

Load RL Load Load VT < 0 Load
VSS
F F F F
In1 In1 In1 In1
In2 PDN In2 PDN In2 PDN In2 PDN
In3 In3 In3 In3

VSS VSS VSS VSS

(a) resistive load (b) Enhancement-type (c) depletion load NMOS (d) pseudo-NMOS
saturated load MOS
Inverter

Goal: to reduce the number of devices over complementary CMOS

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 Resistive Load Inverter
• In the resistive load inverter the PDN is consist of an
NMOS transistor and the load consists of a simple
VDD
linear resistor RL.
• Operating Regions:
Resistive
• Here Vin = VGSn and Vout = VDSn
Load RL
Vin < VTn ……………………… Cut-off
Vin – VTn < Vout (or VDS)…….. Saturation
out Vin – VTn > Vout (or VDS)………Linear

In • Need to Determine:
PDN • VOH, VOL, VM, VIL and VIH
• Static Power Consumption
• Propagation delay
VSS
• Disadvantage of Resistive Load Inverter
• RL >>> Rtr to make VOL close to zero
• Area sacrifice due to large RL.
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• Static power consumption
 Resistive Load Inverter
•
VDD
• When Vin = 0, NMOS is OFF and Vout is raised to
VDD through RL
• When Vin = Vdd, NMOS driver is ON. Resistive
• There is a race condition between NMOS and RL. Load RL
NMOS tries to discharge the output capacitance,
while current through RL tries to charge the output
capacitance
out
• The value of RL is made much higher than Rtrn to
obtain a low output voltage
In
• By ensuring RL >> Rtrn a low output voltage is PDN
obtained. But it is not equal to zero

N transistors + Load Asymmetrical response

VSS
VOH = VDD Static power consumption

VOL = RPN
t pL = 0.69 RLCL
RPN + RL
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 Active Load Inverters
VDD VDD VDD

Saturated Depletion PMOS

Load Load VT < 0 Load
VSS
out out out
In In In
PDN PDN PDN

VSS VSS VSS

(b) Enhancement-type (c) depletion load NMOS (d) pseudo-NMOS
saturated load MOS
Inverter

• The simple resistive load inverter is not suitable for most VLSI design due to
large area occupied by the load resistor.
• Another class of inverter was introduced with MOSFET transistors as active
load device.
• The main advantage of using MOSFET as the load device is that silicon area
occupied by the transistors is smaller than that occupied by a comparable
resistive load. 8
 Pseudo NMOS Inverter
• In pseudo NMOS design technique a permanently grounded PMOS load is used
instead of a linear resistor. VDD

Advantages:
• Lower transistor count PMOS
load
• Smaller area compared to resistive load and CMOS design L I
Vout = VDSn
Disadvantage: D I

• All the disadvantages of ratioed logic NMOS

Vin = VGSn CL
Operation: driver

• Its operation is similar to that of resistive load inverter.

• PMOS load is permanently grounded and always remains ON, since VSG = VDD
• When Vin = 0, NMOS is OFF and Vout is raised to VDD through the PMOS
• When Vin = Vdd, both NMOS driver and PMOS load are ON.
• There is a race condition between NMOS and PMOS. NMOS tries to discharge the
output capacitance, while PMOS tries to charge the output capacitance
• PMOS is made smaller compared to NMOS to ensure RL >> Rtrn. Here RL is the
effective resistance of PMOS load. By ensuring RL >> Rtrn a low output voltage is
obtained. By voltage divider formula we get R
VOL = R PN
PN + R L
• Obviously the low output voltage is not equal to zero. The lowest level of output
depends on the relative values of RL and RPN 9
 Important Features of Ratioed Inverter
• Reduced number of transistor for logic implementation
• The performance and operation of these gates depend on the resistance or
device ratio of the PUN and PDN. RL must be much greater than RPN to
make VOL close to zero
• General Shape of VTC is similar to that of CMOS inverter. But VTC is not
symmetrical
• VOL is imperfect. Here VOH is equal to VDD, but VOL is not perfect and is
larger than 0V.
• Asymmetric design leads to asymmetric noise margins. Since VOL is larger
than 0V, these types of devices has smaller NML (NML = VIL – VOL)
• The load device is always ON and conducting current. PDN is ON half of
the period. Therefore, at steady-state there is a direct current conduction
from path VDD to GND for half the cycle. Therefore, there will be always
static power consumption in addition to leakage and dynamic power
consumption

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 Derivation of Different Characteristics of
Ratioed Inverter
• Need to Determine:
• VOH, VOL, VM, VIL and VIH
• Noise Margins
• Static Power Consumption
• Propagation delay

we will do these through some design problems in class

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 Exam Question
1. True/False: Write ‘T’ for true and ‘F’ for false on the right side of
each question (1x10=10 points)
a. Static power is due to the short circuit between Vdd and GND
during switching
2. Briefly Answer the Following Questions (2x5=10 points)
a. Why in a Pseudo NMOS Inverter the resistance of load device
must be much higher than the resistance of the PDN transistor?
b. Keeping all other parameter unchanged if you double both the
channel length (L) and gate oxide thickness (tox) of a transistor
what will be the change in current ID?
3. Three Problems Similar to HW1 and HW2 (3x20 = 60)

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