ECE467: Introduction to VLSI Design

Lecture-1

Introduction to Integrated Circuits:

Concepts, Historical Developments, and Metrics of Design

Masud H. Chowdhury
Electrical and Computer Engineering
University of Illinois at Chicago
 Technological Revolution Fueled by
Integrated Circuits

ENIAC - The first Electronic Computer (1946)

Dimension: A tiny tablet PC with less than 1” thickness can
be give you million times higher computing
• 80 Feet Long
power than the earliest computer
• 8.5 Feet High
• Several Feet Wide
Parts:
• 18000 Vacuum Tubes
M. Chowdhury @ UIC 2
 Technological Revolution Fueled by
Integrated Circuits

ENIAC - The first Electronic Computer (1946)

Dimension: A tiny tablet PC with less than 1” thickness can
be give you million times higher computing
• 80 Feet Long
power than the earliest computer
• 8.5 Feet High
• Several Feet Wide
Parts:
• 18000 Vacuum Tubes
M. Chowdhury @ UIC 3
 Telephone- Communicate Greater Distances

Early Days
of
Telephone

• Johnson 6 (1875): The Gallows Frame Telephone was one of the earliest phones
– Designed by Alexander Graham Bell and built by Thomas A. Watson
• The first generation telephone sets were wall mounted, magneto and battery type,
with a crank on the side to generate current for ringing
• In the station an operator must be present in front of a switch board to connect the
caller’s phone line to the receiver’s phone line
M. Chowdhury @ UIC 4
• The overall operation was mechanical and involved manual operators
 Today’s Telephone

Cell
Phone Regular Phone

Small
Personal Organizer
Power
Signal RF RF
Text and Graphical
Communication
Power
Management Audio/Video Entertainment
Digital Cellular Market
(Phones Shipped) Analog
Image Capturing
Baseband

1996 1997 1998 1999 2000 Internet Browsing

Digital Baseband
(DSP + MCU)
Units 48M 86M 162M 260M 435M

(data from Texas Instruments)

M. Chowdhury @ UIC 5
 Today’s Telephone

M. Chowdhury @ UIC 6
 Early Days of Television
• An Announcement - July 1928 of the British magazine, called Television.
"Baird Televisors ("seeing-in instruments") will be on sale in the country [England]
at the annual Radio Exhibition to be held at Olympia, September 22nd to 29th,
1928"
• Announcement Caption:
"One of the several designs of the new Baird Televisor, which will be marketed here
and in America in September."

M. Chowdhury @ UIC 7
Seeing instruments: Seeing from distance
 Television: Past and Present

Dimension: Dimension:
Size of a standard dining table 58” x 35” x 4”

Screen: Screen:
Diagonally 7” Viewable Diagonally 61” Viewable

Colors and Shades: Colors and Shades:

M. Chowdhury @ UIC
2 (black and white) 16.9 Million Different Shades8
 Which Color You Like?

M. Chowdhury @ UIC 9
 Definition of Integrated Circuits (IC)
Integrated circuit: The concepts of integrated circuit (IC) is referred to
microelectronic circuits, where all the active and passive circuit
components are fabricated on a single semiconductor substrate or chip
– Active element:
• the electrical characteristics of these elements vary depending on
applied excitation force
• These elements have the ability to act as electrical switches (ON-
OFF characteristics)
• These elements can amplify electrical signals
• Example: (i) pn-junction Diode , (ii) Transistors: BJT, MOSFET,
JFET etc., and (iv) vacuum tube
– Passive element:
• Electrical characteristics of these elements mainly depend on the
physical properties of the materials and the geometrical shapes of
the elements
• These elements can not act as switch or amplifier
• Example: (i) Resistor, (ii) Inductor, (iii) Capacitor, (iv) Wire,
and (v) Insulator
M. Chowdhury @ UIC 10
 Invention of Transistor
Transistor Definition: Transistors are electronically controlled switches with
a control terminal and two other terminals that are connected or
disconnected depending on the voltage applied to the control terminal
Pre-Transistor Era:
• Vacuum tube was the technology for realizing many electronic circuits
before transistors were invented. Vacuum tubes ruled in the first half of 20th
century
• But they were large, expensive, power-hungry, and unreliable
• Excessive power consumption made vacuum tubes obsolete
Point contact transistor:
• John Bardeen and Walter Brattain
of Bell Lab invented point contact
transistor in 1947
• It was nearly declared military secret
• Bell Lab made it public

M. Chowdhury @ UIC 11
 Technology Selection for Integrated Circuits
The beginning of Integrated Circuit (IC):
• The concept of IC was introduced by Jack Kilby of Texas Instrument in
1958 to miniaturize electronic circuits by building multiple transistors on a
single body
• A two transistors (BJTs) flip-flop had been the first Integrated Circuit
implementation, which was built from germanium slice and gold wires
Bipolar Junction Transistor (BJT):
• BJT, invented in 1949 by Schockley, comes in npn or pnp silicon structure
• It requires a small current into base layer that controls large currents
between emitter and collector
• BJT was more reliable, less noisy, and more power-efficient than first
version of point contact transistor
• Invention of BJT and inception of the idea of building IC lead to the
introduction of first set of commercial IC logic gates, called Fairchild
Micrologic Family
• Transistor-Transistor Logic (TTL), pioneered in 1962, became very
successful IC logic family. TTL had the advantage of offering higher
integration density, which made TTL the most popular logic design
approach until 1980s.
M. Chowdhury @ UIC 12
 Bipolar Junction Transistor

E n p n C

E p n p C

B
M. Chowdhury @ UIC 13
 Technology Selection for Integrated Circuits
Emitter Coupled Logic:
• Other logic families were also developed keeping higher performance in
mind.
• For example, Emitter Coupled Logic (ECL), which is capable of producing
subnanosecond gates.

ECL 3-input Gate

Motorola 1966

M. Chowdhury @ UIC 14
 Technology Selection for Integrated Circuits
Metal Oxide Semiconductor Field Effect Transistors (MOSFET):
• The idea of Field Effects devices was originally proposed by German
scientist Julius Lilienfield in 1925 and British scientist Oskar Heil in 1935
• Material problems foiled early attempts to make functioning device
• In MOSFET, which comes in two flavors – NMOS and PMOS, a voltage
applied to insulated gate controls current between source and drain

Source Gate Drain Source Gate Drain

Polysilicon

SiO2

n+ n+ p+ p+
p bulk Si n bulk Si

M. Chowdhury @ UIC 15
 Technology Selection for Integrated Circuits
MOSFET largely replaced BJT Technology:
• The quiescent power dissipated by the base current of BJT limited the
integration density as IC became more complex
• Power consumption was the reason that haunted vacuum tube approach.
For the same reason BJT started loosing favor as compared more power-
efficient MOSFET technology
• MOSFETs offer the advantage of almost zero control current while idle.
• Low power consumption of MOSFETs allows very high integration
• Improvement of silicon processes made MOSFETs more popular due to
simpler fabrication process, and lower cost and area per device
• First generations of MOS ICs used PMOS-only technology. But PMOS-
only processes suffered from poor performance, yield, and reliability
• NMOS-only processes became dominant in the 1970s. NMOS transistor
has the advantage of implementing faster gate for the same area compared
to PMOS transistor
• But soon Complementary MOS (CMOS) technology replaced every
technology in almost 80% of IC applications

M. Chowdhury @ UIC 16
 Technology Selection for Integrated Circuits
Complementary Metal Oxide Semiconductor (CMOS):
• In 1963 Frank Wanlass at Fairchild described the first logic gates using
both NMOS and PMOS transistors, earning the name CMOS
• Wanlass used discrete transistors, but soon improvement of silicon
technology made CMOS integrated circuits possible
• While NMOS process is less expensive than CMOS, NMOS logic gates
still consumes power while idle.
• CMOS logic gates consumes almost zero static power
• Even the discrete CMOS circuit built by Wanlass consumed only nano-
watts of power, six orders of magnitude less than their bipolar counterparts
• Power consumption became the major issue in 1980s as hundreds of
thousands of transistors were integrated onto a single chip
• CMOS process has become the most widely adopted technology and
replaced most of NMOS and bipolar processes for nearly all digital
applications
• Currently CMOS technology holds more than 80% of the market share

M. Chowdhury @ UIC 17
 Historical Development
First 4 Kbits memory: First memory IC was built in 1970 using MOSFET
¾ Intel later pioneered NMOS technology with its 1101 256-bit static random access
memory
First Microprocessor: First 4-bit Microprocessor (Intel 4004) in 1972
¾ 1970’s processes usually had only nMOS transistors

Intel 1101 256-bit SRAM Intel 4004 4-bit mProc Intel Pentium 4 mProc

¾ Intel Pentium 4 in 2003: Contained 55 million transistors

¾ 512-Mbit dynamic memory (DRAM): Contained half a billion transistors
M. Chowdhury @ UIC 18
 Historical Growth Rate
Growth Rate:
¾ Number of transistors increased from 2 in the first IC (1958) to 55 millions in Intel
Pentium 4 (2003). A growth corresponds to a compound rate of 53% annually over
45 years
¾ No other technology in history has sustained such a high growth rate for so long.
Most other fields involve tradeoffs between performance, power and price.
However, as transistors become smaller, they also become faster and cheaper
¾ Steady miniaturization of transistors and improvement of process and
manufacturing technologies made it possible
Moore’s Law:
¾ Gordon Moore – the founder of Intel observed in 1965 that plotting the number of
transistors that can be most economically integrated on a chip gives a straight line
on a semi-logarithmic scale. At that time he found that transistor count doubling
every 18 months. This observation has been called Moore’s Law
¾ In 2003 semiconductor industry manufactured more than one quintillion (1018)
transistors, or 100 million for every human being on this planet
¾ Not only the transistor count, but also the clock frequency or the speed of
integrated circuits have seen an unprecedented rise over last few decades

M. Chowdhury @ UIC 19
 1,000,000,000
Historical Growth Rate 10,000

100,000,000
Pentium 4 1,000 4004

Pentium III 8008

10,000,000 Pentium II
Pentium Pro 8080
Transistors

Clock Speed (MHz)

Pentium
Intel486 100 8086
1,000,000
80286
Intel386
80286 Intel386
100,000
10 Intel486
8086
Pentium
10,000 8080 Pentium Pro/II/III
8008
4004 1 Pentium 4
1,000

1970 1975 1980 1985 1990 1995 2000

1970 1975 1980 1985 1990 1995 2000 2005
Year Year

Transistor counts in Intel processors have doubled Intel microprocessor clock frequencies have
every 26 months doubled every 34 months

Semiconductor Market
¾ 1994: IC industry has become a $100B/year business
¾ 2000: A huge surge for Y2K upgrades followed by worldwide recession
¾ 2003: 1018 transistors manufactured. 100 million for every human on the planet
Global Semiconductor Billings

200
(Billions of US$)

150

100

50

0
1982 1984 1986 1988 1990 1992 1994 1996 1998 2000 2002

Year
M. Chowdhury @ UIC 20
 Level of Integration
SSI: Small-scale Integration (SSI) circuits has been classified as those with roughly
fewer than 10 gates and about a dozen transistors per gate, such as, 7400 series logic
ICs.
MSI: Medium-scale Integration (MSI) circuits are those with up to 1000 gates per
chip, such as, 74000 series counters
LSI: Large-scale Integration (LSI) circuits have up to 10,000 gates per chip, such as, 8-
bit microprocessor
¾ It soon became apparent that new names would have to be created every five
years if this naming trend continued and thus the term VLSI is used to describe
all ICs from 1980s onward
VLSI: Very Large Scale Integration (VLSI) circuits can now contain hundreds of
thousands of gates with billions of transistors per chip
¾ In some literature the term ULSI (Ultra Large Scale Integration) is used for
current and upcoming integrated circuits, but this term has not yet become
popular.
Integration Levels
SSI: 10 gates
MSI: 1000 gates
LSI: 10,000 gates
VLSI: > 10k gates
M. Chowdhury @ UIC 21
 Transistor Scaling
Transistor Sizes:
• Intel 4004 in 1971 used transistors with minimum dimensions of 10 micrometer,
whereas Pentium 4 in 2003 used 130 nanometer transistors. This corresponds to two
orders of magnitude in reduction over three decades
• IC industry has now entered into the Nanometer Regime
• As predicted this downward scaling of transistors will continue for at least a decade
• Dramatic scaling of all physical and electrical parameters is going on simultaneously
Why Scaling:
• Technology shrinks by 0.7/generation
• With every generation can integrate 2x more functions per chip; chip cost does not
increase significantly
• Cost of a function decreases by 2x
• But …
– How to design chips with more and more functions?
– Design engineering population and efficiency does not double every two years…
• Hence, a need for more efficient design methods
– Resolve numerous challenges that arise at every design step in every generation
– Exploit different levels of abstraction
M. Chowdhury @ UIC 22
 Issues of Integrated Circuit Technology
• Integration Density:
– We have observed an exponential growth in integration density
– More functionality in less area with reduced cost per die
• Performance or Speed:
– Performance or speed of integrated circuits is measured in terms of operating
clock frequencies
– Demand for faster operation is always growing
– At current rate clock frequencies double almost every three year (refer to previous
slides)
• Technology Scaling:
– Continuous demand for higher integration density and faster speed is pushing the
physical limits of the circuit and system elements to the extreme end.
– As we enter into nanometer scale probably we are approaching the end of the road
• Time to market: Crucial factors that determine economic feasibility of an IC
• Reliability: noise immunity, fault tolerance and robustness
• Manufacturability: Ability to transfer a design from “soft form” to “hard form”
often limits the achievements
• Power Consumption: most important deciding factor
• Power and Clock Distribution Schemes: Becoming very complex
• Interconnect and Parasitics: Have become dominant over device parameters
M. Chowdhury @ UIC 23
 Issues of Integrated Circuit Technology
• Design Automation:
– Early design were truly hand-crafted, where every transistor was laid out and
optimized individually and carefully fitted to the environment
– But manual design approach has become inadequate as integrated circuit’s
complexity is becoming intractable for manual analysis
– Computer aided design automation has evolved to resolve this issue. With rapid
evolution of technology, the scopes and efficiency of the CAD tools are
increasing.
– Still there is a huge gap between what designers want to do and what they can
handle by the available tools
– Designers have to adhere to rigid design methodologies and strategies that more
amenable to design automation
– Regularity and reuse of cells or blocks are the two prime features of design
automation
– In this approach cells are reused as much as possible to reduce design effort and
to ensure regularity, so that an IC can be constructed in a hierarchical way
– Consequently, automation approaches work very well for the systems that can
be designed by hierarchical approach.
M. Chowdhury @ UIC 24
 Levels of Abstraction
– Hierarchical approach requires
different levels of abstraction
– At each design level, the internal
designs or details of a complex
module can be abstracted away
from the designer of that level
– Instead of the internal detail a
designer can use a model, which
contains all the information
needed to deal with the block at
the next level of hierarchy
– Digital integrated circuits are
very suitable for design
automation, since their design
efforts can be divided into
multiple abstraction levels that
can be handled by individual
design group
M. Chowdhury @ UIC 25
 Design Partitioning
• Architecture: describes the function of the system
– User’s perspective, what does it do?
– Instruction set, registers, memory model
– MIPS, x86, Alpha, PIC, ARM, …
• Micro-architecture: how the architecture is partitioned into functional units
– Single cycle, multicycle, pipelined, superscalar?
• Logic Design: how are functional blocks constructed
– Ripple carry, carry look-ahead, carry select adders
– Logic minimization and check for functional correctness
• Circuit Design: how are transistors used to implement the logic
– Complementary CMOS, pass transistors, domino
– Detail circuit specifications for performance, power and other metrics
• Physical Design: describes the chip layout
– Datapaths, memories, random logic
– Design Verification & Area Estimation
– Dependent on process technology

M. Chowdhury @ UIC 26
 Fabrication, Packaging & Testing
• Fabrication:
– Tapeout final layout
– 6, 8, 12” wafers
– Optimized for throughput, not latency (10 weeks!)
– Cut into individual dice and packaged
• Packaging:
– Bond gold wires from die I/O pads to package
– Cooling requirements
– Electro-mechanical interface with external environment

• Testing:
– Test chips for Design and Manufacturing errors
– A single dust particle or wafer defect kills a die
– Yields from 90% to < 10%. Depends on die size, maturity of process
– Test each part before shipping to customer
M. Chowdhury @ UIC 27
 Metrics for Evaluating Integrated Circuit
• How to evaluate performance of an IC?
– Functionality
– Reliability
– Scalability
– Speed (delay, operating frequency)
– Power dissipation and Energy to perform a function
– Cost

M. Chowdhury @ UIC 28
 Metrics for Evaluating Integrated Circuit
Functionality: it should perform its function it is designed for
– Cause of malfunction:
• Logic fault
• Variation in manufacturing process
• Noise: unwanted variation of signal at logic node
Reliability or Robustness: It measures how robust a circuit is against the
variations in manufacturing process and noise disturbance
– Noise margin: Sensitivity of a circuit to noise is given by noise margin
• Higher noise margins are desired
• Lower noise margin means lower robustness against noise
• It expresses the capability of overpowering a noise source
– Noise immunity: Ability to function properly in the presence of noise
• Circuit with low noise margin may have very good noise immunity
• Noise immune circuits reject a noise source rather than overpower it

M. Chowdhury @ UIC 29
 Reliability:Noise in Digital Integrated Circuits

v(t) V DD
i(t)

Inductive coupling Capacitive coupling Power and ground

noise

M. Chowdhury @ UIC 30
 DC Operation
Voltage Transfer Characteristic
Vout

V f
VOH = f(VOL)
OH
Vout =Vin VOL = f(VOH)
VM = f(VM)
VOH: Nominal high output voltage
VOL: Nominal low output voltage
VM Switching Threshold VIL: Input low voltage
VIH: Input high voltage
VM: Switching threshold voltage
V OL
where Vin = Vout

V IL V Vin
IH

Nominal Voltage Levels

M. Chowdhury @ UIC 31
Mapping between analog and digital signals

V
V
out
“ 1” OH
V Slope = -1
V OH
IH

Undefined
Region

V
IL
Slope = -1

“ 0”
V
V
OL
OL
V V V
IL IH in
M. Chowdhury @ UIC 32
 Definition of Noise Margins
"1"
V
OH
NM H Noise margin high
V
IH
Transition width Undefined
(TW) Region
NM L V
V
OL
IL Noise margin low

"0"

Gate Output Gate Input

Noise Budget
• Allocates gross noise margin to expected sources of noise
• Sources: supply noise, cross talk, interference, offset
• Differentiate between fixed and proportional noise sources
M. Chowdhury @ UIC 33
 Key Reliability Properties

• Absolute noise margin values are deceptive

– a floating node is more easily disturbed than a node
driven by a low impedance (in terms of voltage)
• Noise immunity is the more important metric – the
capability to suppress noise sources
• Key metrics: Noise transfer functions, Output impedance
of the driver and input impedance of the receiver;

M. Chowdhury @ UIC 34
 Fan-in and Fan-out
Fan-out: The fan-out denotes the number of
load gates N that are connected to the output of
a driving gate.
N
• Generally increasing fan-out affects the
logic output levels
• With higher fan-out the driving gate sees
more capacitive load and suffers from
higher propagation delay Fan-out N

Fan-in: The fan-in of a gate is the number of

inputs to the gate from static perspective
• Gates with large fan-in tend to be more M
complex, which results in poor static and
dynamic properties.

Fan-in M
M. Chowdhury @ UIC 35
 The Ideal Gate

V out

Ri = ∞
Ro = 0
Fanout = ∞
g=∞
NMH = NML = VDD/2

V in

M. Chowdhury @ UIC 36
 An Old-time Inverter
5.0

4.0 NM L

3.0
( V )

V
o u t

2.0
VM
NM H
1.0

0.0 1.0 2.0 3.0 4.0 5.0

V in (V)

M. Chowdhury @ UIC 37
 Metrics for Evaluating Integrated Circuit
Speed or Performance: the computational ability of a integrated circuit
– Example: The number of instructions per second for a microprocessor
– Speed is determined by the propagation delay and operating frequency
– Performance metric depends on
• The architecture of the processor or the integrated circuit
• The design of the logic, and clock generation and distribution circuits
– From design point of view performance is expressed by maximum
achievable clock frequency, which depends on
• Propagation delay: Time for signal to propagate through the logic gate
• Delay and uncertainty of the clock signal line
– Propagation delay: Defines how quickly a gate responds to a change at
the input of the gate.
• It expresses the delay experienced by a signal when passing through the gate
• It is measured between 50% transition points of the input and output signal

M. Chowdhury @ UIC 38
 Propagation Delay Continued….
• measured between 50% transition points of the input and output signal
in out
Logic
gate Rise/fall time: defined as the time
vin
between the 10% and 90% points of the
50%
t
signal
vout
tpHL tpLH Rise/fall time depends on
90% • Strength of the driving gate
50% t
10%
tf tr
• The load presented to the signal

• Gates display different response times for rising and falling input waveforms:
• tpLH: response time for low-to-high transition
• tpHL: response time for high-to-low transition
Propagation delay tp = ( tpLH + tpHL)/2
• Propagation delay depends on
• Circuit technology and complexity
• Slopes or the rise and fall times of signal, which express how fast a signal
transits between the different levels
M. Chowdhury @ UIC 39
 Metrics for Evaluating Integrated Circuit
Power and Energy Consumption: Energy consumed per operation of the
integrated circuit influence following design issues:
– Power supply capacity
– Battery lifetime
– Supply line sizing
– Packaging
– Heat dissipation and cooling
• Different measures of power consumption
– Instantaneous power: p(t) = v(t)i(t) = Vsupplyi(t)
– Peak power: Ppeak = Vsupplyipeak
• for supply line sizing
– Average power:
1 t +T Vsupply t +T
Pave = ∫ p (t )dt = ∫ isupply (t )dt
T t T t
• for cooling or battery life time
M. Chowdhury @ UIC 40
 Metrics for Evaluating Integrated Circuit
Different types of power dissipation in IC:
• Static power: due to leakage, and static conductive path between supply rails
– Static power dissipation is always present
– It does not depend on switching activities
• Dynamic power: Transient power dissipated during the switching, temporary current path
between the supply rails
– Depends on switching frequency
• Short-Circuit Power: Power consumed due the direct or short-circuit path between supply and
ground during the brief period of switching

Power and Delay Product (PDP): For a given technology the product of power consumption
and propagation delay is generally a constant
• Power-Delay Product (PDP) = E = Energy per operation = Pav × tp
– Propagation delay is determined by the speed at which a given amount of energy can be
transferred
– Power consumption is determined by the rate of energy transfer
– Faster transfer of energy indicates higher power consumption but lower propagation delay
• Energy-Delay Product (EDP) = quality metric of gate = E × tp
M. Chowdhury @ UIC 41
 Metrics for Evaluating Integrated Circuit
• Cost of Integrated Circuits:
– Fixed or nonrecurring cost (NRC)
– Variable or recurring cost
• Fixed cost: independent of the manufacturing and sales volume
– Design cost
• Design time and effort, mask generation
• Complexity of design
• Aggressiveness of the specification
• Productivity of the designer
– Research and development
– Company’s overhead cost: equipment, infrastructure, sales and marketing
• Variable cost: manufacturing cost directly proportional to product volume
– silicon processing, packaging, testing
– proportional to volume
– proportional to chip area

M. Chowdhury @ UIC 42
 Cost of IC continued……
NRE Cost is Increasing

M. Chowdhury @ UIC 43
 Die Cost

Single die

Wafer

Going up to 12” (30cm)

M. Chowdhury @ UIC 44
 Cost per Transistor

cost:
¢-per-transistor
1
0.1 Fabrication capital cost per transistor (Moore’s law)
0.01
0.001
0.0001
0.00001
0.000001
0.0000001
1982 1985 1988 1991 1994 1997 2000 2003 2006 2009 2012

M. Chowdhury @ UIC 45
 Cost of IC continued……
fixed cost
Cost per IC = variable cost per IC +
volume
cost of die + cost of die test + cost of packaging
Variable cost =
final test yield

cost of wafer
cost of die =
dies per wafer X die yield

π × ( wafer diameter / 2) 2 π × wafer diameter

dies per wafer = −
die area 2 × die area

M. Chowdhury @ UIC 46
 Cost of IC continued……
Yield: No. of good chips per wafer
Y= × 100%
Total number of chips per wafer

Defects:

−α
⎛ defects per unit area × die area ⎞
die yield = ⎜1 + ⎟
⎝ α ⎠
ƒ α depends on the complexity of the manufacturing process
ƒ For current process α = 3 is a good estimate

die cost = f (die area)4

M. Chowdhury @ UIC 47
 Cost of IC continued……
cost of wafer
cost of die =
dies per wafer X die yield

dies per wafer X die yield = functional or defect-free die per wafer

π × ( wafer diameter / 2) 2 π × wafer diameter

dies per wafer = −
die area 2 × die area
−α
⎛ defects per unit area × die area ⎞
die yield = ⎜1 + ⎟
⎝ α ⎠

die cost = f (die area)4

M. Chowdhury @ UIC 48
 Cost of IC continued……
• Current trend: larger IC for better functionality and speed

• Die cost is proportional to the fourth power of the area

• Area is the prime metric of cost
• The smaller the gate the smaller is the die size
• Smaller gate is also faster and less energy consuming
• Therefore, smaller area is most desirable property for digital gate

• Factors that determine area:

• Number transistors per gate is a indicative of the implementation area
• Interconnect pattern also influences area
• Simplicity and regularity of design is the most desirable

M. Chowdhury @ UIC 49
 Summary
• Digital integrated circuits have come a long way and still
have quite some potential left for the coming decades
• Some interesting challenges ahead
– Getting a clear perspective on the challenges and
potential solutions is the purpose of this book
• Understanding the design metrics that govern digital
design is crucial
– Cost, reliability, speed, power and energy dissipation

M. Chowdhury @ UIC 50
 Problem
• Given the information about a semiconductor process
– Wafer diameter = 20 cm
– Area of a die = 2.5 cm2
– Process parameter α = 3
– Defects per unit area = 1/cm2
1. How many dies will be obtained per wafer?
2. How many dies will be functional or defect free per wafer?
3. What will be the cost of a die if the whole wafer costs $50?
Solution:
1. Directly use “dies per wafer” formula
2. Find the yield of the process using “yield” formula. Multiply “dies per
wafer” by “yield”
3. Use “cost of die” formula

M. Chowdhury @ UIC 51