EE105 – Fall 2014

Microelectronic Devices and Circuits

Prof. Ming C. Wu
wu@eecs.berkeley.edu
511 Sutardja Dai Hall (SDH)

Lecture 9: MOSFET (2): Scaling, DC bias 1

NMOS Transistor Capacitances:

Saturation Region

• Drain no longer connected to channel

2
CGS = CGC + CGSOW CGD = CGDOW
3

Lecture 9: MOSFET (2): Scaling, DC bias 2

1
 SPICE Model for NMOS Transistor

Typical default values used by SPICE:

KP = 50 or 20 µA/V2
γ=0
λ=0
VTO = 1 V
µn or µp = 500 or 200 cm2/V-s
2ΦF = 0.6 V
CGDO = CGSO = CGBO = CJSW = 0
Tox= 100 nm

Lecture 9: MOSFET (2): Scaling, DC bias 3

MOS Transistor Scaling

• All physical dimensions shrinks by a factor of α
• All voltages (including threshold voltage) reduced by α also
– Constant field scaling
• Drain current: εox W α " vGS VTN vDS % vDS iD
iD* = µ n $ − − ' =
Tox α L α # α α 2α & 2α α

• Gate Capacitance: CGC

* εox ! W $! L $ CGC
* "
= Cox W * L* = ( ) # &# & =
Tox α " α %" α % α

• Circuit delay in a logic circuit.

ΔV * CGC ΔV / α τ
τ * = CGC
*
= =
iD* α iD / α α

Lecture 9: MOSFET (2): Scaling, DC bias 4

2
 MOS Transistor Scaling
Scale Factor α (cont.)
• Circuit and Power Densities:
VDD iD P
P * = VDD
* *
iD = =
α α α2
P* P* P α2 P
*
= * *
= = extremely important result!
A W L (W α )( L α ) A

• Power-Delay Product:
P τ PDP
€ PDP * = P *τ * = = 3
α2 α α
• Cutoff Frequency:
gm µ
€ ωT = = 2n (VGS − VTN )
CGC L
– fT improves with square of channel length reduction

€
Lecture 9: MOSFET (2): Scaling, DC bias 5

Impact of Velocity Saturation

• At low electric field, electron
velocity is proportional to field
• At high electric field, the velocity
reaches a maximum called
saturation velocity, vSAT
"
Cox W
iD = (vGS −VTN ) vSAT
2
• The drain current is proportional
to (vGS – VTN) rather than its
square
• There are (many) other
corrections to the basic model
when the channel become very
short
– Interested, take EE130

Lecture 9: MOSFET (2): Scaling, DC bias 6

3
 NMOSFET in OFF State
• We had previously assumed that there is no channel current
when vGS < VTN. This is incorrect!
• As vGS is reduced (toward 0 V) below VTN, the potential
barrier to carrier diffusion from the source into the channel
is increased.
• The drain current ID is limited by carrier diffusion into the
channel, rather than by carrier drift through the channel.
• This is similar to the case of a PN junction diode!
– ID varies exponentially with the potential barrier height
at the source, which varies directly with the channel
potential.

Lecture 9: MOSFET (2): Scaling, DC bias 7

Sub-Threshold Leakage Current

• In the depletion (sub-threshold) region of operation, the
channel potential is capacitively coupled to the gate
potential. A change in gate voltage (ΔvGS) results in a
change in channel voltage (ΔvCS):

# ΔV &
iD ∝ exp % CS ( Similar to pn junction diode!
$ VT '
# C & C
ΔVCS = ΔVGS × %% ox
(( ≡ ΔVGS / m, m = 1+ dep >1
C
$ ox + C dep ' Cox
Sub-threshold slope (also called sub-threshold swing):
−1
# d(log10 I DS ) &
S ≡% (
$ dVGS '
S = mVT ln(10) > 60mV/dec

Lecture 9: MOSFET (2): Scaling, DC bias 8

4
 MOS Transistor Scaling (cont.)
VDD
Fixed
Subthreshold • Sub-threshold Conduction:
Slope
– iD decreases exponentially for
ON state vGS < VTN.
current – Reciprocal of the slope in
mV/decade gives the turn-off
rate for the MOSFET.
– Fundamental limit of MOSFET
sub-threshold slope:
60mV/decade
Leakage current

Lecture 9: MOSFET (2): Scaling, DC bias 9

Mask Sequence
Polysilicon-Gate Transistor
• Mask 1: Defines active area or
thin oxide region of transistor
• Mask 2: Defines polysilicon
gate of transistor, aligns to
mask 1
• Mask 3: Delineates the contact
window, aligns to mask 2.
• Mask 4: Delineates the metal
pattern, aligns to mask 3.
• Channel region of transistor
formed by intersection of first
two mask layers. Source and
Drain regions formed
wherever mask 1 is not
covered by mask 2

Lecture 9: MOSFET (2): Scaling, DC bias 10

5
 Basic Ground Rules for Layout

• Design of large circuits can be

simplified with simple rules
• Minimum feature size: F = 2 Λ
• Minimum alignment between
different features: T = Λ
• Λ could be 1, 0.5, 0.25 µm, etc.

• In this example:
– W/L = 10Λ / 2Λ = 5
– Transistor Area = 120 Λ2

Lecture 9: MOSFET (2): Scaling, DC bias 11

MOSFET Biasing
• ‘Bias’ sets the dc operating point.
• The ‘signal’ is actually comprised of relatively small changes in
the voltages and/or currents.
• Remember (Total = dc + signal): vGS = VGS + vgs and iD = ID + id

Lecture 9: MOSFET (2): Scaling, DC bias 12

6
 Bias Analysis - Example 1:
Constant Gate-Source Voltage Biasing

VDD = I D RD + VDS
VDS = 10V − (50 µA)(100K ) = 5.00 V

• Check:VDS > VGS-VTN. Hence

€ saturation region assumption
Since IG = 0, is correct.
VEQ = IG REQ + VGS = VGS • Q-pt: (50.0 mA, 5.00 V) with
Kn 2
VGS= 3.00 V
ID =
2
(VGS − VTN )
• Discussion: The Q-point of
25x10 −6 A 2 this circuit is quite sensitive
ID =
2 V2
(3 −1) V 2 = 50.0 µA to changes in transistor
characteristics, so it is not
widely used.
€
Lecture 9: MOSFET (2): Scaling, DC bias 13

Bias Analysis Using Load Line

VDD = I D RD + VDS
10 = 105 I D + VDS
For VDS = 0, ID = 100 uA
Check: The load line approach agrees
For ID = 0, VDS = 10 V
with previous calculation.
€ Plotting the line on the transistor Q-pt: (50.0 mA, 5.00 V) with VGS = 3.00 V
output characteristic yields Q-pt at
Discussion: Q-pt is clearly in the
intersection with VGS = 3V device saturation region. Graphical load line is
curve. good visual aid to see device operating
region.

Lecture 9: MOSFET (2): Scaling, DC bias 14

7
 Bias Analysis - Constant Gate-Source Voltage Biasing with
Channel-Length Modulation

Kn 2
ID = (V − VTN ) (1+ λVDS )
2 GS
VDS = VDD − I D RD
25x10 −6 2
VDS = 10 −
2
( )
105 (3 −1) (1+ 0.02VDS )

VDS = 4.55 V
25x10 −6 2
ID =
2
[ ]
(3 −1) 1+ 0.02(4.55) = 54.5 µA

Check: VDS > VGS - VTN. Hence the Discussion: The bias levels have
€ saturation region assumption is changed by about 10% (54.5 µA
correct. vs 50 µA). Typically, component
values will vary more than this,
Q-pt: (54.5 mA, 4.55 V) with
so there is little value in
VGS = 3.00 V
including λ effects in most
circuits.

Lecture 9: MOSFET (2): Scaling, DC bias 15

Bias Analysis - Example 6:

Two-Resistor Feedback Biasing

Kn 2
VGS = VDD −
2
(VGS − VTN ) RD

2.6x10 −4 2
VGS = 3.3 −
2
( )
10 4 (VGS −1)

VGS = −0.769 V or + 2.00 V

Since VGS < VTN for VGS = -0.769 V,

the MOSFET would be cut-off,
€
∴VGS = +2.00 V and I D = 130 µA
Assumption: IG = IB = 0, transistor is
saturated (since VDS = VGS ) VDS > VGS-VTN. Hence saturation
Analysis: VDS = VDD - IDRD region assumption is correct.
€
Q-pt: (130 µA, 2.00 V)

Lecture 9: MOSFET (2): Scaling, DC bias 16

8
 Bias Analysis - Example 6:
Two-Resistor Feedback Biasing

Kn 2
VGS = VDD − (V − VTN ) RD
2 GS
2.6x10 −4 2
VGS = 3.3 −
2
( )
10 4 (VGS −1)

VGS = −0.769 V or + 2.00 V

Since VGS < VTN for VGS = -0.769 V,

the MOSFET would be cut-off,
€
∴VGS = +2.00 V and I D = 130 µA
Assumption: IG = IB = 0, transistor is
saturated (since VDS = VGS )
VDS > VGS-VTN. Hence saturation
Analysis: VDS = VDD - IDRD region assumption is correct.
€
Q-pt: (130 µA, 2.00 V)

Lecture 9: MOSFET (2): Scaling, DC bias 17

Bias Analysis –
Two-Resistor biasing for PMOS Transistor
Assumption: IG = IB = 0;
transistor is saturated
Analysis:
VGS − I G RG −VDS = 0 → VDS = VGS
VDD +VDS − I D RD = 0
Kn 2
VDD +VGS − (VGS −VTP ) RD = 0
2
5x10 −5 2
15 +VGS − ( 2.2x10 5 ) (VGS + 2) = 0
2
VGS = −0.369 V or − 3.45 V V > V −V
DS GS TP
Since VGS = −0.369 > VTP , VGS = −3.45 V
Hence
€
saturation assumption is
correct.
I D = 52.5 µ A and VDS = −3.45 V
Q-pt: (52.5 µA, -3.45 V)
€

Lecture 9: MOSFET (2): Scaling, DC bias 18