This document describes the design and implementation of a 16-bit reversible Arithmetic Logic Unit (ALU) with 15 operations using reversible logic gates. Single-bit reversible ALUs are first designed and then 16 are cascaded together. The ALU uses Double Peres, Fredkin, Toffoli, and DKG gates and can perform operations like AND, OR, addition, increment, and decrement. Block and schematic diagrams of the reversible 1-bit and 16-bit ALU designs are presented along with simulation results verifying the design meets specifications of reversible logic. The ALU is concluded to improve features over previous designs by supporting more operations and a wider bit-width while being implemented using Verilog for Xilinx
This document describes the design and implementation of a 16-bit reversible Arithmetic Logic Unit (ALU) with 15 operations using reversible logic gates. Single-bit reversible ALUs are first designed and then 16 are cascaded together. The ALU uses Double Peres, Fredkin, Toffoli, and DKG gates and can perform operations like AND, OR, addition, increment, and decrement. Block and schematic diagrams of the reversible 1-bit and 16-bit ALU designs are presented along with simulation results verifying the design meets specifications of reversible logic. The ALU is concluded to improve features over previous designs by supporting more operations and a wider bit-width while being implemented using Verilog for Xilinx
This document describes the design and implementation of a 16-bit reversible Arithmetic Logic Unit (ALU) with 15 operations using reversible logic gates. Single-bit reversible ALUs are first designed and then 16 are cascaded together. The ALU uses Double Peres, Fredkin, Toffoli, and DKG gates and can perform operations like AND, OR, addition, increment, and decrement. Block and schematic diagrams of the reversible 1-bit and 16-bit ALU designs are presented along with simulation results verifying the design meets specifications of reversible logic. The ALU is concluded to improve features over previous designs by supporting more operations and a wider bit-width while being implemented using Verilog for Xilinx
This document describes the design and implementation of a 16-bit reversible Arithmetic Logic Unit (ALU) with 15 operations using reversible logic gates. Single-bit reversible ALUs are first designed and then 16 are cascaded together. The ALU uses Double Peres, Fredkin, Toffoli, and DKG gates and can perform operations like AND, OR, addition, increment, and decrement. Block and schematic diagrams of the reversible 1-bit and 16-bit ALU designs are presented along with simulation results verifying the design meets specifications of reversible logic. The ALU is concluded to improve features over previous designs by supporting more operations and a wider bit-width while being implemented using Verilog for Xilinx
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Design and Implementation 16 BIT
REVERSIBLE LOGIC ALU with 15-
Operations abstract • Reversible logic is one of the emerging technologies having promising applications in quantum computing. This project will deal with the design of a 16 bit reversible Arithmetic Logic Unit (ALU) with 15 operations is presented by making use of Double Peres gate, Fredkin gate, Toffolli gate, DKG gate and NOT gate. A new VLSI architecture for ALU using reversible logic gates is proposed. ALU is one of the most important components of CPU that can be part of a programmable reversible computing device such as a quantum computer. A first single bit reversible ALU and second single bit ALU are designed and Then 16 single bit ALU’s are cascaded together taking carry out of ALU performing LSB operation as an input to carry in of ALU performing next LSB operation. Introduction • Design of a control unit for any computing unit is the toughest part and involves more critical constraints. Power consumption is an important issue in modern day VLSI designs. • The advancement in VLSI designs and particularly portable device technologies and increasingly high computation requirements, lead to the design of faster, smaller and more complex electronic Systems Cont.… • The advent of multi-giga-hertz processors, high-end electronic gadgets bring with them an increase in system complexity, high density packages and a concern on power concumption • Power optimization can be done at various abstraction levels in CMOS VLSI design. ALU • In computing, an arithmetic and logic unit (ALU) is a digital circuit that performs arithmetic and logical operations. • Mathematician John von Neumann proposed the ALU concept in 1945. • . The processors found inside modern CPUs and graphics processing units (GPUs) accommodate very powerful and very complex ALUs; Cont.… • Most of a processor's operations are performed by one or more ALUs. An ALU loads data from input registers. Then an external control unit tells the ALU what operation to perform on that data, and then the ALU stores its result into an output register. • Engineers can design an Arithmetic Logic Unit to calculate most COMPLEX operations SO ALU takes more space in a cpu and it concumes more power. Cont.… • Therefore engineers make the ALU powerful enough to make the processor fast yet not so complex as to become prohibitive. • Ex: ALU takes single step to calculate the square root of any number. REVERSIBLE GATES • Reversible computing is a model of computing where the computational process to some extent is reversible, i.e., time-invertible. • A necessary condition for reversibility of a computational model is that the relation of the mapping states of transition functions to their successors should at all times be one-to- one Reversible circuits • Reversible logic circuits have been first motivated in the 1960 • More generally, reversible gates have the same number of inputs and outputs. • To implement reversible computation, estimate its cost, and to judge its limits, it is formalized it in terms of gate-level circuits Cont.… • For example, the inverter (logic gate) (NOT) gate is reversible because it can be undone • . The exclusive or (XOR) gate is irreversible because its inputs cannot be unambiguously reconstructed from an output value Cont.… • 1. NOT Gate • The Reversible 1*1 gate is NOT Gate with zero Quantum Cost is as shown in the Fig. 1. Cont.… • In the design of reversible logic circuits the following points must be considered to achieve an optimized circuit. They are • Fan-out is not permitted. • Loops or feedbacks are not permitted • Garbage outputs must be minimum • Minimum delay • Minimum quantum cost. SOME OF REVERSIBLE GATES: • Fredkin gate • The Fredkin gate (also CSWAP gate) is a computational circuit suitable for reversible computing, invented by Ed Fredkin. It is universal, which means that any logical or arithmetic operation can be constructed entirely of Fredkin gates. The Fredkin gate is the three-bit gate that swaps the last two bits if the first bit is 1. DESIGN & IMPLEMENTATION Reversible ALU’s • The ALU that is proposed is 15-operations. There ALU has 2 parts. 1st which has Double Peres Gate as base of the circuit and is selected when select line s3 is zero. The operations performed here are buffer, AND, OR,NAND, NOR, EX-OR, and EX-NOR. 2nd part has DKG Gate as base of the circuit and is selected when select line s3 is one. • The operations performed here are add, increment, 2’s complement, set, subtract, decrement, not, and clear. • The operations selected depending on various select line are shown in the table Cont.… Block diagram of reversible ALU1 Block diagram of reversible ALU design 2: Block diagram of reversible 16 bit ALU : RTL SCHEMATIC Cont.… TECHNOLOGY SCHEMATIC Cont.… Design summary Simulation Result for Top:tb: Simulation Result for design1: Simulation Result for design2:tb Simulation Result for design2: CONCLUSION • This 16-bit reversible Alu is designed and implemented in Verilog using XILINX 14.4. • The main aim of the design in this paper is improve the ALU features by increasing it to 15-operations and increase widthto 16-bit. • For further research this ALU can be extended to 32-bit and 64-bit and more features can also be added. • This design is verified using Verilog which has constrains of input to output one-way functionality, if we can design the reversible logic circuit using tools which support 2-way functionality the reversible logic result can be simulated and analysed in much better. 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