Microprocessors

AIM

To have an in depth knowledge of the architecture and 16-bit

Microprocessors, Microcontrollers and to study how to interface various
peripheral devices with them.
 Module 1

Module 1 - The Processors : 8086

Register Organization of 8086, Architecture, Signal Description of 8086, Physical Memory

Organization, General Bus Operation, I/O Addressing Capability, Special Processor
Activities, Minimum Mode 8086 System and Timings, Maximum Mode 8086 System and
Timings. Addressing Modes of 8086.

.
 A microprocessor is a computer processor which incorporates the
functions of a computer's central processing unit (CPU) on a single
integrated circuit (IC).

 It is a multipurpose, clock driven, register based, programmable electronic

device which accepts digital or binary data as input, processes it according
to instructions stored in its memory, and provides results as output

 The integration of a whole CPU onto a single chip or on a few chips greatly
reduced the cost of processing power

 A minimal microprocessor might only include an arithmetic logic unit (ALU)

and a control logic section.
•The first 4-bit microprocessor was introduced in 1971 by Intel (named 4004).

•In 1972, Intel created the 8-bit microprocessor 8008

•In 1974, Intel launched the first general purpose 8-bit microprocessor 8008

•This microprocessor was used on the world's first personal computer, named
Altair.

•Followed by 8085 with more added features in architecture

•Main limitation of 8-bit processor was low speed, low memory addressing
capability, limited number of general purpose registers, and less powerful
instruction set

•8086 was launched in 1978 which is a 16-bit microprocessor

 Intel 8086 Microprocessor

 Register Organization of 8086

 Architecture

 Signal Description of 8086

 Physical Memory Organization

 General Bus Operation

 I/O Addressing Capability

 Special Processor Activities

 Minimum Mode 8086 System and Timings

 Maximum Mode 8086 System and Timings.

 Addressing Modes of 8086

Register Organization of 8086
 Registers

General Purpose Index

AH AL
BP
AX

SP
BH BL
BX
SI

CH CL
DI
CX

DH DL
DX Segment

CS

Status and Control SS

Flags DS

IP ES
 Registers

 Classified as General purpose registers and Special purpose registers

 General purpose registers can be used as either 8-bit or 16-bit

 Used for holding data, variables and intermediate results or as counter

or for storing offset address for some addressing modes

 Special purpose registers are used as segment registers, pointers,

index registers
 Registers

AX, BX, CX and DX are two

bytes wide and each byte can
be accessed separately

These registers are used as

memory pointers.

Contain results of
ALU computations

Segment registers are used as base

Address for a segment in the 1 Mbyte
of memory which is divided into
16 logical segments each containing
64 K bytes of memory
 Registers

• General Data Registers

• Hold data for an operation to be performed
• 16 bit registers
• There are 4 data registers (AX, BX, CX, DX)
• Low and High bytes of the data registers can be accessed
separately
– AH, BH, CH, DH are the high bytes
– AL, BL, CL, and DL are the low bytes
• Data Registers are general purpose registers but they also
perform special functions
 General Purpose Registers
• AX
– Used as 16 bit Accumulator Register
– Preferred register to use in arithmetic, logic and data transfer
instructions because it generates the shortest Machine Language Code
• BX
– Base Register
– Also serves as an address register to store offset for forming physical
address.
• CX
– Count register in string instructions
– Used as a loop counter
• DX
– Data register
– Used as implicit operand or destination in few instructions
• Segment Registers
• Hold the address of an instruction or data element
• Segment registers (CS, DS, ES, SS)
• Code Segment Register(CS)
• Addressing memory location in code segment where
executable program is stored
• Data Segment Register(DS)
• Addressing memory location in data segment where data
is resided
• Extra Segment Register(ES)
• Essentially another data segment
• Stack Segment Register(SS)
• Addressing stack segment of memory
• Pointer and Index Registers
• Pointer registers (SP, BP, IP)
• Contain the offset addresses of memory locations
• SP: Stack pointer
– Used with SS to access the stack segment
• BP: Base Pointer
– Primarily used to access data on the stack
– Can be used to access data in other segments
• IP: Instruction Pointer
• Contain offsets within the code
 Pointer and Index Registers

• Index registers (SI, DI)

• General purpose registers as well as offset storage for indexed, base
indexed and relative based indexed addressing modes
• SI: Source Index register
– The register SI is used to store the offset of source data in DS.
• DI: Destination Index register
– The DI register is used to store the offset of destination in DS or ES
• The SI and the DI registers may also be used to access data
stored in arrays
• Status register
• Keeps the current status of the processor
• On an IBM PC the status register is called the FLAGS register
– In total there are fourteen 16-bit registers in an 8086/8088
 Intel 8086 Microprocessor

 Register Organization of 8086

 Architecture

 Signal Description of 8086

 Physical Memory Organization

 General Bus Operation

 I/O Addressing Capability

 Special Processor Activities

 Minimum Mode 8086 System and Timings

 Maximum Mode 8086 System and Timings.

 Addressing Modes of 8086

8086 ARCHITECTURE DIAGRAM
 8086 ARCHITECTURE
The 8086 has two parts,
 Bus Interface Unit (BIU)
 Circuitry for physical address calculation and a predecoding instruction byte queue

 Execution Unit (EU).

 The BIU fetches instructions, reads and writes data, and computes the 20-bit address.
 Opcode is fetched by the BIU
 The EU decodes and executes the instructions using the 16-bit ALU.
 BIU along with EU thus forms a pipeline.

The BIU contains the following registers:

IP - the Instruction Pointer

CS - the Code Segment Register
DS - the Data Segment Register
SS - the Stack Segment Register
ES - the Extra Segment Register
 PROGRAM MODEL
8086 Programmer’s Model

ES Extra Segment
BIU registers
(20 bit adder) CS Code Segment
SS Stack Segment
DS Data Segment
IP Instruction Pointer

EU registers AX AH AL Accumulator
BX BH BL Base Register
CX CH CL Count Register
DX DH DL Data Register
SP Stack Pointer
BP Base Pointer
SI Source Index Register
DI Destination Index Register
FLAGS
 While the fetched instruction is executed internally, the
external bus is used to fetch the machine code of the
next instruction and arrange it in a queue called as
predecoded instruction byte queue.
 This is a 6 byte long queue, works in first-in first-out
policy.
 While the opcode is fetched by the bus interface unit
(BIU), the execution unit (EU) executes the previously
decoded instruction concurrently.
 The CPU 8086 is able to address 1
Mbytes of physical memory.
 The compete 1 Mbytes memory can
be divided into 16 segments, each of
64 Kbytes size.
 The addresses of the segment may
be assigned as 0000H to F000H
respectively.
 The offset values are from 0000H to
FFFFH.
 If the segmentation is done as per
above mentioned way, the segments
are called non-overlapping segments.
 In some cases segment may overlap
also. Suppose a segment starts at a
particular address and its maximum
size can go up to 64 Kbytes. But if
another segment starts before this
64 Kbytes location of the first
segment, the two segments are said
to be overlapping segment.
 The area of memory from the start of
the second segment to the possible
end of the first segment is called as
overlapped segment.
FLAG REGISTER
FLAG REGISTER
Signal Description of 8086
 8086 is a 16 bit CPU

 Available in 3 clock rates-5,8,10MHz

 40 pin package

 Categorized into three groups

 Signals having common functions in minimum as well as maximum mode

 Signals having special functions in minimum mode

 Signals having special functions in maximum mode

 Minimum and Maximum

AD15 – AD0:
Address/Data bus lines. These are multiplexed lines.
Address remains in lines during T1 state
Data remains in lines during T2,T3,Tw,T4 states
A19/S6 – A16/S3:
Address/Status bus bits are multiplexed to provide
address signals A19-A16 and status bits S6-S3.
S6 – always remains 0
S5 – indicates the condition of the interrupt flag
S4 and S3 – Indicate the segment being accessed
during current bus cycle.

34
RD:
When this read signal pin is at logic 0, the data bus is
receptive to data from memory or I/O devices.

READY:
This pin is used to enforce a waiting state.
READY pin at 0 – the microprocessor goes into idle
state.
READY pin at 1 – the microprocessor does normal
operation.

35
 INTR:
Interrupt request pin is used to request a
hardware interrupt.
INTA becomes active when interrupt is being
serviced.

TEST:
Test pin is an input that is tested by the WAIT instruction.
If the test pin is at logic 0, execution will continue.
If the test pin is at logic 1, processor remains in an idle state

36
NMI:
Non-maskable interrupt input is similar to
INTR expect that the NMI interrupt does not
check priority.

RESET:
If this reset pin is held high the microprocessor
terminate the current activity and It begins execution
from memory location FFFF0H.

CLK:
The clock pin is used to connect a clock generator

37
Vcc:
The power supply. +5V should be
connected to this pin.

GND:
The ground connection for the microprocessor.

MN/MX:
The minimum/maximum mode pin selects
the mode for the processor.
Minimum- single processor
Maximum - multiprocessor

38
BHE/S7:
The bus high enable pin is used in the 8086 to
enable the Most significant data bus bits(D15-D8)
during a read or write operation.
S7 is not currently used

BHE A0 Indication
0 0 Whole word
0 1 Upper byte from or to odd address
1 0 Lower byte from or to even address
1 1 None

39
 Pin Connections ( Minimum)

IO/M
This pin indicates whether the address bus
contains a memory address or an I/O port
address.

WR:
The write line is used when the
microprocessor is writing data to memory
and the memory bus contains a valid
address.

40
INTA:
Interrupt acknowledgement signals is a response to INTR input pin.

ALE:
Address Latch enable shows whether the multiplexed AD lines carry address
or data.

DT/R:
Data transmit/receive shows that the microprocessor data bus is
transmitting(1) or receiving(0) data. This is used to control buffers.

41
DEN:
Data Enable bus indicates the availability of valid data on the address/data
lines.

HOLD,HLDA:
HOLD pin is used to input request DMA.
Hold set to 1 microprocessor gives up control of buses to DMA controller.
The processor issues the hold acknowledge signal on HLDA pin

42
 Maximum Mode Pins

S2, S1 and S0:

These signal bits indicate the function of the current bus cycle.
These becomes active during T4 of the previous cycle and remain active
during T1 and T2 of the current bus cycle

S2 S1 S0 Indication
0 0 0 Interrupt Acknowledge
0 0 1 Read I/O port
0 1 0 Write I/O port
0 1 1 Halt
1 0 0 Code Access
1 0 1 Read Memory
1 1 0 Write Memory
1 1 1 Passive 43
 Maximum Mode Pins

RQ/GT1 and RQ/GTO:

Requests/grants pins used by other local bus masters to force the processor to
release the local bus.
Request- a pulse one clock wide. Response - a pulse one clock wide during
T4(current) or T1 (next)

LOCK:
Lock output is used to lock peripherals off the system.

QS0 and QS1: QS1 QS2 Indication

Queue status bits 0 0 No operation
show the status of the 0 1 First byte of opcode from the queue
code prefetch queue.
1 0 Empty queue
1 1 44from the queue
Subsequent byte
Physical Memory Organization

BHE A0 Indication
0 0 Whole word
0 1 Upper byte from or to odd address
1 0 Lower byte from or to even address
1 1 None
45
Addressing Modes of 8086
 Immediate
 the data is provided in the instruction

MOV AX, 0005H

 Direct
 the memory address of the operand is in the
instruction

MOV AX,[5000H]
Effective address: 10*DS+5000
 Register
 operand is in a register

MOV BX, AX
 indirect
 instruction specifies a register containing an
address, where data is located.
 Offset address is in SI, DI, or BX.
 Segments are DS or ES

MOV AX, [BX]

Data is present in a memory location in DS whose
offset is in BX. Effective address: 10*DS+[BX]
 Indexed
 Offset of the operand is in one of the index register
SI or DI
 Segment is DS

MOV AX,[SI]
Here data is available at an offset address stored in SI in
DS. The effective address is computed as 10 *DS+SI
 Register Relative
 Effective address is formed by adding an 8-
bit or 16-bit displacement with registers
BX,BP,SI,DI in the default segment DS or ES

MOV AX,50H[BX]
Effective address: 10*DS+50H+[BX]
 Based Indexed
 Offset of the operand is obtained by adding the
contents of a base register (BX or BP) to the
contents of an index register SI or DI

MOV AX,[BX],[SI]
Effective address: 10*DS+[BX]+[SI]
 Relative Based Indexed
 Offset of the operand is obtained by adding
8-bit or 16-bit displacement to the contents of
a base register (BX or BP) and any one of
the index registers(SI or DI)

MOV AX,50H [BX] [SI]

Effective address: 10*DS+[BX]+[SI]+50H
 Two addressing modes for control transfer
Instruction,
 Intersegment – location to which control is to
be transferred lies in a different segment
 Intersegment Direct
 Intersegment Indirect
 Intrasegment – location to which control is to
be transferred lies in the same segment
 Intrasegment Direct
 Intrasegment Indirect
 Intrasegment Direct Mode
 address to which control is transferred
appears directly in the instruction as
immediate displacement value
 Displacement is relative to the content of IP
 Short jump – 8 bits : -128 to +127
 Long jump – 16 bits : -32768 to +32767

JMP SHORT LABEL

 Intrasegment Indirect Mode
 address to which control is transferred id
found in a register or memory location

JMP [BX]
 Intersegment Direct Mode
 CS and IP of the destination address to which
control is transferred appears directly in the
instruction

JMP 5000H:2000H
 Intersegment Indirect Mode
 address to which control is transferred is
passed to the instruction as contents of a
memory block containing 4 bytes ie. IP(LSB),
IP(MSB), CS(LSB), CS(MSB).
 Starting address of the memory block is
referred by any addressing mode except
immediate mode

JMP [2000H]
 Forming the Effective
Address
Example
Offset(displacement) = 5000H
[AX] – 1000H [BX] – 2000H
[SI] - 3000H [DI] – 4000H
[BP] – 5000H [SP] – 6000H
[CS] – 0000H [DS] – 1000H
[SS] – 2000H [IP] – 7000H
 Direct Addressing Mode
MOV AX,[5000]
 Register Indirect
MOV AX,[BX]
 Register Relative
MOV AX,5000 [BX]
 Based Indexed
MOV AX,[BX] [SI]
 Relative Based Indexed
MOV AX,5000 [BX] [SI]
I/O Addressing Capability
 I/O Addressing Capability

• Address up to 64K I/O byte registers or 32K word registers

• I/O address appears on address lines A0 to A15 for T1
• Upper lines A16 to A19 are 0

• 16 bit DX – 16 bit I/O address pointer

• 8 bit address
63
Special Processor Activities
1. Processor Reset and Initialisation
• RESET – 1 – reset
• It terminates the ongoing operation on the positive
edge of the reset signal.
• Until logic 0 is applied it remains in this state
• Register contents are set to 0000H, CS is set to
FFFFH
• For NMI request to be served it must appear after the
second clock cycle during reset initialization. Before
the second clock cycle,it will not be served.
• If a HOLD request appears , immediately after reset ,it
will be immediately served after initialization.
2. HALT
• Executes HLT instruction
• HLT state in two ways…
• Minimum mode – issues ALE pulse but no control
signal
• Maximum mode – it puts HLT status 011 on S2, S1
and S0 and then the bus controller issues an ALE
pulse with no qualifying signal
3. TEST and Synchronization with External Signals
• WAIT instruction-Processor preserves the content of
the registers, before execution of WAIT instruction.
• CPU wait for TEST input to go low
• If low it continues further execution
• While waiting – HOLD request will be served
• If interrupt occurs it fetches and executes the WAIT
instruction once more and serves the interrupt.
4. Deriving System Bus
• Multiplexed 16-bit address/data bus(AD0 – AD15)
• Multiplexed 4-bit address/status bus(A16/S3 – A19/S6)
• Address can be latched using ALE
• Data can be separated from address and buffered using
2 dimensional buffers 74245

• DEN and DT/R indicate the presence of data and the

direction of data.
• DEN low enables the buffers
• When DIR goes high the data available at X pins are
transferred to Y pins(write)
• When DIR goes low the data available at Y pins are
transferred to X pins(read)
Minimum mode 8086 system
Latches
Transreceivers
Thereare generally
isare
aThe
single buffered output
themicroprocessor
bidirectional
microprocessor inD-type
buffers(data
8086 the flip- in
is operated
minimum
amplifiers).
The system contains memory for the monitor and users
Theyflops like 74LS373.They
aremode
required
system.
minimum
to separate are
theused
The remaining
mode by for separating
validcomponents
data from thein the
time
program storage. Usually, EPROM are used for monitor
validsystem
address
multiplexed from
address/data
are thesignals.
strapping
latches, multiplexed
its address/data
transreceivers,
MN/MX
Theypinaretocontrolled
clock
logicgenerator,
1. by two
storage, while RAM for users program storage
signals
signals namely,
memoryDEN and I/Oanddevices.
DT/R
Read Cycle timing diagram
for Minimum Mode
The read cycle begins in T1 with the
assertion of address latch enable (ALE)
signal and also M / IO signal.

At T2, the address is removed from the

local bus and is sent to the output. The
read (RD) control signal is also activated
in T2..
After RD goes low, the valid data is
available on the data bus in T3.

At T4 RD goes high , the data is remov

from the bu
Write Cycle timing diagram
for Minimum Mode
Write cycle begins with the assertion
of ALE and emission of the address.

In T2 the processor sends the data

to be written
Data remains on the bus until the
middle ofT4 state.
WR becomes active at the
beginning of T2
 Bus Request and Bus
Grant in Minimum Mode

• HOLD pin is checked at the end of each clock cycle

• Before T4 of previous cycle or during T1 of current cycle – CPU
activates HLDA in next clock cycle
• When the request is dropped by the requesting master, HLDA is
dropped by the processor at the next clock
 Intel 8086 Microprocessor

 Register Organization of 8086

 Architecture

 Signal Description of 8086

 Physical Memory Organization

 General Bus Operation

 I/O Addressing Capability

 Special Processor Activities

 Minimum Mode 8086 System and Timings

 Maximum Mode 8086 System and Timings.

 Addressing Modes of 8086

Maximum mode 8086 system
Read Cycle timing diagram
for Maximum Mode
Write Cycle timing diagram
for Maximum Mode
 RQ/GT timing in Maximum
Mode

• Series of 3 pulses
• When the request is detected, processor issues a grant pulse during
T4(current) or T1(Next)
• After use, it sends a release pulse
General Bus Operation