Location via proxy:   [ UP ]  
[Report a bug]   [Manage cookies]                
Scribd Logo
Upload

Welcome to Scribd!

  • 142 views

    Instruction Level Parallelism (ILP)

    Uploaded by

    Ravi K R
    Instruction level parallelism (ILP) refers to executing multiple instructions simultaneously by exploiting parallelism between instructions that do not depend on each other. The document discusses different types and implementations of ILP including bit level, instruction level, loop level, and thread level parallelism. It also describes techniques used by hardware and compilers to identify and exploit parallel instructions such as pipelining, superscalar architectures, VLIW, and speculative execution.

    Copyright:

    © All Rights Reserved
    Download as PPT, PDF, TXT or read online from Scribd

    Instruction Level Parallelism (ILP)

    Uploaded by

    Ravi K R
    142 views9 pages
    Instruction level parallelism (ILP) refers to executing multiple instructions simultaneously by exploiting parallelism between instructions that do not depend on each other. The document discusses different types and implementations of ILP including bit level, instruction level, loop level, and thread level parallelism. It also describes techniques used by hardware and compilers to identify and exploit parallel instructions such as pipelining, superscalar architectures, VLIW, and speculative execution.

    Original Description:

    Instruction Level Parallelism (ILP)

    Original Title

    ILP

    Copyright

    © © All Rights Reserved

    Available Formats

    PPT, PDF, TXT or read online from Scribd

    Did you find this document useful?

    Is this content inappropriate?

    Instruction level parallelism (ILP) refers to executing multiple instructions simultaneously by exploiting parallelism between instructions that do not depend on each other. The document discusses different types and implementations of ILP including bit level, instruction level, loop level, and thread level parallelism. It also describes techniques used by hardware and compilers to identify and exploit parallel instructions such as pipelining, superscalar architectures, VLIW, and speculative execution.

    Copyright:

    © All Rights Reserved
    Download as PPT, PDF, TXT or read online from Scribd
    Download as ppt, pdf, or txt
    142 views9 pages

    Instruction Level Parallelism (ILP)

    Uploaded by

    Ravi K R
    Instruction level parallelism (ILP) refers to executing multiple instructions simultaneously by exploiting parallelism between instructions that do not depend on each other. The document discusses different types and implementations of ILP including bit level, instruction level, loop level, and thread level parallelism. It also describes techniques used by hardware and compilers to identify and exploit parallel instructions such as pipelining, superscalar architectures, VLIW, and speculative execution.

    Copyright:

    © All Rights Reserved
    Download as PPT, PDF, TXT or read online from Scribd
    Download as ppt, pdf, or txt
    of 9

    Instruction Level Parallelism

    (ILP)
    What is a parallel instruction?
    • ILP is a measure of the number of instructions that can
    be performed during a single clock cycle.
    • Parallel instructions are a set of instructions that do not
    depend on each other to be executed.
    ►Hierarchy
     Bit level Parallelism
    ► 16 bit add on 8 bit processor
     Instruction level Parallelism
     Loop level Parallelism
    ► for (i=1; i<=1000; i= i+1)
    x[i] = x[i] + y[i];
     Thread level Parallelism (SMT, multi-core
    computers)
    Loop-level parallelism exploits parallelism among
    iterations of a loop. A completely parallel loop
    adding two 1000-element arrays:

    Within an iteration there is no opportunity for overlap, but


    every iteration can overlap with any other iteration.
    The loop can be unrolled either statically by compiler or
    dynamically by hardware.

    Vector processing is also possible. Supported in DSP, graphics,


    and multimedia applications.
    Data Dependences
    Making Computers Think Parallel?

    •Human
    •Write code yourself, directly controlling
    each processor
    •Compiler
    •Let the compiler convert your sequential
    code into parallel instructions.
    •Hardware
    Implementations of ILP

    • Pipelining
    • Superscalar Architecture
    • Dependency checking on chip.
    • Multiple Processing Elements eg. ALU, Shift
    • Multi operation instructions requires a larger
    number of bits to encode
    • VLIW (Very Long Instruction Word Architecture)
    • Simple hardware, Complex Compiler
    • EPIC explicitly parallel instruction computer
    • Pipelining

    http://en.wikipedia.org/wiki/Image:Fivestagespipeline.png

    ► Superscalar

    http://en.wikipedia.org/wiki/Image:Superscalarpipeline.png
    Identifying parallel instructions

    • Hardware Techniques • Compiler Techniques


    • Out of order execution • Register Renaming
    • Window Size ADD $t0,$s1,$2
    • Speculative execution SW $t0, 0($s3)
    ADD $t0,s$4,$s5
    • Branch Prediction
    SW $t0, 0($s6)
    • Branch Fanout
    • Unrolling loops
    • Takes advantage of loop level
    parallelism
    References

    • http://en.wikipedia.org/wiki/Image:Fivestagespipeline.png
    • http://en.wikipedia.org/wiki/Image:Superscalarpipeline.png
    • http://www.cs.iastate.edu/~prabhu/Tutorial/PIPELINE/instrLevParal.html

    You might also like