ARM Has 7 Operating Modes ARM Has 7 Operating Modes: - Fa F Fa F

ñ ARM has 7 operating modes

-U
3 nprivileged mode nder which most tasks r n)
-Fa
F
3to handle high priority interr pt )
-

3entered when a low priority interr pt is raised )
-S SVC
3entered on reset or a software interr pt )
-Ab ABT
3 sed to handle memory access violation)
-U

UND
3 sed to handle ndefined instr ction)
-SySYS
| 3 ses same registers as ser mode)
DES
ñ Most application program r n in User Mode
ñ A program in ser mode is nable to access some

protected system reso rces or to change mode , other
than by ca sing exception
ñ Mode change can be by

-Software control
-External interr pts
-Exception processing
|
DES
ñ Modes other than ser mode are called {
ñ rivileged modes has f ll access to the system

reso rces
ñ Five of them are called exception modes
-F
-
-SVC
-ABT
-UND
|
DES
ñ rocessor enters into rivileged modes nder
specific exception condition
ñ All the exception Modes ses some additional
registers ,to avoid corr pting the ser state
when exception occ rs
ñ SYS ses the same no: of registers as the User
Mode
| |
Ba

ARM 7 ses load and store Architect re.
ñ ÿata has to be moved from memory location to a
central set of registers.
ñ ÿata processing is done and is stored back into
memory.
ñ Register bank contains, general p rpose registers to
hold either data or address.
ñ It is a bank of 16 ser registers R0-
R0-R15 and 2 stat s
registers.
ñ Each of these registers is 32 bit wide.
|
EG STE S
ñ ARM has 32 bit long registers
30 general p rpose registers

5 dedicated aved rogram tat s egisters
1 dedicated rrent rogram tat s egister
1 dedicated program co nter
|
G
al
ñ uan be divided into three gro ps
Un-banked r0-
Un- r0-r7
Banked r8-
r8-r14
u r15
|
U
--ba

U
ñ Registers to
ñ Each of these registers address the same physical

registers for all the modes
ñ uompletely general p rpose registers , with no

ses implied by the architect re
|
Ba

ñ Registers to
ñ physical registers referred to by each of them

depends on the mode of operation
ñ Banked register contents are preserved across

operating mode changes
|
Ba

ñ r8 to r12
* two banked physical registers each
*one for FIQ and other for all other modes
*referred to as r8_ sr to r12_ sr & r8_fiq to r12_fiq
ñ r13 & r14
*has six banked registers each
*one in USER & SYS and rest five in each exception modes
*referred to as r13_<mode>/r14_<mode>3for exception modes)
|
G
al
ñ 32 bit registers
32
ñ 15 general p rpose registers are visible at one
time , depending on the c rrent processor mode
,as
ñ conventionally sed as stack pointer

ñ
conventionally sed as link register to store
the ret rn address for exception/ s b-b-ro tine
call
|
aC

ñ u is accessed as r15
ñ Incremented by 4 bytes for ARM state and 2
bytes for THUMB state
ñ Branch instr ction loads destination address into
the u
ñ uan also be loaded sing data operation
instr ction
|
A EG STE S
r0 r0 r0 r0 r0 r0
r1 r1 r1 r1 r1 r1
r2 r2 r2 r2 r2 r2
r3 r3 r3 r3 r3 r3
r4 r4 r4 r4 r4 r4
r5 r5 r5 r5 r5 r5
r6 r6 r6 r6 r6 r6
r7 r7 r7 r7 r7 r7
r8 r8_fiq r8 r8 r8 r8
r9 r9_fiq r9 r9 r9 r9
r10 r10_fiq r10 r10 r10 r10
r11 r11_fiq r11 r11 r11 r11
r12 r12_fiq r12 r12 r12 r12
r13 r13_fiq r13_svc r13_abt r13_irq r13_ nd
r14 r14_fiq r14_svc r14_abt r14_irq r14_ nd
r153u) r153u) r153u) r153u) r153u) r153u)
uSR uSR uSR uSR uSR uSR

SSR_fiq SSR_svc SSR_abt SSR_irq SSR_ nd
|
CS
CS --

a
aa
a

ñ uSR holds
uopies of ALU stat s flags
The c rrent processor mode
Interr pt disable flag
ñ ALU stat s flags are sed to determine whether
conditional instr ctions are exec ted or not
ñ On THUMB capable processors ,the uSR
holds the c rrent processor state
| |
FLAGS
ñ C

la
N(31) ² *set to bit 31 of the res lt of the instr ction

*N=0 if positive
*N=1 if negative
ë(30)²² *Z=1 if res lt is zero

ë(30)
*Z=0 if not zero
C(29) ² *for addition ,set to 1 if carry occ rs & 0 otherwise

*for s btraction ,set to 0 if borrow occ rs & 1
otherwise
*for shift operations , u contains the last bit shifted
(28)² *for addition and s btraction V set to 1 if signed overflow

V (28)²
occ rs
|
FLAGS
C
lb
(7) *when set disables IRQ interr pt
F(6) *when set disables FIQ interr pt
T(5) *on T variants

T=0 ,indicates ARM exec tion
T=1 ,indicates THUMB exec tion
|
FLAGS
ñ MOÿE BITS 34:0)
(4:0)
10000 User
10001 FIQ
10010 IRQ
10011 S pervisor
10111 Abort
11011 UNÿ
11111 SYS
|
SS
SS --a
a
a
aa
a

ñ Used to store uSR when an exception is taken
ñ One SSR is accessible in each of the exception

handling mode
ñ User Mode and System Mode doesn·t have

SSR as they don·t handle exceptions
|

ARM Has 7 Operating Modes ARM Has 7 Operating Modes: - Fa F Fa F

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ARM Has 7 Operating Modes ARM Has 7 Operating Modes: - Fa F Fa F

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ñ ARM has 7 operating modes

ñ A program in ser mode is nable to access some

ñ Mode change can be by

ñ rivileged modes has f ll access to the system

30 general p rpose registers

ñ Each of these registers address the same physical

ñ uompletely general p rpose registers , with no

ñ physical registers referred to by each of them

ñ Banked register contents are preserved across

uSR uSR uSR uSR uSR uSR

N(31) ² *set to bit 31 of the res lt of the instr ction

ë(30)²² *Z=1 if res lt is zero

C(29) ² *for addition ,set to 1 if carry occ rs & 0 otherwise

(28)² *for addition and s btraction V set to 1 if signed overflow

F(6) *when set disables FIQ interr pt

T(5) *on T variants

ñ One SSR is accessible in each of the exception

ñ User Mode and System Mode doesn·t have

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ARM Has 7 Operating Modes ARM Has 7 Operating Modes: - Fa F Fa F

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ARM Has 7 Operating Modes ARM Has 7 Operating Modes: - Fa F Fa F

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ARM Has 7 Operating Modes ARM Has 7 Operating Modes: - Fa F Fa F

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 

ñ ARM has 7 operating modes

ñ A program in ser mode is nable to access some

ñ Mode change can be by

ñ rivileged modes has f ll access to the system

 30 general p rpose registers

ñ Each of these registers address the same physical

ñ uompletely general p rpose registers , with no

ñ physical registers referred to by each of them

ñ Banked register contents are preserved across

uSR uSR uSR uSR uSR uSR

N(31) ² *set to bit 31 of the res lt of the instr ction

ë(30)²² *Z=1 if res lt is zero

C(29) ² *for addition ,set to 1 if carry occ rs & 0 otherwise

(28)² *for addition and s btraction V set to 1 if signed overflow

F(6) *when set disables FIQ interr pt

T(5) *on T variants

ñ One SSR is accessible in each of the exception

ñ User Mode and System Mode doesn·t have

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ñ rivileged modes has f ll access to the system

30 general p rpose registers

uSR uSR uSR uSR uSR uSR

ë(30)²² *Z=1 if res lt is zero

(28)² *for addition and s btraction V set to 1 if signed overflow

ñ One SSR is accessible in each of the exception