BRANCH, CALL,

AND TIME DELAY

LOOP
• Status Register (SREG)
• C: Carry Flag R0
R1
• Z: Zero Flag ALU
R2
• N: Negative Flag

…
• V: Two’s complement overflow SREG: I T H S V N Z C
R15
indicator
• S: For signed tests
CPU R16
R17

PC

…
• H: Half Carry Flag
• T: Transfer bit used by BLD Instruction decoder R30
R31
(Bit load) and BST (Bit store) instructions Instruction Register
registers
• I: Global Interrupt Enable/Disable Flag
• In the sequence of instructions to be executed, it is
often necessary to transfer program control to a
different location. There are many instructions in AVR
to achieve this. This chapter covers the control
transfer instructions available in AVR Assembly
language.
• we discuss instructions used for looping, as well as
instructions for conditional and unconditional
branches (jumps)
BRANCH INSTRUCTIONS AND
LOOPING
• Repeating a sequence of instructions or an operation a certain
number of times is called a loop.
• The loop is one of most widely used programming techniques.
• In the AVR, there are several ways to repeat an operation many times.
• A sample Program without Loop.
LDI R16,0 ;R16 = 0
LDI R17,3 ;R17 = 3
ADD R16,R17 ;add value 3 to R16 (R16 0x03)
ADD R16,R17 ;add value 3 to R16 (R16 0x06)
ADD R16,Rl7 ;add value 3 to R16 (R16 0x09)
ADD R16,R17 ;add value 3 to R16 (R16 0x0C)
ADD R16,R17 ;add value 3 to R16 (R16 0x0F)
ADD R16,R17 ;add value 3 to R16 (R16 0x12)
Using BRNE instruction for looping
• The BRNE (branch if not equal) instruction uses the zero flag in the status register.
• It means, if it is not zero, it branches (Jumps) back to the target address referred
to by the label.
• The BRNE instruction is used as follows:
BACK: ................. ; start of the loop
......... ; body of the loop
......... ; body of the loop
DEC Rn ;decrement Rn, Z = 1 if Rn= 0
BRNE BACK ;branch to BACK if Z = 0

• In the last two instructions, the Rn (e.g., R16 or R17) is decremented; if it is not
zero, it branches (jumps) back to the target address referred to by the label.
Write a program to (a) clear R20, then (b) add 3 to R20 ten times, and
( c) send the sum to PORTB. Use the zero flag and BRNE.
Load Counter . INCLUDE “M32DEF. INC”

CLEAR R20
LDI R16, 10 ;R16 = 10 (decimal) for counter
Load R21 with 3 LDI R20, 0x00 ;R20 = 0x00

Add Value LDI R21, 0x03 ;R21 = 0x03

AGAIN: ADD R20, R21 ;add 03 to R20 (R20 = sum)
Decrement Counter
DEC R16 ;decrement Rl6 (counter)
BRNE AGAIN ;repeat until COUNT = 0
Is counter
Zero? OUT PORTB, R20 ;send sum to PORTB
NO

YES What is the maximum number of times that the loop in

Place the result on PORTB Example can be repeated?
Write a program to (a) load the PORTH register
with the value Ox55, and (b) complement Port B
700 times.
• Because 700 is larger than 255 (the maximum capacity of any general purpose
register), we use two registers to hold the count. The following code shows
how to use R20 and R21 as a register for counters.
.INCLUDE “M32DEF.INC”
.ORG 0
LDI R16, 0x55 ;R16 = 0x55
OUT PORTE, R16 ;PORTE = 0x55
LDI R20, 10 ;load 10 into R20 (outer loop count)
LOP_1:LDI R21, 70 ;load 70 into R21 (inner loop count)
LOP_2:COM R16 ;complement R16
OUT PORTE, R16 ;load PORTB SFR with the complemented value
DEC R21 ;dec R21 (inner loop)
BRNE LOP_2 ;repeat it 70 times
DEC R20 ;dec R20 (outer loop)
BRNE LOP_1 ;repeat it 10 times
Other conditional jumps
• BRLO->Branch if Lower (Unsigned) ( Branch if C = 1)
• BRSH->Branch if Same or Higher (Unsigned) (Branch if C = 0)
• BREQ ->Branch if Equal (Branch if Z = 1)
• BRNE->Branch if Not Equal (Branch if Z = 0)
• BRMI->Branch if Minus (Branch if N = 1)
• BRPL->Branch if Plus (Branch if N = 0)
• BRVS->Branch if Overflow Set(Branch if V = 1)
• BRVC->Branch if Overflow Cleared (Branch if V = 0)
•All conditional branches are short jumps
•It must be noted that all conditional jumps are short jumps, meaning that the
address of the target must be within 64 bytes of the program counter (PC).
•All conditional branches such as BRSH, BREQ, and BRNE are short branches due to
the fact that they are all 2-byte instructions.
•In these instructions the opcode is 9 bits and the relative address is 7 bits.
•The target address is relative to the value of the program counter. If the relative
address is positive, the jump is forward. If the relative address is negative, then the
jump is backwards.
•The relative address can be a value from -64 to +63.
•To calculate the target address, the relative address is added to the PC of the next
instruction (target address= relative address + PC).
Unconditional branch instruction
• The unconditional branch is a jump in which control is
transferred unconditionally to the target location.
• In the AYR there are three unconditional branches: JMP
Gump), RJMP (relative jump), and IJMP (indirect jump).
• Deciding which one to use depends on the target address.
JMP (JMP is a long jump)
• JMP is an unconditional jump that can go to any memory location in the
4M (word) address space of the AVR.
• It is a 4-byte (32-bit) instruction in which 10 bits are used for the opcode,
and the other 22 bits represent the 22-bit address of the target location.
• The 22-bit target address allows a jump to 4M (words) of memory
locations from 000000 to $3FFFFF. So, it can cover the entire address
space.
• Although the AVR can have ROM space of 8M bytes, not all AYR family
members have that much on-chip program ROM.
• Some AYR family members have only 4K-32K of on-chip ROM for program
space; consequently, every byte is precious.
RJMP (relative jump)

• For this reason there is also an RJMP (relative jump) instruction,

which is a 2-byte instruction as opposed to the 4-byte JMP
instruction.
• In this 2-byte (16-bit) instruction, the first 4 bits are the opcode and
the rest (lower 12 bits) is the relative address of the target location.
• The relative address range of 000 - $FFF is divided into forward and
backward jumps; that is, within -2048 to +2047 words of memory
relative to the address of the current PC (program counter).
• If the jump is forward, then the relative address is positive. If the
jump is backward, then the relative address is negative.
IJMP (indirect jump)
• IJMP is a 2-byte instruction.
• When the instruction executes, the PC is loaded with the
contents of the Z register, so it jumps to the address pointed
to by the Z register.
• so IJMP can jump within the lowest 64K words of the
program memory.
• In the other jump instructions, the target address is static,
which means that in a specific condition they jump to a fixed
point. But IJMP has a dynamic target point, and we can
dynamically change the target address by changing the Z
register's contents through the program.
CALL INSTRUCTIONS AND STACK
• Another control transfer instruction is the CALL instruction,
which is used to call a subroutine
• Subroutines are often used to perform tasks that need to be
performed frequently.
• This makes a program more structured in addition to saving
memory space.
• In the AYR there are four instructions for the call subroutine:
CALL (long call) RCALL (relative call), ICALL (indirect call to Z),
and EICALL (extended indirect call to Z).
CALL
• In this 4-byte (32-bit) instruction, I 0 bits are used for the opcode and the other
22 bits, are used for the address of the target subroutine, just as in the JMP
instruction.
• Therefore, CALL can be used to call subroutines located anywhere within the 4M
address space of000000-$3FFFFF for the AVR.
• To make sure that the AYR knows where to come back to after execution of the
called subroutine, the microcontroller automatically saves on the stack the
address of the instruction immediately below the CALL.
• When a subroutine is called, control is transferred to that subroutine, and the
processor saves the PC (program counter) of the next instruction on the stack and
begins to fetch instructions from the new location.
• After finishing execution of the subroutine, the RET instruction transfers control
back to the caller. Every subroutine needs RET as the last instruction.
Call instruction
Call example: Toggle all the bits of Port B
with a time delay
MYREG EQU 0x08 ORG 300H
ORG 0 DELAY MOVLW 0xFF
BACK MOVLW 0x55 MOVLW MYREG
MOVWF PORTB AGAIN NOP
CALL DELAY NOP
MOVLW 0xAA DECF MYREG, F
MOVWF PORTB BNZ AGAIN
CALL DELAY RETURN
GOTO BACK END
Stack and stack pointer
• Store critical information temporarily
RCALL (relative call): 2-byte instruction
MYREG EQU 0x08 ORG 300H
ORG 0 DELAY MOVLW 0xFF
BACK MOVLW 0x55 MOVLW MYREG
MOVWF PORTB AGAIN NOP
RCALL DELAY NOP
MOVLW 0xAA DECF MYREG, F
MOVWF PORTB BNZ AGAIN
CALL DELAY RETURN
GOTO BACK END
Pipelining
Instruction cycle
 one instruction cycle consists of 4 oscillatory cycles
 Example: Find the period of instruction cycle if crystal
frequency is 4 MHz and 20 MHz
 4/4 = 1 MHz instruction cycle = 1/1 MHz = 1 μs
 20/4 = 5 MHz instruction cycle = 1/5 MHz = 0.2 μs
Branch penalty and delay calculation
 Pipeline is flushed 4-MHz crystal frequency
if branch Instruction
 Instruction cycle = 2 cycle
 GOTO
DELAY MOVLW 0xFA 1
 CALL
BRA
MOVLW MYREG 1
 Instruction cycle = 2 or 1 in
conditional branch AGAIN NOP 1
 2 if jump NOP 1
 1 if fall through NOP 1
DECF MYREG, F 1
BNZ AGAIN 2
RETURN 1

Time delay=
(250x6+3)x1μs=1503 μs
Large delay using a nested loop
R2 EQU 0x7  Time delay =
EQU 0x8 { [ (5 x 250) + 5 ] x 200 + 3
R3 - 200 – 1 } x 1 μs
D MOVLW D’200’ 1
EL MOVWF R2 1 Fall through in BNZ
AY
AGAIN MOVLW D’250’ 1
MOVWF R3 1
HERE NOP 1
NOP 1
DECF R3, F 1
BNZ HERE 2
DECF R2, F 1
BNZ AGAIN 2
RETURN 1
Toggle PORTB every 1 s.
(The crystal frequency is 10 MHz)
R2 EQU 0x2 DELAY
MOVLW D’20’ 1
R3 EQU 0x3
R4 EQU 0x4 MOVWF R4 1
BACK MOVLW D’100’ 1
MOVLW 0x55 MOVWF R3 1
MOVWF PORTB AGAIN MOVLW D’250’ 1
BACK CALL DELAY MOVWF R2 1
COMF PORTB HERE NOP 1
GOTO BACK NOP 1
DECF R2, F 1
BNZ HERE 2
DECF
Time delay = 20 x 100 x 250 x 5 x 400 ns R3, F 1
=1s AGAIN 2

BNZ
DECF R4, F 1
BNZ BACK 2