Abstractlevelppt

DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING
Performance analysis of full-adder

based on domino logic technique
PRESENTED BY: UNDER THE GUIDENCE OF:

Batch Number: B8 MR S SRIKANTH
• GANESH - 21C35A0437 (ASSISTANT PROFESSOR)
• ASHRITHA - 21C35A0410 DEPARTMENT OF ELECTRONICS AND COMMUNICATION
• ROHITH - 21C35A0419 ENGINEERING
• MUSHEER - 20C31A0483
• GANESH - 20C31A0473
CONTENTS
 Abstract  Advantages
 Introduction  Applications
 Literature review  Tools used
 Existing system  References
 Disadvantages
 Proposed system
ABSTRACT
 In modern VLSI area efficient devices are most used because most of the
devices are becoming portable.
 The Domino logic technique is often employed in designing the area
efficient and high-speed devices.
 In this project one- bit full adder circuit using CMOS based logic and
domino- based logic will be designed on Tanner EDA tool, based on 250Nm
technology having the supply voltage of 5v.
 This project is mainly centralized on the design of area efficient and fast
speed devices.
 This work will implements the performance of CMOS and Domino logic
based on full adder circuit in terms of delay and power consumption.
INTRODUCTION
 In the fast-growing VLSI industry, transistor density is increasing with rapid rate
day-by-day. According to Moore’s law transistor density will get doubled itself
after every eighteen months .
 As the number of transistors will increase, correspondingly area, delay and
power consumption of the device will also increase. So, a technology is required
by which the area can be reduced and increase the performance of the device.
 From the past few decades CMOS technology is being used for designing the
chips in semiconductor industry, but as the number of transistors are increasing,
area of the device and delay both are increasing. So, it requires to switch to a
technology, which uses lesser area and smaller delay.
 Hence, the Domino logic is used for designing the one-bit full adder and
compared the various performance parameter like area, delay, and power
consumption in both technologies.
LITERATURE SURVEY
PROBLEM IDENTIFIED
• More number of transistors due to CMOS technology

• Large delay
• More Power Consumption
OBJECTIVE
 Implementing a one bit full using CMOS technology

Is replaced by DOMINO logic
EXISTING SYSTEM
Logic diagram of one-bit full adder

One-bit full adder using CMOS Logic - 28 Transistors
PROPOSED METHOD
 Domino logic operates in two steps, the first being pre-charging and
the second being evaluation. When the clock 'clk' is equal to zero or
low, the PMOS switches on and charges the output node to Vdd .
The p-MOS is turned off when the clock reaches a high value, and
the evaluation phase commences .
 The configuration of the input determines the output during this
phase. The output node may discharge if the inputs have a direct
conducting link to ground; otherwise, it will remain high.
 As a result, the output of the circuit, mainly depends on the
evaluation stage. In pre-charge phase, it will provide low output
because we used an inverter in this logic style for cascading the next
stage
One-bit full adder using Domino Logic - 20 Transistors
Domino logic.
ADVANTAGES
 Less number of transistors are required as only n-mos logic is used

 Less delay is achieved due to domino logic
 Less power consumption
APPLICATIONS
 A Full Adder’s circuit can be used as a part of many other larger

circuits like Ripple Carry Adder which adds n-bits simultaneously.
 The dedicated multiplication circuit uses Full Adder’s circuit to
perform Carryout Multiplications.
 Full Adders are used in ALU - arithematic logic unit.
 In order to memory address inside a computer and to make the
program counter point to next instruction, the ALU makes the use of
Full Adder.
 Full Adders are a part of Graphics Processing unit for graphic related
applications.
TOOLS USED
 TANNER EDA
 Technology used:250nm
REFERENCES
• Thorp, K. Himabindu and K. Hariharan, "Design of area and power efficient
full adder in 180nm," 2017 International Conference on Networks &
Advances in Computational Technologies ( NetACT ), Thiruvanthapuram, ,
pp. 336-340, 2017.
• Zhiyu Liu, Volkan Kursun, "Leakage Power Characteristics of Dynamic
Circuits in Nanometer CMOS Technologies", IEEE Trans. Circuits and
Systems-II, vol. 53, no. 8, 2006.
• "High-Performance Low-Power Domino Full-Adder Circuits" by P.
Subbarami Reddy and K. V. Srinivas, a new design for a domino full adder
is presented.
• In "An Ultra-Low Power, Area Efficient Domino Full Adder" by M. T. Nasef
and M. I. Elmasry, a new domino full adder circuit is proposed.
THANK YOU

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DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING

Performance analysis of full-adder

PRESENTED BY: UNDER THE GUIDENCE OF:

• More number of transistors due to CMOS technology

 Implementing a one bit full using CMOS technology

Logic diagram of one-bit full adder

 Less number of transistors are required as only n-mos logic is used

 A Full Adder’s circuit can be used as a part of many other larger

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