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    DD Seminar

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    Prarthana TL

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    © All Rights Reserved
    Download as PPTX, PDF, TXT or read online from Scribd

    DD Seminar

    Uploaded by

    Prarthana TL
    4 views8 pages

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    Copyright:

    © All Rights Reserved
    Download as PPTX, PDF, TXT or read online from Scribd
    Download as pptx, pdf, or txt
    4 views8 pages

    DD Seminar

    Uploaded by

    Prarthana TL

    Copyright:

    © All Rights Reserved
    Download as PPTX, PDF, TXT or read online from Scribd
    Download as pptx, pdf, or txt
    You are on page 1of 8

    BASIC

    PROCESSI
    NG UNIT
    Single Bus
    Organization
    Processors contain only a single bus for the movement of data,
    address and instructions.
    Insert or Drag and Drop your Image
    MDR -> Memory Data Register,
    MAR -> Memory Address Register
    ALU -> Arithmetic and Logic Unit
    MUX -> Multiplexer
    PC -> Program Counter

    Jens Martensson 2
    Register
    Transfers
    • Instruction execution involves a sequence of steps in which
    data are transferred from one register to another.
    • For each register, two control-signals are used: Riin & Riout.
    These are called Gating Signals
    • Riin=1,the data on the bus are loaded into Ri, Insert or Drag and Drop your Image
    • Riout=1,the contents of register are placed on the bus,
    • Riout=0,the bus can be used for transferring data from other
    registers.

    Jens Martensson 3
    PERFORMING AN ARITHMETIC OR LOGIC OPERATION
    • The ALU is a combinational circuit that has no internal storage.
    • The ALU performs arithmetic and logic operations on the 2 operands
    applied to its A and B inputs.
    • ALU gets the two operands, one is from MUX and another from bus. The result is temporarily
    stored in register Z.
    • Therefore, a sequence of operations [R3]=[R1]+[R2].
    1) R1out, Yin
    2) R2out, Select Y, Add, Zin
    3) Zout, R3in
    Instruction execution proceeds as follows:
    • Step 1 --> Contents from register R1 are loaded into register Y.
    • Step2 --> Contents from Y and from register R2 are applied to the A and B inputs of ALU;
    Addition is performed & Result is stored in the Z register.
    • Step 3 --> The contents of Z register is stored in the R3 register. The signals are activated for the
    duration of the clock cycle corresponding to that step. All other signals are inactive.

    Jens Martensson 4
    CONTROL-SIGNALS OF
    MDR
    The MDR register has 4 control-signals (Figure 7.4):
    1) MDRin & MDRout control the connection to the internal processor
    data bus
    2) MDRinE & MDRoutE control the connection to the external memory
    Data
    • bus.
    • • Similarly, MAR register has 2 control-signals.
    • 1) MARin: controls the connection to the internal processor address
    bus &
    • 2) MARout: controls the connection to the memory address bus.

    Jens Martensson 5
    EXECUTION OF A
    COMPLETE
    INSTRUCTION
    Consider the instruction Add (R3),R1 which adds the contents of a
    memory-location pointed by R3 to register R1.
    Executing this instruction requires the following actions:
    1) Fetch the instruction.
    2) Fetch the first operand.
    3) Perform the addition
    4) Load the result into R1.

    Jens Martensson 6
    PERFORMING AN ARITHMETIC OR LOGIC OPERATION
    • Step1--> The instruction-fetch operation is initiated by loading contents of PC into MAR &
    sending a Read request to memory. The Select signal is set to Select4, which causes the Mux to
    select constant 4. This value is added to operand at input B (PC‟s content), and the result is
    stored in Z.
    • Step2--> Updated value in Z is moved to PC. This completes the PC increment operation and PC
    will now point to next instruction.
    • Step3--> Fetched instruction is moved into MDR and then to IR. The step 1 through 3 constitutes
    the Fetch Phase. At the beginning of step 4, the instruction decoder interprets the contents of
    the IR. This enables the control circuitry to activate the control-signals for steps 4 through 7.
    The step 4 through 7 constitutes the Execution Phase.
    • Step4--> Contents of R3 are loaded into MAR & a memory read signal is issued.
    • Step5--> Contents of R1 are transferred to Y to prepare for addition.
    • Step6--> When Read operation is completed, memory-operand is available in MDR,
    • Step7--> Sum is stored in Z, then transferred to R1.The End signal causes a new instruction fetch
    cycle to begin by returning to step1.

    Jens Martensson 7
    Thank
    You

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