Execution of a complete instruction

Hardwired control design

Micro programmed control design Unit -2

Nano programming

CISC and RISC principles

 Execution of a complete
Instruction Cycle:
instruction
• Fetch Instruction
• Decode Instruction(Identify opcode and operand)
• Execute Instruction
• Write Back Result(In Register/Memory)
Registers Involved In Each Instruction Cycle:
• Memory address registers(MAR) : It is connected to the address lines of the system
bus. It specifies the address in memory for a read or write operation.
• Memory Data Register(MDR) : It is connected to the data lines of the system bus. It
contains the value to be stored in memory or the last value read from the memory.
• Program Counter(PC) : Holds the address of the next instruction to be fetched.
• Instruction Register(IR) : Holds the last instruction fetched.
Example:
ADD(R3),R1
• Fetch the instruction and place into some register
• Fetch the first operand(the contents of the memory location pointed
by R3)
• Fetch the Second operand
• Perform the addition
• Store the result into R1
Example:
ADD(R3),R1
• Fetching the instruction means extract the instruction from the
memory location to instruction register, that we want to execute next.
• Decode unit decode the instruction which is available in the
instruction register then identify what operation has to be perform
next and what are the operands required
• Execute the instruction
• Finally write the results into Register/Memory Location
Perform: ADD (R3), R1
 Execution of a complete
instruction

ADD (R3), R1
Steps 1, 2 and 3. Fetch &
Increase PC
• PCout, MARin, Read, Select 4, Add, Zin
• Load the content of the PC into MAR, and send a read
request
• PCout, MARin, Read
• While waiting for a response, increment PC
• Select constant 4 in MUX
• ALU input B is receiving the current value in PC,
• Specify Add operation
• In step 2, move updated value back into PC and wait MFC
(Zout, PCin, WMFC)
• In step 3, the word fetched from memory is loaded into
IR
• MDRout, IRin

10
Steps 4, 5, 6
and 7
Step 4 and 5:
• Fetch the first operand: the content of the memory location pointed to by R3
• R3out, MARin, Read
• R1out, Yin, WMFC

Step 6:
• Perform the addition
• MDRout, Select Y, Add, Zin

Step 7:
• Load results into R1
• Zout, R1in, End

11
• Store R2,[R1]
MAR<-[R1]
MDR<-R1,
WRITE
WMFC
R2<-MDR
 r
Control sequence for ADD (NUM),R1
Hardwired Control Unit
Hardwired Control
Unit
• We can design a circuit which can generate the signal
• The control unit (CU) is a component of a CPU that directs the
operation of the processor
• It tells the computer’s memory, ALU unit and I/P-O/P device-How to
respond to a program’s instructions?
• It direct the operations of the other units by providing timing and
control signals
• All computer resources are manages by the CU.
• It directs the flow of data b/w CPU and other devices.
• Control Unit generates the control signals to perform the
operations
• It also instruct ALU, which operation should be perform on data
 Hardwired Control
Unit
• Control unit can be designed by two methods
 Hardwired Control Unit
 Microprogrammed Control Unit
 Hardwired Control
Unit
• It is implemented with the help of physical components which is
hardwired (gates, flip flop, decoders) in H/W.
• The input to the control unit are the Instruction Register, Flags, Timing
Signals, Step Counter
• If designed is modified or changed, all the combinational circuits should
be modified which is a very difficult task.
• Hardwired CU is faster because control signals are generated using logic
circuit
• The sequence of operation carried out by this machine is determined by
wiring the logic elements so it is known as “Hardwired”
• The purpose of CU is to generate the signals, which will direct the
operations
 Hardwired Control
Unit
• Block Diagram of Hardwired CU (Sequence Counter Method)
1. Instruction Register(I/P): It is used to store the instruction fetched
from the memory
2. Decoder: Used to decode(Interpret) the operation code of the
instructions
3. Clock: Used to generate a sequence of timing signals using timing
generator
4. Flags: Condition codes/status flags are used to specify the status of
previous ALU Operations
Hardwired Control
Unit
 Hardwired Control
Unit register
Instruction
• The instruction register is
processors register that has a
‘instruction’ which is currentlythein
execution. The instruction register
generates the OP-code
bits respective of
the operation and the addressing
modes of the operands,
mentioned in the instruction.
• One of the i/p for the control unit
is IR(Instruction Register).
• In the Instruction Register we can
identify the opcode bits.
• Opcode bits tells about which
operation like ADD, LOAD,
MOV will be performed.
 Hardwired Control
Unit
Instruction Decoder
• Instruction decoder receives
Op-code bits generated by the
instruction the
register and interprets the
operation and addressing
modes of the instruction.
• Now, based on operation and
addressing mode of the
instruction in
instruction register it set the
corresponding
Instruction signal
INSi to 1.
 Hardwired Control
Unit
Step Counter
• Now, the control unit must be aware of the current
step, the instruction is in. For this, a Step Counter is
implemented which has signals from T1, …, T5. The
step counter sets one of the signals T1 to T5 to 1 on
the basis of the step, the instruction is in.
• Here, the question arises how step counter
knows
the current step of the instruction?
• It means you have to design a machine such that it
can generates
• For this, a stage
Clocksignal within 1CC.
is implemented. This clock
designed
is such that for each step the clock must
complete its one clock cycle.
So, consider if the step counter has set T3 signal
1(enabled) then after a clock cycle completes
step counter will set T4 to 1(enabled).
• There is a periodicity in instruction execution(Fetch,
Decode, Execute, Memory Access, Store). So it can be
synchronized with the Clock.
 Hardwired Control
Unit
Step Counter
• Depends on the ‘Step Counter bit patterns’
control signal generator can understand what
is the situation, i.e. instruction
execution is in which state like fetch,
decode, execute etc.
NOTE:
• It means from the output of instruction decoder
we can understand the what type of instruction
we have to perform and from the o/p of step
counter step counter it can be understand
execution is in which state like fetch, decode,
execute etc.
 Hardwired Control
Unit
Counter Enable
• What if the execution of instruction has is interrupted due
to some reason?
• Will the clock still continue to trigger step counter?
• The answer is No. The Counter Enable ‘disables’ the step
counter to increment to the next step signal, till
the execution of the current step is completed.
• E.g. Sometimes memory access phase may take 2CC. At
this time Counter Enable ‘disables’ the clock till
the Memory Function Complete. It means CC will
not be increase and all the signals will be stopped for
some time.
• Once Memory interface generates MFC Signal, it means
memory work is over then immediately counter enable
set to 1.
 Hardwired Control
Unit
Condition Signal
• Now, suppose the execution of an
instruction depends on some condition
or if it is branch instruction.
• This is determined with the help of
the Condition signals.
• The Condition signals generate the signals
for the conditions greater than, less
than, equal, greater than equal, less than
equal etc.
• During ALU Operations, some conditional
signal is generated.
 Hardwired Control
Unit
External Input
• The remaining is External inputs, it
acknowledges the control signal
generator of interrupts which affects
the execution of the instruction.
• Let us keyboard generates the interrupt
signals, it should also be
considered because based on this
execution flow is going to be affected.
 Hardwired Control
•Unit
Wrt to given table, write circuit expression for generating signal for
bring the data from memory and keep into MDR . Let only during
the execution of operations LDA,ADD,AND instructions; read from
memory is required. Let Execution Cycle is done when PQ=11.
CYCLE MICRO-OPERATIONS CONTROL SIGNALS

Fetch t1: MARPC C2

PQ=00 t2: MDRMemory C5
Indirect t1: MARIR(Address) C8
PQ = 01 t2: MDRMemory C5
Interrupt Cycle t1: MARPC C4
PQ = 10 t3: MDRMemory C5
 Hardwired Control
•Unit
Wrt to given table, write circuit expression for generating signal for
fetch the data from memory and keep into MDR .
CYCLE MICRO-OPERATIONS CONTROL SIGNALS

Fetch t1: MARPC C2

PQ=00 t2: MDRMemory C5
Indirect t1: MARIR(Address) C8
PQ = 01 t2: MDRMemory C5
Interrupt Cycle t1: MARPC C4
PQ = 10 t3: MDRMemory C5

C5 = P’Q’t2+ P’Qt2+ PQ’t3

Let only LDA,ADD,AND instruction read from memory. It means during opcode (LDA,
ADD, AND) we need
C5 = P’Q’t2+ P’Qt2+ PQ’t3 + PQ(LDA+ADD+AND)t2
Hardwired Control
Unit
• C5 = P’Q’t2+ P’Qt2+ PQ’t3 + PQ(LDA+ADD+AND)t2
• Using this above expression logic circuit will be designed.
• This circuit will be used in control unit
• Like this many other circuits will be used based on what control
signals are required.
• The work of these control signals is to do the micro-operations
• Micro-operations means moving one value to one register to another
register or memory to register etc.
 State Table Method
• Here the behavior of control unit is represented in the form of a table,
which is known as the state table.

• Here, each row represents the Micro operations (t0,t1,..) and the
columns represent the instructions.

• Every intersection of the specific column to each row indicates which

control signal will be produced in the corresponding T- state of an
instruction.

• Here the hardware circuitry is designed for each column(i.e. for every
instruction) for producing control signals in different T-states.
Q. Consider a hypothetical CPU which supports only two
instructions.
Each instruction requires 5-micro operations. The
system employs 4 control signals S0, S1, S2 and S3.
Design the
Time circuit for
I1 S2. I2
T1 S0,S1 S0,S3
T2 S1,S2 S2,S2
T3 S1,S0 S1,S3
T4 S3,S3 S1,S2
T5 S1,S2 S1,S3
Q. Consider a hypothetical CPU which supports only two
instructions.
Each instruction requires 5-micro operations. The
system employs 4 control signals S0, S1, S2 and S3.
Design the
Time circuit for
I1 S2. I2
T1 S0,S1 S0,S3
T2 S1,S2 S2,S2
T3 S1,S0 S1,S3
T4 S3,S3 S1,S2
T5 S1,S2 S1,S3

S1 = I1T1 + I1T2 + I1T3 + I1T5 + I2T3 + I2T4 +I2T5

S1 = T3 + T5 + I1T1 + I1T2 + I2T4

Similarly,
S2 = I1T2 + I2T2 + I2T4 + I1T5 = T2 + I2T4 + I1T5

S3 = I1T4 + I2T1 + I2T3 + I2T5

Q. Consider a hypothetical CPU which supports only two
instructions. Each requires 5-micro operations. The system
employs 4 control
signals S0, S1, S2 and S3. Design the circuit for S2.
• Circuit for S2 [ S2 = T2 + I2T4 + I1T5]
Q. Consider a hypothetical CPU which supports only two
instructions. Each instruction requires 4-micro operations.
The system employs 4 control signals S1, S2,S3 and S4.
Design the circuit for S1,S2 and S4.
Time I1 I2
T1 S1,S4 S1,S3
T2 S2,S3 S1,S4
T3 S1,S2 S3,S2
T4 S3,S4 S1,S4
Microprogrammed Control Unit
Micro-program
Control Unit
• A microprogram CU in which control signals are stored in the binary
form(0 & 1) as control word in a ROM Chip called Control
Memory.
• The purpose of designing of microprogram CU is to generate control
signals for every operation.
• So, whatever possible control signals has to be generated, it is
programmed at the chip level in advance and save into memory,
which is called ROM Memory.
 Microprogram Control
Unit
Micro-operation Example:
• Transfer the data from Register R1 to R2 i.e.,
MOV R2, R1
(RTL- register transfer language)
Condition: operation
T1 : R2 R1
Control Signals Required: R1 OUT ;
R2 IN
• Swapping the content of Register R1 and R2
T : R1 R2; R2 R1
Control Signals Required: R2 OUT; R1IN ;
• A set of microInstructions represent the microprogram.
• Fetch microprogram (common for every instruction) Clock
• Execute microprogram (vary for instruction to instruction) T1 :MAR (PC)
T2 :MDR M[MAR]
• Interrupt microprogram T3 :IR (MDR)
• Instructions are available in memory. PC (PC) + 1 (Incremented using Up
Counter)

Fetch Microprogram: place the instruction into Instruction

Control Signals
• Register (IR) PC(out) ;MAR(in)
• Visit the memory MAR(out) ;MDR(in)
MDR(out) ; IR(in)
• Get the instruction
PC(out) ; PC(in)
• Place/store it in IR
Write the executional phase microprogram
for INC X

• This instruction has to increment the contents of memory

• location X.
• Visit location X
• Get the content of X INC X executional microprogram
T1 : MAR IR(Ref )
• Increment it. T2 : MDR M[MAR]
• Save the result at X T3 : MDR [MDR]
+ 1 T4 : M[MAR]
[MDR]
Control Signals:
MAR(IN) ;
IR(OUT) ;MDR(IN)
;MDR(OUT) ; IR(IN)
 Write the executional phase microprogram for ADD X.

• This instruction has to add the content of memory location X to Accumulator (A).
• Visit the memory location X
ADD X executional microprogram
• Get the content of X T1 : MAR IR(Reference)
• Perform the addition T2 : MDR
M[MAR] T3 : A
(A) +
(MDR)
Control Signals:
MAR(IN) ;
IR(OUT) ;MDR(IN)
;MDR(OUT)
Micro-program
Control Unit
• Control Memory is a ROM Chip that is used to store the control signals in
the form of micro-instructions.

Control Signals
Microinstruction1
Microinstruction2
Microinstruction3 Micro-Program
.
.
• In main Memory, instructions are
Microinstruction N
stored which is called a program.
• Similarly, In control Memory,
Control Memory instructions are stored which is
(ROM Chip) called as Microinstruction.
Micro-program
Control Unit
• A control memory is a ROM Chip which stores microinstructions as
control word.
• Microprograming is the art of writing microprogram (micro-code) for
the control unit of CPU.
• Each control word consist of micro-operations.
• Each micro instruction when executes, it generates a sequence of
micro-operations to fetch instruction from memory, calculate
effective address, fetch operand etc.
Microprogramming is
Dynamic
• Computer system whose control unit is implemented with a
microprogram in WCS(Writable Control Storage).
• Microprogram can be changed by a systems programmer or
a user.
Micro-program
Control Unit
• Microinstruction: Contains a control word and a sequencing word
Control Word :- Contains all the control information required for
one clock cycle.
• Sequencing Word :- Contains information needed to decide the next
microinstruction address Micro operation.
• A microinstruction contains one or more micro operations to be
completed.
Micro-program
Control Unit
Micro-program
Control
•
Unit
Now, we will discuss how control signals are generated using mP- control
unit design? Who is generating? How Address key is generated? etc.

• All micro instructions are already stored in the control memory. So how to
fetch these micro-instructions from control memory? We need
address to fetch any data/ instruction from memory?
• The general configuration of a microprogrammed unit is
control demonstrated in the following block diagram:
Micro-program
Control Unit

• Microprogram Sequencer: It is also called as Next Address Generator as it determines the address
of the next micro-instruction i.e. read from the control memory.
• The device or program that generates address of next microinstruction to be executed is called
sequencer.
• While the micro operations are being executed, the next address is computed in the next address
generator circuit and then transferred into the control address register to read the next
microinstruction.
• The location of the next microinstruction may be the one next in sequence, or it may be located
somewhere else in the control memory.
• Typical functions of a microprogram sequencer are incrementing the control address register by
one, loading into the control address register an address from control memory, transferring an
external address, or loading an initial address to start the control operations.
Micro-program
Control Unit

Control Address Register(CAR): Microprogram Sequencer loads the address of

the next micro-instruction (i.e. which is going to be read from the control
memory) to the Control Address Register.
Micro-program
Control Unit

Control Memory: The Control Memory is actually a ROM Chip ,where all the
microinstructions are stored.

Control Data Register(CDR): It stores the micro instruction after reading from
control memory. The micro instruction when executed, it perform a set of
micro operation along with ; providing the address of the next instruction.

After storing the micro-operation in CDR, it automatically executes the set of

micro-oprations.
Address Sequencing OR Next Address Gen
• Process of finding address of next microinstruction to be executed is called
address sequencing.
i. Incrementing of the control address register.
ii. Unconditional branch or conditional branch, depending on status bit conditions.
iii. A facility for subroutine call and return.
iv.A mapping process from the bits of the instruction to an address for
control memory.
Micro-program
Control Unit
Micro-Instruction Format
F1 F2 F3 CD BR AD

3bits 3bits 3bits 2bits 7bits

2bits

F1, F2, F3 – Micro-operations fields

CD- Condition for branching
BR- Branch Field
AD- Address Field
Total No of Micro-operations = 24
(21 op + 3 No-op)

Micro-operation Fundamental
or basic operations that
are performed on the content of
register
e.g. MARPC
PCPC+1
Micro-program
Control Unit
Micro-Instruction Format
F1 F2 F3 CD BR AD

3bits 3bits 3bits 2bits 2bits 7bits

Status Condition(CD)

CD Condition Symbol Comments

00 Always =1 U Unconditional

01 IR(15th Bit) I Indirect Address

10 AC(15th Bit) S Signed Bit of AC

11 AC=0 Z Zero value in AC

Micro-program
Control Unit
Micro-Instruction Format
F1 F2 F3 CD BR AD

3bits 3bits 3bits 2bits 2bits 7bits

Branch Condition(BR)
BR Symbol Function
00 JMP CARAD,IF Condition(T)=1
CARCAR+1,IF Condition(T)=0
01 CALL CARAD,
IF Condition(T)=1
SBRCAR+1
CARCAR+1, IF Condition(T)=0
10 RET CARSBR (return from subroutine)
11 Z CAR(2,5)IR(11-14), CAR(0,1,6)0
 Block Diagram of Microprogram Status Condition
Control Unit CD Condition Symbol Comments
B R T S1 S0 L 00 Always =1 U Unconditional
0 0 0 0 0 0 01 IR(15th Bit) I Indirect
Address
0 0 1 0 1 0
10 AC(15th S Signed Bit of
0 1 0 0 0 0 Bit) AC
0 1 1 0 1 1
B
11 AC=0 Z Zero value in
AC
1 0 X 1 0 0 R
4*1
1 1 X 1 1 0
Branch Condition
Part of BR Symbol Function
CM
4*1 00 JMP CARAD,IF T=1
CARCAR+1,IF T=0
CAR=CAR+1
01 CALL CARAD,
T=1
SBRCAR+1
CARCAR+1,IF T=0
10 RET CARSBR
C D
11 Z CAR(2,5)IR(11-
14), CAR(0,1,6)0
 Types of Microinstruction
Format
• Horizontal
• Vertical
• Hybrid
Horizontal Microinstruction Format

• The control signals are represented in the decoded binary format that is 1 bit/CS. Example: If 64 Control
signals are present in the processor then 64 bits are required.
• More than 1 control signal can be enabled at a time.
• It supports longer control word.
• It is used in parallel processing applications.
• It allows higher degree of parallelism. If degree is n, n CS are enabled at a time.
• It requires no additional hardware(decoders). It means it is faster than Vertical Microprogrammed.
• Flexible than Hard Wired
 Types of Microinstruction
Format

• 64 bit micro instruction, one bit for each signal

• 64 control Signals(C1,C2,C3……….Cn)
• Size of control memory = 256 words
• Bits required to represent 256 words = 2^8; i.e. 8 bits
• Size of Next Address = 8 bits.
• Size of control word = 64+8 = 72 bits.
Vertical Micro-programmed
control Unitrepresented
• The control signals : in the encoded binary format.
• All control signals are not generated at the same time.
• So, we can compress the unwanted signals.
• For N control signals- Log2^(N) bits are required.
• use of ROM encoding to reduce the length of the control word.
• It supports shorter control words.
• It allows low degree of parallelism i.e., degree of parallelism is either 0 or 1.
• Requires an additional hardware (decoders) to generate control signals, it implies it is slower than horizontal
microprogrammed.
• Flexible than Horizontal Micro Programming
Types of Microinstruction
Format
64 control signals and 16 Flags. What is the size of control word used in bits and
control memory in byte using: a) Horizontal Programming b) Vertical programming
Nano
programming
• In the microprogrammed processor, an instruction fetched from primary memory is interpreted
by a microprogram, stored in the control memory.
• In some microprogrammed processor, the microinstructions are directly not used to generate the
signals for interpreting the user programs.
• The micro instructions do not directly issue the signals that control the hardware.
• They are used to access a second level control memory termed a Nano control memory nCM, that
directly controls the hardware.
Advantages of Nano programming
• Reduces total size of required control memory
• Greater design flexibility
Dis-Advantages of Nano programming
• Increased memory access time
LEVELS OF CONTROL MEMORY
• Micro controlled memory- higher level
• Nano control memory(Nano instructions)-lower level

Two Level control store organization for nano programming

• The nano-programmed control unit reduces effective control memory size.
• Effective CMSize= HM(logHM + log HN) + P × HN
Here HM(log HM + log HN ) ⇒ μprogram control memory
size P × HN ⇒nano program control memory size
HM ⇒Total no2 . of wo2 rds in μCM
HN ⇒Tota2l no. of2words in ηCM
P ⇒Total number of control signals to be generated
Question : Consider a η-programmed control unit with 1024 words in µ-
programmed control memory and 64 words in η-programmed control memory. The
system is using 48 control signals. What is the total control memory size?
 RISC and CISC
• Classification is based on the design of instruction sets:
• Reduced Instruction Set Computer (RISC)
• Complex Instruction Set Computer (CISC)
RISC :
Key characteristics of RISC Architecture are:
• Each instruction fits in a single word i.e., each instruction occupies exactly one word in memory.
• A load/store architecture is used, in which: Memory operands are accessed only using Load and
Store instructions.
• Requirement: Cycles per instruction = 1
• All operands involved in an arithmetic or logic operation must either be in processor registers, or one
of the operands may be given explicitly within the instruction word.
• Main idea: make hardware simpler by using an instruction set composed of a few basic steps for
loading, evaluating and storing operations (just like a load command will load data, store command
will store the data).
RISC and
CISC
Other characteristics of RISC Architecture:
• Uses highly-optimized set of instructions
• Instruction take single clock cycle to get executed.
• More number of general purpose registers.
• Simple Addressing Modes.
• Less Data types.
• Pipelining can be achieved easily i.e., sequence of instructions are performed in \pipelined" fashion to
overlap activity and reduce total execution time of a program.
• More RAM is required to store assembly level instructions.
• RISC uses Harvard memory model means it is Harvard Architecture.
• Restriction: each instruction must fit into a single word reduces the complexity.
RISC and
CISC
 RISC and
CISC
CISC:
• CISC Stands for Complex Instruction Set Computer, developed by the Intel.
Key characteristics of CISC Architecture are:
• Make use of more complex instructions which may span more than one word of memory.
• Each instruction may specify more complicated operations.
• Not constrained to the load/store architecture, in which arithmetic and logic operations can be performed
only on operands that are in processor registers.
• Main idea: make hardware complex because single instruction will do all loading, evaluating and
storing operations (just like a multiplication command will do all like loading data, evaluating and storing
it).
• Complex instruction, hence complex instruction decoding.
• Instruction may take more than single clock cycle to get executed.
• It provides easier programming in assembly language.
• Complex Addressing Modes, and more data types.
• CISC Architecture attempts to minimize the number of instructions per program but at the cost of
increase in
number of cycles per instruction
RISC and
CISC
• RISC focuses on simplicity and efficiency, making it ideal for applications where
speed and power efficiency are critical (e.g., embedded systems, mobile devices,
workstations)
• CISC with its complex instructions and multi-tasking abilities, is well-suited for
applications requiring fewer instructions and flexibility in memory operations
(e.g., desktop computers, servers).
CISC RISC

1. Complex Instruction Set Computer 1. Reduced Instruction Set Computer

2. Large No of Instructions 2. Less No of Instructions

3. Variable Length Instruction Format 3. Fixed Length Instruction Format

4. Large No of Addressing Modes 4. Few No of Addressing Modes

5. High Cost 5. Less Cost

6. More Powerful 6. Less Powerful

7. Several Cycle Instruction 7. Single Cycle Instruction

8. Manipulation directly in memory 8. . Only in Register

9. Micro-programmed Control Unit 9. Hardwired Control Unit

10. Examples: Mainframe, Motorola 6800, Intel 8080 10. MIPS, ARM, SPARC, Fugaku