research-article

An energy-efficient adaptive hybrid cache

Authors:

Karthik Gururaj,

Yi ZouAuthors Info & Claims

ISLPED '11: Proceedings of the 17th IEEE/ACM international symposium on Low-power electronics and design

Pages 67 - 72

Published: 01 August 2011 Publication History

Abstract

By reconfiguring part of the cache as software-managed scratchpad memory (SPM), hybrid caches manage to handle both unknown and predictable memory access patterns. However, existing hybrid caches provide a flexible partitioning of cache and SPM without considering adaptation to the run-time cache behavior. Previous cache set balancing techniques are either energy-inefficient or require serial tag and data array access. In this paper an adaptive hybrid cache is proposed to dynamically remap SPM blocks from high-demand cache sets to low-demand cache sets. This achieves 19%, 25%, 18% and 18% energy-runtime-production reductions over four previous representative techniques on a wide range of benchmarks.

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Cited By

Singh ADave SZardoshti PBrotzman RZhang CGuo XShrivastava ATan GSpear M(2020)SPX64ACM Transactions on Architecture and Code Optimization10.1145/343673018:1(1-26)Online publication date: 30-Dec-2020
https://dl.acm.org/doi/10.1145/3436730
Vijaykumar NJain AMajumdar DHsieh KPekhimenko GEbrahimi EHajinazar NGibbons PMutlu O(2018)A case for richer cross-layer abstractionsProceedings of the 45th Annual International Symposium on Computer Architecture10.1109/ISCA.2018.00027(207-220)Online publication date: 2-Jun-2018
https://dl.acm.org/doi/10.1109/ISCA.2018.00027
He JCallenes-Sloan J(2017)Designing large hybrid cache for future HPC systemsProceedings of the 25th High Performance Computing Symposium10.5555/3108096.3108105(1-12)Online publication date: 23-Apr-2017
https://dl.acm.org/doi/10.5555/3108096.3108105
Show More Cited By

Index Terms

An energy-efficient adaptive hybrid cache
1. Hardware
  1. Integrated circuits
    1. Semiconductor memory
      1. Dynamic memory

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Information & Contributors

Information

Published In

ISLPED '11: Proceedings of the 17th IEEE/ACM international symposium on Low-power electronics and design

August 2011

434 pages

ISBN:9781612846606

General Chairs:
Naehyuck Chang
Seoul National University
,
Hiroshi Nakamura
The University of Tokyo
,
Koji Inoue
Kyushu University
,
Program Chairs:
Kenichi Osada
Hitachi
,
Massimo Poncino
Politecnico Di Torino

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IEEE Press

Publication History

Published: 01 August 2011

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Research-article

Conference

ISLPED'11

Sponsor:

SIGDA

ISLPED'11: International Symposium on Low Power Electronics and Design

August 1 - 3, 2011

Fukuoka, Japan

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Overall Acceptance Rate 398 of 1,159 submissions, 34%

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Cited By

Singh ADave SZardoshti PBrotzman RZhang CGuo XShrivastava ATan GSpear M(2020)SPX64ACM Transactions on Architecture and Code Optimization10.1145/343673018:1(1-26)Online publication date: 30-Dec-2020
https://dl.acm.org/doi/10.1145/3436730
Vijaykumar NJain AMajumdar DHsieh KPekhimenko GEbrahimi EHajinazar NGibbons PMutlu O(2018)A case for richer cross-layer abstractionsProceedings of the 45th Annual International Symposium on Computer Architecture10.1109/ISCA.2018.00027(207-220)Online publication date: 2-Jun-2018
https://dl.acm.org/doi/10.1109/ISCA.2018.00027
He JCallenes-Sloan J(2017)Designing large hybrid cache for future HPC systemsProceedings of the 25th High Performance Computing Symposium10.5555/3108096.3108105(1-12)Online publication date: 23-Apr-2017
https://dl.acm.org/doi/10.5555/3108096.3108105
Siddique NBadawy ACook JResnick DJacob B(2017)LMStrProceedings of the International Symposium on Memory Systems10.1145/3132402.3132440(152-165)Online publication date: 2-Oct-2017
https://dl.acm.org/doi/10.1145/3132402.3132440
Reed EAlameldeen ANaeimi HStolt PJacob B(2017)Probabilistic replacement strategies for improving the lifetimes of NVM-based cachesProceedings of the International Symposium on Memory Systems10.1145/3132402.3132433(166-176)Online publication date: 2-Oct-2017
https://dl.acm.org/doi/10.1145/3132402.3132433
Komuravelli RSinclair MAlsop JHuzaifa MKotsifakou MSrivastava PAdve SAdve V(2015)StashACM SIGARCH Computer Architecture News10.1145/2872887.275037443:3S(707-719)Online publication date: 13-Jun-2015
https://dl.acm.org/doi/10.1145/2872887.2750374
Cheng HPoremba MShahidi NStalev IIrwin MKandemir MSampson JXie Y(2015)EECacheACM Transactions on Architecture and Code Optimization10.1145/275655212:2(1-22)Online publication date: 8-Jul-2015
https://dl.acm.org/doi/10.1145/2756552
Komuravelli RSinclair MAlsop JHuzaifa MKotsifakou MSrivastava PAdve SAdve VMarr DAlbonesi D(2015)StashProceedings of the 42nd Annual International Symposium on Computer Architecture10.1145/2749469.2750374(707-719)Online publication date: 13-Jun-2015
https://dl.acm.org/doi/10.1145/2749469.2750374
Wen HZhang WChatha KErnst RRaghunathan AIyer R(2014)Reducing cache leakage energy for hybrid SPM-cache architecturesProceedings of the 2014 International Conference on Compilers, Architecture and Synthesis for Embedded Systems10.1145/2656106.2656124(1-9)Online publication date: 12-Oct-2014
https://dl.acm.org/doi/10.1145/2656106.2656124
Cheng HPoremba MShahidi NStalev IIrwin MKandemir MSampson JXie YXie YKarnik TKhellah MMehra R(2014)EECacheProceedings of the 2014 international symposium on Low power electronics and design10.1145/2627369.2627661(303-306)Online publication date: 11-Aug-2014
https://dl.acm.org/doi/10.1145/2627369.2627661
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