Cited By
View all- Siddique NGrubel PBadawy ACook J(2018)A performance study of the time-varying cache behaviorThe Journal of Supercomputing10.1007/s11227-017-2144-174:2(665-695)Online publication date: 1-Feb-2018
LMStr: exploring shared hardware controlled scratchpad memory for multicores
Authors: 
Nafiul Alam Siddique, Abdel-Hameed A. Badawy, Jeanine Cook, David ResnickAuthors Info & Claims
Nafiul Alam Siddique, Abdel-Hameed A. Badawy, Jeanine Cook, David ResnickAuthors Info & ClaimsPages 152 - 165
Abstract
In this paper, we present an on-chip memory store called "Local Memory Store (LMStr)"which can be used with a regular cache hierarchy or solely as a redesigned scratchpad memory (SPM). The LMStr is a shared special kind of a SPM among the cores in a multicore processor. This memory hierarchy is hardware-controlled in terms of management of the store itself. Yet, compiler support is instrumental in deciding which data items/types should live in the store. Critical data should be stored in the LMStr according to its type (i.e., local, global, static, or temporary). The programmer can provide, at will, hints to the compiler to place certain data items in the LMStr. We evaluate our design using a matrix multiplication micro-application and multiple Mantevo mini-applications. Our results show that LMStr improves data movement by up to 21% compared to cache alone with a mere 3% area overhead. Not only that but LMStr improves the cycles per memory access by up to 40%. It also projects up to 85% less dynamic energy consumption compared to traditional cache.
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- LMStr: exploring shared hardware controlled scratchpad memory for multicores
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Published: 02 October 2017
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View all- Siddique NGrubel PBadawy ACook J(2018)A performance study of the time-varying cache behaviorThe Journal of Supercomputing10.1007/s11227-017-2144-174:2(665-695)Online publication date: 1-Feb-2018
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