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ORCIDChung-Yang Huang
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2020 – today
- 2022
[i2]Chin-Yi Cheng
, Chien-Yi Yang, Ren-Chu Wang, Yi-Hsiang Kuo, Hao-Chung Cheng, Chung-Yang Huang:
Qubit Mapping Toward Quantum Advantage. CoRR abs/2210.01306 (2022)- 2021
- [c36]Yu-Neng Wang, Yun-Rong Luo, Po-Chun Chien, Ping-Lun Wang, Hao-Ren Wang, Wan-Hsuan Lin, Jie-Hong Roland Jiang, Chung-Yang (Ric) Huang:
Compatible Equivalence Checking of X-Valued Circuits. ICCAD 2021: 1-9
2010 – 2019
- 2017
- [c35]Kuan-Lun Tseng, Yen-Liang Lin, Winston H. Hsu, Chung-Yang Huang:
Joint Sequence Learning and Cross-Modality Convolution for 3D Biomedical Segmentation. CVPR 2017: 3739-3746 - [i1]Kuan-Lun Tseng, Yen-Liang Lin, Winston H. Hsu, Chung-Yang Huang:
Joint Sequence Learning and Cross-Modality Convolution for 3D Biomedical Segmentation. CoRR abs/1704.07754 (2017) - 2016
- [c34]Kuan Fan, Ming-Jen Yang, Chung-Yang Huang:
Automatic abstraction refinement of TR for PDR. ASP-DAC 2016: 121-126 - 2014
- [j7]Bo-Han Wu, Chun-Ju Yang, Chung-Yang Huang:
A High-Throughput and Arbitrary-Distribution Pattern Generator for the Constrained Random Verification. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 33(1): 139-152 (2014) - [j6]Cheng-Yin Wu, Chi-An Wu, Chien-Yu Lai, Chung-Yang (Ric) Huang:
A Counterexample-Guided Interpolant Generation Algorithm for SAT-Based Model Checking. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 33(12): 1846-1858 (2014) - [c33]Chien-Yu Lai, Cheng-Yin Wu, Chung-Yang (Ric) Huang:
Adaptive interpolation-based model checking. ASP-DAC 2014: 744-749 - 2013
- [j5]Shao-Lun Huang, Wei-Hsun Lin, Po-Kai Huang, Chung-Yang Huang:
Match and Replace: A Functional ECO Engine for Multierror Circuit Rectification. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 32(3): 467-478 (2013) - [j4]Yu-Fu Yeh, Hsin-Cheng Lin, Chung-Yang Huang:
An Ultrasynchronization Checking Method With Trace-Driven Simulation for Fast and Accurate MPSoC Virtual Platform Simulation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 32(6): 928-939 (2013) - [c32]Cheng-Yin Wu, Chi-An Wu, Chien-Yu Lai, Chung-Yang (Ric) Huang:
A counterexample-guided interpolant generation algorithm for SAT-based model checking. DAC 2013: 118:1-118:6 - [c31]Bo-Han Wu, Chung-Yang (Ric) Huang:
A robust constraint solving framework for multiple constraint sets in constrained random verification. DAC 2013: 119:1-119:7 - [c30]Chun-Nan Chou, Chen-Kai Chu, Chung-Yang (Ric) Huang:
Conquering the scheduling alternative explosion problem of SystemC symbolic simulation. ICCAD 2013: 685-690 - 2012
- [c29]Shihheng Tsai, Man-Yu Li, Chung-Yang Huang:
A semi-formal min-cost buffer insertion technique considering multi-mode multi-corner timing constraints. ASP-DAC 2012: 505-510 - [c28]Chun-Nan Chou, Yen-Sheng Ho, Chiao Hsieh, Chung-Yang (Ric) Huang:
Symbolic model checking on SystemC designs. DAC 2012: 327-333 - [c27]Kai-Fu Tang, Po-Kai Huang, Chun-Nan Chou, Chung-Yang Huang:
Multi-patch generation for multi-error logic rectification by interpolation with cofactor reduction. DATE 2012: 1567-1572 - [c26]Bo-Han Wu, Chung-Yang (Ric) Huang:
A robust general constrained random pattern generator for constraints with variable ordering. ICCAD 2012: 109-114 - [c25]Hu-Hsi Yeh, Cheng-Yin Wu, Chung-Yang (Ric) Huang:
QuteRTL: Towards an Open Source Framework for RTL Design Synthesis and Verification. TACAS 2012: 377-391 - 2011
- [c24]Chung-Yang Huang, Yu-Fan Yin, Chih-Jen Hsu, Thomas B. Huang, Ting-Mao Chang:
SoC HW/SW verification and validation. ASP-DAC 2011: 297-300 - [c23]Shao-Lun Huang, Chi-An Wu, Kai-Fu Tang, Chang-Hong Hsu, Chung-Yang Huang:
A robust ECO engine by resource-constraint-aware technology mapping and incremental routing optimization. ASP-DAC 2011: 382-387 - [c22]Kai-Fu Tang, Chi-An Wu, Po-Kai Huang, Chung-Yang (Ric) Huang:
Interpolation-based incremental ECO synthesis for multi-error logic rectification. DAC 2011: 146-151 - [c21]Ting-Hao Lin, Chung-Yang (Ric) Huang:
Using SAT-based Craig interpolation to enlarge clock gating functions. DAC 2011: 621-626 - [c20]Yu-Fu Yeh, Chung-Yang Huang, Chi-An Wu, Hsin-Cheng Lin:
Speeding Up MPSoC virtual platform simulation by Ultra Synchronization Checking Method. DATE 2011: 353-358 - [c19]Shao-Lun Huang, Wei-Hsun Lin, Chung-Yang (Ric) Huang:
Match and replace - A functional ECO engine for multi-error circuit rectification. ICCAD 2011: 383-388 - [c18]Bo-Han Wu, Chun-Ju Yang, Chia-Cheng Tso, Chung-Yang (Ric) Huang:
Toward an extremely-high-throughput and even-distribution pattern generator for the constrained random simulation techniques. ICCAD 2011: 602-607 - [c17]Hu-Hsi Yeh, Cheng-Yin Wu, Chung-Yang (Ric) Huang:
Property-specific sequential invariant extraction for SAT-based unbounded model checking. ICCAD 2011: 674-678 - 2010
- [j3]Jie-Hong Roland Jiang, Chih-Chun Lee, Alan Mishchenko, Chung-Yang Huang:
To SAT or Not to SAT: Scalable Exploration of Functional Dependency. IEEE Trans. Computers 59(4): 457-467 (2010) - [c16]Kuen-Huei Lin, Siao-Jie Cai, Chung-Yang (Ric) Huang:
Speeding up SoC virtual platform simulation by data-dependency-aware synchronization and scheduling. ASP-DAC 2010: 143-148 - [c15]Hu-Hsi Yeh, Chung-Yang Huang:
Automatic constraint generation for guided random simulation. ASP-DAC 2010: 613-618 - [c14]Jing-Jia Nian, Shihgeng Tsai, Chung-Yang (Ric) Huang:
A unified multi-corner multi-mode static timing analysis engine. ASP-DAC 2010: 669-674 - [c13]Bo-Han Wu, Chun-Ju Yang, Chung-Yang Huang, Jie-Hong Roland Jiang:
A robust functional ECO engine by SAT proof minimization and interpolation techniques. ICCAD 2010: 729-734 - [c12]Chun-Nan Chou, Chang-Hong Hsu, Yueh-Tung Chao, Chung-Yang Huang:
Formal deadlock checking on high-level SystemC designs. ICCAD 2010: 794-799
2000 – 2009
- 2009
- [c11]Chi-An Wu, Ting-Hao Lin, Shao-Lun Huang, Chung-Yang Huang:
SAT-controlled redundancy addition and removal: a novel circuit restructuring technique. ASP-DAC 2009: 191-196 - [c10]Shihheng Tsai, Chung-Yang Huang:
A false-path aware formal static timing analyzer considering simultaneous input transitions. DAC 2009: 25-30 - [c9]Chih-Jen Hsu, Shao-Lun Huang, Chi-An Wu, Chung-Yang Huang:
Interpolant generation without constructing resolution graph. ICCAD 2009: 9-12 - 2008
- [c8]Chao-Yue Lai, Chung-Yang Huang, Kei-Yong Khoo:
Improving Constant-Coefficient Multiplier Verification by Partial Product Identification. DATE 2008: 813-818 - 2007
- [c7]Chi-An Wu, Ting-Hao Lin, Chih-Chun Lee, Chung-Yang Huang:
QuteSAT: a robust circuit-based SAT solver for complex circuit structure. DATE 2007: 1313-1318 - [c6]Chih-Chun Lee, Jie-Hong Roland Jiang, Chung-Yang Huang, Alan Mishchenko:
Scalable exploration of functional dependency by interpolation and incremental SAT solving. ICCAD 2007: 227-233 - [c5]Hsing-Chih Hung, Ting-Hao Lin, Chung-Yang Huang:
QuteIP: An IP qualification framework for System on Chip. SoCC 2007: 237-240 - 2001
- [j2]Chung-Yang Huang, Kwang-Ting Cheng:
Using word-level ATPG and modular arithmetic constraint-solvingtechniques for assertion property checking. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 20(3): 381-391 (2001) - [c4]Ganapathy Parthasarathy, Chung-Yang Huang, Kwang-Ting Cheng:
An analysis of ATPG and SAT algorithms for formal verification. HLDVT 2001: 177-182 - 2000
- [j1]Shi-Yu Huang, Kwang-Ting Cheng, Kuang-Chien Chen, Chung-Yang Huang, Forrest Brewer:
AQUILA: An Equivalence Checking System for Large Sequential Designs. IEEE Trans. Computers 49(5): 443-464 (2000) - [c3]Chung-Yang Huang, Kwang-Ting Cheng:
Assertion checking by combined word-level ATPG and modular arithmetic constraint-solving techniques. DAC 2000: 118-123 - [c2]Chung-Yang Huang, Bwolen Yang, Huan-Chih Tsai, Kwang-Ting Cheng:
Static property checking using ATPG vs. BDD techniques. ITC 2000: 309-316
1990 – 1999
- 1998
- [c1]Chung-Yang Huang, Yucheng Wang, Kwang-Ting Cheng:
LIBRA - a library-independent framework for post-layout performance optimization. ISPD 1998: 135-140
Coauthor Index
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