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2020 – today
- 2024
[j53]Hasitha Muthumala Waidyasooriya, Masanori Hariyama:
Performance evaluation of Word2vec accelerators exploiting spatial and temporal parallelism on DDR/HBM-based FPGAs. J. Supercomput. 80(12): 17192-17211 (2024)- 2022
- [j52]Hasitha Muthumala Waidyasooriya
, Hiroki Oshiyama, Yuya Kurebayashi, Masanori Hariyama, Masayuki Ohzeki:
A Scalable Emulator for Quantum Fourier Transform Using Multiple-FPGAs With High-Bandwidth-Memory. IEEE Access 10: 65103-65117 (2022) - [j51]Mitsuhiro Okada, Takayuki Suzuki, Naoya Nishio, Hasitha Muthumala Waidyasooriya, Masanori Hariyama:
FPGA-Accelerated Searchable Encrypted Database Management Systems for Cloud Services. IEEE Trans. Cloud Comput. 10(2): 1373-1385 (2022) - [j50]Chia-Yin Liu, Hasitha Muthumala Waidyasooriya, Masanori Hariyama:
Design space exploration for an FPGA-based quantum annealing simulator with interaction-coefficient-generators. J. Supercomput. 78(1): 1-17 (2022) - [j49]Hasitha Muthumala Waidyasooriya, Masanori Hariyama:
Temporal and spatial parallel processing of simulated quantum annealing on a multicore CPU. J. Supercomput. 78(6): 8733-8750 (2022) - [c44]Hasitha Muthumala Waidyasooriya, Yuta Ohma, Masanori Hariyama:
FPGA-Based Prototype of a Quantum Annealing Simulator for Sparse Ising Model. MCSoC 2022: 195-199 - [c43]Kosiro Obata, Hasitha Muthumala Waidyasooriya, Masanori Hariyama:
Implementation of an FPGA-Oriented Complex Number Computation Library Using Intel OneAPI DPC++. MWSCAS 2022: 1-4 - [c42]Hasitha Muthumala Waidyasooriya, Masanori Hariyama, Hiroe Iwasaki, Daisuke Kobayashi, Yuya Omori, Ken Nakamura, Koyo Nitta, Kimikazu Sano:
OpenCL-Based Design of an FPGA Accelerator for H.266/VVC Transform and Quantization. MWSCAS 2022: 1-4 - [c41]Hasitha Muthumala Waidyasooriya, Shutaro Ishihara, Masanori Hariyama:
Word2Vec FPGA Accelerator Based on Spatial and Temporal Parallelism. PDCAT 2022: 69-77 - 2021
- [j48]Hasitha Muthumala Waidyasooriya, Masanori Hariyama:
Highly-Parallel FPGA Accelerator for Simulated Quantum Annealing. IEEE Trans. Emerg. Top. Comput. 9(4): 2019-2029 (2021) - 2020
- [j47]Hasitha Muthumala Waidyasooriya, Masanori Hariyama:
A GPU-Based Quantum Annealing Simulator for Fully-Connected Ising Models Utilizing Spatial and Temporal Parallelism. IEEE Access 8: 67929-67939 (2020) - [j46]Shunsuke Tatsumi, Masanori Hariyama, Koichi Ito, Takafumi Aoki:
An FPGA accelerator for PatchMatch multi-view stereo using OpenCL. J. Real Time Image Process. 17(2): 215-227 (2020) - [c40]Chia-Yin Liu, Yi-Jung Chen, Masanori Hariyama:
Thermal-aware memory system synthesis for MPSoCs with 3D-stacked hybrid memories. SAC 2020: 546-553
2010 – 2019
- 2019
- [j45]Hasitha Muthumala Waidyasooriya, Masanori Hariyama:
Multi-FPGA Accelerator Architecture for Stencil Computation Exploiting Spacial and Temporal Scalability. IEEE Access 7: 53188-53201 (2019) - [j44]Hasitha Muthumala Waidyasooriya, Masanori Hariyama, Masamichi J. Miyama, Masayuki Ohzeki:
OpenCL-based design of an FPGA accelerator for quantum annealing simulation. J. Supercomput. 75(8): 5019-5039 (2019) - [c39]Tomoki Shoji, Hasitha Muthumala Waidyasooriya, Taisuke Ono, Masanori Hariyama, Yuichiro Aoki, Yuki Kondoh, Yaoko Nakagawa:
A Memory-Bandwidth-Efficient Word2vec Accelerator Using OpenCL for FPGA. CANDAR Workshops 2019: 103-108 - [c38]Chia-Yin Liu, Hasitha Muthumala Waidyasooriya, Masanori Hariyama:
Data-Transfer-Bottleneck-Less Architecture for FPGA-Based Quantum Annealing Simulation. CANDAR 2019: 164-170 - [c37]Hasitha Muthumala Waidyasooriya, Yasuaki Iimura, Masanori Hariyama:
Benchmarks for FPGA-Targeted High-Level-Synthesis. CANDAR 2019: 232-238 - [c36]Taisuke Ono, Tomoki Shoji, Hasitha Muthumala Waidyasooriya, Masanori Hariyama, Yuichiro Aoki, Yuki Kondoh, Yaoko Nakagawa:
FPGA-Based Acceleration of Word2vec using OpenCL. ISCAS 2019: 1-5 - 2018
- [c35]Hasitha Muthumala Waidyasooriya, Yusuke Araki, Masanori Hariyama:
Accelerator Architecture for Simulated Quantum Annealing Based on Resource-Utilization-Aware Scheduling and its Implementation Using OpenCL. ISPACS 2018: 335-340 - [c34]Yaya Watanabe, Masanori Hariyama, Mitsugi Shimoda:
A System for Estimating Optimal Resected Liver Regions Considering Practical Surgical Constraints. ISPACS 2018: 415-420 - [c33]Yuki Hiradate, Hasitha Muthumala Waidyasooriya, Masanori Hariyama, Masaaki Harada:
Architecture of an FPGA-Based Heterogeneous System for Code-Search Problems. SCFA 2018: 146-155 - [p1]Masato Motomura, Masanori Hariyama, Minoru Watanabe:
Advanced Devices and Architectures. Principles and Structures of FPGAs 2018: 207-231 - 2017
- [j43]Hasitha Muthumala Waidyasooriya, Masanori Hariyama, Kota Kasahara:
An FPGA Accelerator for Molecular Dynamics Simulation Using OpenCL. Int. J. Networked Distributed Comput. 5(1): 52-61 (2017) - [j42]Hasitha Muthumala Waidyasooriya, Tsukasa Endo, Masanori Hariyama, Yasuo Ohtera:
OpenCL-Based FPGA Accelerator for 3D FDTD with Periodic and Absorbing Boundary Conditions. Int. J. Reconfigurable Comput. 2017: 6817674:1-6817674:11 (2017) - [j41]Hasitha Muthumala Waidyasooriya, Yasuhiro Takei, Shunsuke Tatsumi, Masanori Hariyama:
OpenCL-Based FPGA-Platform for Stencil Computation and Its Optimization Methodology. IEEE Trans. Parallel Distributed Syst. 28(5): 1390-1402 (2017) - [c32]Taisuke Ono, Hasitha Muthumala Waidyasooriya, Masanori Hariyama, Tsukasa Ishigaki:
Architecture of an FPGA accelerator for LDA-based inference. SNPD 2017: 357-362 - 2016
- [j40]Shunsuke Tatsumi, Masanori Hariyama, Norikazu Ikoma:
Evaluation of an OpenCL-Based FPGA Platform for Particle Filter. J. Adv. Comput. Intell. Intell. Informatics 20(5): 743-754 (2016) - [j39]Hasitha Muthumala Waidyasooriya, Masanori Hariyama:
Hardware-Acceleration of Short-Read Alignment Based on the Burrows-Wheeler Transform. IEEE Trans. Parallel Distributed Syst. 27(5): 1358-1372 (2016) - [c31]Hasitha Muthumala Waidyasooriya, Masanori Hariyama:
FPGA-based deep-pipelined architecture for FDTD acceleration using OpenCL. ICIS 2016: 1-6 - [c30]Hasitha Muthumala Waidyasooriya, Masanori Hariyama, Kota Kasahara:
Architecture of an FPGA accelerator for molecular dynamics simulation using OpenCL. ICIS 2016: 1-5 - 2015
- [j38]Yasuhiro Takei, Hasitha Muthumala Waidyasooriya, Masanori Hariyama, Michitaka Kameyama:
Data-Transfer-Aware Design of an FPGA-Based Heterogeneous Multicore Platform with Custom Accelerators. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 98-A(12): 2658-2669 (2015) - [j37]Zhengfan Xia, Masanori Hariyama, Michitaka Kameyama:
Asynchronous Domino Logic Pipeline Design Based on Constructed Critical Data Path. IEEE Trans. Very Large Scale Integr. Syst. 23(4): 619-630 (2015) - [c29]Hasitha Muthumala Waidyasooriya, Daisuke Ono, Masanori Hariyama:
Hardware-oriented succinct-data-structure based on block-size-constrained compression. SoCPaR 2015: 136-140 - 2014
- [j36]Hasitha Muthumala Waidyasooriya, Masanori Hariyama, Yasuhiro Takei, Michitaka Kameyama:
FDTD Acceleration for Cylindrical Resonator Design Based on the Hybrid of Single and Double Precision Floating-Point Computation. J. Comput. Eng. 2014: 634269:1-634269:8 (2014) - [c28]Hasitha Muthumala Waidyasooriya, Daisuke Ono, Masanori Hariyama, Michitaka Kameyama:
Efficient data transfer scheme using word-pair-encoding-based compression for large-scale text-data processing. APCCAS 2014: 639-642 - 2013
- [j35]Yoshiya Komatsu, Masanori Hariyama, Michitaka Kameyama:
Architecture of an Asynchronous FPGA for Handshake-Component-Based Design. IEICE Trans. Inf. Syst. 96-D(8): 1632-1644 (2013) - [j34]Yasuhiro Takei, Hasitha Muthumala Waidyasooriya, Masanori Hariyama, Michitaka Kameyama:
Evaluation of an FPGA-Based Heterogeneous Multicore Platform with SIMD/MIMD Custom Accelerators. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 96-A(12): 2576-2586 (2013) - [j33]Shota Ishihara, Noriaki Idobata, Masanori Hariyama, Michitaka Kameyama:
Flexible Ferroelectric-Capacitor Element for Low Power and Compact Logic-in-Memory Architectures. J. Multiple Valued Log. Soft Comput. 20(5-6): 595-623 (2013) - [c27]Hasitha Muthumala Waidyasooriya, Masanori Hariyama, Michitaka Kameyama:
Implementation of a custom hardware-accelerator for short-read mapping using Burrows-Wheeler alignment. EMBC 2013: 651-654 - 2012
- [j32]Hasitha Muthumala Waidyasooriya, Yosuke Ohbayashi, Masanori Hariyama, Michitaka Kameyama:
Memory-Access-Driven Context Partitioning for Window-Based Image Processing on Heterogeneous Multicore Processors. IEICE Trans. Inf. Syst. 95-D(2): 354-363 (2012) - [j31]Zhengfan Xia, Shota Ishihara, Masanori Hariyama, Michitaka Kameyama:
Design of High-Performance Asynchronous Pipeline Using Synchronizing Logic Gates. IEICE Trans. Electron. 95-C(8): 1434-1443 (2012) - [j30]Yoshitaka Hiramatsu, Hasitha Muthumala Waidyasooriya, Masanori Hariyama, Tohru Nojiri, Kunio Uchiyama, Michitaka Kameyama:
Acceleration of Block Matching on a Low-Power Heterogeneous Multi-Core Processor Based on DTU Data-Transfer with Data Re-Allocation. IEICE Trans. Electron. 95-C(12): 1872-1882 (2012) - [c26]Hasitha Muthumala Waidyasooriya, Yasuhiro Takei, Masanori Hariyama, Michitaka Kameyama:
FPGA implementation of heterogeneous multicore platform with SIMD/MIMD custom accelerators. ISCAS 2012: 1339-1342 - [c25]Zhengfan Xia, Shota Ishihara, Masanori Hariyama, Michitaka Kameyama:
Dual-rail/single-rail hybrid logic design for high-performance asynchronous circuit. ISCAS 2012: 3017-3020 - 2011
- [j29]Hasitha Muthumala Waidyasooriya, Masanori Hariyama, Michitaka Kameyama:
Memory Allocation for Window-Based Image Processing on Multiple Memory Modules with Simple Addressing Functions. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 94-A(1): 342-351 (2011) - [j28]Shota Ishihara, Ryoto Tsuchiya, Yoshiya Komatsu, Masanori Hariyama, Michitaka Kameyama:
Implementation of a Low-Power FPGA Based on Synchronous/Asynchronous Hybrid Architecture. IEICE Trans. Electron. 94-C(10): 1669-1679 (2011) - [j27]Shota Ishihara, Noriaki Idobata, Yoshihiro Nakatani, Masanori Hariyama:
A Switch Block for Multi-Context FPGAs Based on Floating-Gate-MOS Functional Pass-Gates Using Multiple/Binary Valued Hybrid Signals? J. Multiple Valued Log. Soft Comput. 17(5-6): 553-580 (2011) - [j26]Hasitha Muthumala Waidyasooriya, Yosuke Ohbayashi, Masanori Hariyama, Michitaka Kameyama:
Memory Allocation Exploiting Temporal Locality for Reducing Data-Transfer Bottlenecks in Heterogeneous Multicore Processors. IEEE Trans. Circuits Syst. Video Technol. 21(10): 1453-1466 (2011) - [j25]Shota Ishihara, Masanori Hariyama, Michitaka Kameyama:
A Low-Power FPGA Based on Autonomous Fine-Grain Power Gating. IEEE Trans. Very Large Scale Integr. Syst. 19(8): 1394-1406 (2011) - [c24]Yoshiya Komatsu, Shota Ishihara, Masanori Hariyama, Michitaka Kameyama:
An implementation of an asychronous FPGA based on LEDR/four-phase-dual-rail hybrid architecture. ASP-DAC 2011: 89-90 - 2010
- [j24]Shota Ishihara, Yoshiya Komatsu, Masanori Hariyama, Michitaka Kameyama:
An Asynchronous FPGA Based on LEDR/4-Phase-Dual-Rail Hybrid Architecture. IEICE Trans. Electron. 93-C(8): 1338-1348 (2010) - [j23]Shota Ishihara, Noriaki Idobata, Masanori Hariyama, Michitaka Kameyama:
A Switch Block Architecture for Multi-Context FPGAs Based on a Ferroelectric-Capacitor Functional Pass-Gate Using Multiple/Binary Valued Hybrid Signals. IEICE Trans. Inf. Syst. 93-D(8): 2134-2144 (2010) - [j22]Hasitha Muthumala Waidyasooriya, Daisuke Okumura, Masanori Hariyama, Michitaka Kameyama:
Task Allocation with Algorithm Transformation for Reducing Data-Transfer Bottlenecks in Heterogeneous Multi-Core Processors: A Case Study of HOG Descriptor Computation. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 93-A(12): 2570-2580 (2010) - [c23]Hasitha Muthumala Waidyasooriya, Masanori Hariyama, Michitaka Kameyama:
Architecture of an FPGA-Oriented Heterogeneous Multi-core Processor with SIMD-Accelerator Cores. ERSA 2010: 179-186 - [c22]Masanori Hariyama, Ryoto Tsuchiya, Shota Ishihara, Michitaka Kameyama:
An Field-Programmable VLSI Based on Synchronous/Asynchronous Hybrid Architecture. ERSA 2010: 271-274 - [c21]Hasitha Muthumala Waidyasooriya, Daisuke Okumura, Masanori Hariyama, Michitaka Kameyama:
Mapping for a Heterogeneous Multi-Core Media Processor Considering the Data Transfer Time. ERSA 2010: 281-284
2000 – 2009
- 2009
- [j21]Hasitha Muthumala Waidyasooriya, Masanori Hariyama, Michitaka Kameyama:
Implementation of a Partially Reconfigurable Multi-Context FPGA Based on Asynchronous Architecture. IEICE Trans. Electron. 92-C(4): 539-549 (2009) - [j20]Yasuhiro Kobayashi, Masanori Hariyama, Michitaka Kameyama:
Optimal Periodic Memory Allocation for Image Processing With Multiple Windows. IEEE Trans. Very Large Scale Integr. Syst. 17(3): 403-416 (2009) - [c20]Shota Ishihara, Masanori Hariyama, Michitaka Kameyama:
A low-power FPGA based on autonomous fine-grain power-gating. ASP-DAC 2009: 119-120 - [c19]Shota Ishihara, Yoshiya Komatsu, Masanori Hariyama, Michitaka Kameyama:
An Asynchronous Field-Programmable VLSI Using LEDR/4-Phase-Dual-Rail Protocol Converters. ERSA 2009: 145-150 - [c18]Masanori Hariyama, Keita Tanji, Michitaka Kameyama:
FPGA Implementation of a High-Speed Stereo Matching Processor Based on Recursive Computation. ERSA 2009: 263-266 - [c17]Shota Ishihara, Noriaki Idobata, Masanori Hariyama, Michitaka Kameyama:
A Fine-Grain SIMD Architecture Based on Flexible Ferroelectric-Capacitor Logic. ERSA 2009: 271-274 - [c16]Hasitha Muthumala Waidyasooriya, Masanori Hariyama, Michitaka Kameyama:
Acceleration of Optical-Flow Extraction Using Dynamically Reconfigurable ALU Arrays. ERSA 2009: 291-294 - 2008
- [j19]Masanori Hariyama, Naoto Yokoyama, Michitaka Kameyama:
Design of a Trinocular-Stereo-Vision VLSI Processor Based on Optimal Scheduling. IEICE Trans. Electron. 91-C(4): 479-486 (2008) - [j18]Hasitha Muthumala Waidyasooriya, Weisheng Chong, Masanori Hariyama, Michitaka Kameyama:
Multi-Context FPGA Using Fine-Grained Interconnection Blocks and Its CAD Environment. IEICE Trans. Electron. 91-C(4): 517-525 (2008) - [j17]Masanori Hariyama, Shota Ishihara, Michitaka Kameyama:
Evaluation of a Field-Programmable VLSI Based on an Asynchronous Bit-Serial Architecture. IEICE Trans. Electron. 91-C(9): 1419-1426 (2008) - [j16]Yasuhiro Kobayashi, Masanori Hariyama, Michitaka Kameyama:
Memory Allocation for Multi-Resolution Image Processing. IEICE Trans. Inf. Syst. 91-D(10): 2386-2397 (2008) - [j15]Hasitha Muthumala Waidyasooriya, Masanori Hariyama, Michitaka Kameyama:
Evaluation of Interconnect-Complexity-Aware Low-Power VLSI Design Using Multiple Supply and Threshold Voltages. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 91-A(12): 3596-3606 (2008) - [c15]Hasitha Muthumala Waidyasooriya, Masanori Hariyama, Michitaka Kameyama:
Implementation of a Multi-Context FPGA Based on Flexible-Context-Partitioning. ERSA 2008: 201-207 - [c14]Masanori Hariyama, Shota Ishihara, Noriaki Idobata, Michitaka Kameyama:
Non-Volatile Multi-Context FPGAs Using Hybrid Multiple-Valued/Binary Context Switching Signals. ERSA 2008: 309-310 - [c13]Masanori Hariyama, Kensaku Yamashita, Michitaka Kameyama:
FPGA implementation of a vehicle detection algorithm using three-dimensional information. IPDPS 2008: 1-5 - 2006
- [j14]Masanori Hariyama, Shigeo Yamadera, Michitaka Kameyama:
Minimizing Energy Consumption Based on Dual-Supply-Voltage Assignment and Interconnection Simplification. IEICE Trans. Electron. 89-C(11): 1551-1558 (2006) - [j13]Masanori Hariyama, Sho Ogata, Michitaka Kameyama:
A Multi-Context FPGA Using Floating-Gate-MOS Functional Pass-Gates. IEICE Trans. Electron. 89-C(11): 1655-1661 (2006) - [c12]W. H. Muthumala, Masanori Hariyama, Michitaka Kameyama:
GA-Based Assignment of Supply and Threshold Voltages and Interconnection Simplification for Low Power VLSI Design. APCCAS 2006: 1264-1267 - [c11]Masanori Hariyama, Michitaka Kameyama:
A Multi-Context FPGA Using a Floating-Gate-MOS Functional Pass-Gate and Its CAD Environment. APCCAS 2006: 1803-1806 - [c10]Yoshihiro Nakatani, Masanori Hariyama, Michitaka Kameyama:
Architecture of a multi-context FPGA using a hybrid multiple-valued/binary context switching signal. IPDPS 2006 - [c9]Yoshihiro Nakatani, Masanori Hariyama, Michitaka Kameyama:
Switch Block Architecture for Multi-Context FPGAs Using Hybrid Multiple-Valued/Binary Context Switching Signals. ISMVL 2006: 17 - [c8]Masanori Hariyama, Michitaka Kameyama, Yasuhiro Kobayashi:
Optimal Periodical Memory Allocation for Logic-in-Memory Image Processors. ISVLSI 2006: 193-198 - 2005
- [j12]Masanori Hariyama, Haruka Sasaki, Michitaka Kameyama:
Architecture of a Stereo Matching VLSI Processor Based on Hierarchically Parallel Memory Access. IEICE Trans. Inf. Syst. 88-D(7): 1486-1491 (2005) - [j11]Weisheng Chong, Masanori Hariyama, Michitaka Kameyama:
Low-Power Field-Programmable VLSI Using Multiple Supply Voltages. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 88-A(12): 3298-3305 (2005) - [j10]Masanori Hariyama, Yasuhiro Kobayashi, Haruka Sasaki, Michitaka Kameyama:
FPGA Implementation of a Stereo Matching Processor Based on Window-Parallel-and-Pixel-Parallel Architecture. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 88-A(12): 3516-3522 (2005) - [j9]Masanori Hariyama:
Editorial: VLSI Computing for Real-World Intelligent Systems. J. Robotics Mechatronics 17(4): 371 (2005) - [j8]Masanori Hariyama, Tetsuya Aoyama, Michitaka Kameyama:
Genetic Approach to Minimizing Energy Consumption of VLSI Processors Using Multiple Supply Voltages. IEEE Trans. Computers 54(6): 642-650 (2005) - [c7]Weisheng Chong, Sho Ogata, Masanori Hariyama, Michitaka Kameyama:
Architecture of a Multi-Context FPGA Using Reconfigurable Context Memory. IPDPS 2005 - [c6]Masanori Hariyama, Weisheng Chong, Sho Ogata, Michitaka Kameyama:
Novel Switch Block Architecture Using Non-Volatile Functional Pass-Gate for Multi-Context FPGAs. ISVLSI 2005: 46-50 - 2004
- [c5]Weisheng Chong, Masanori Hariyama, Michitaka Kameyama:
Low-Power Field-Programmable VLSI Processor Using Dynamic Circuits. ISVLSI 2004: 243-248 - [c4]Naotaka Ohsawa, Osamu Sakamoto, Masanori Hariyama, Michitaka Kameyama:
Program-Counter-Less Bit-Serial Field-Programmable VLSI Processor with Mesh-Connected Cellular Array Structure. ISVLSI 2004: 258-259 - 2002
- [c3]Naotaka Ohsawa, Masanori Hariyama, Michitaka Kameyama:
High-Performance Field Programmable VLSI Processor Based on a Direct Allocation of a Control/Data Flow Graph. ISVLSI 2002: 95-100 - 2001
- [c2]Masanori Hariyama, Toshiki Takeuchi, Michitaka Kameyama:
VLSI Processor for Reliable Stereo Matching Based on Adaptive Window-Size Selection. ICRA 2001: 1168-1173 - 2000
- [j7]Masanori Hariyama, Seunghwan Lee, Michitaka Kameyama:
Architecture of a high-performance stereo vision VLSI processor. Adv. Robotics 14(5): 329-332 (2000) - [j6]Masanori Hariyama, Michitaka Kameyama:
Stereo Vision VLSI Processor Based on Pixel-Serial and Window-Parallel Architecture. J. Robotics Mechatronics 12(5): 521-526 (2000) - [j5]Masanori Hariyama, Michitaka Kameyama:
Path Planning Based on Distance Transformation and Its VLSI Implementation. J. Robotics Mechatronics 12(5): 527-533 (2000) - [j4]Hideki Kazama, Masanori Hariyama, Michitaka Kameyama:
Design of a VLSI Processor Based on an Immediate Output Generation Scheduling for Ball-Trajectory Prediction. J. Robotics Mechatronics 12(5): 534-540 (2000)
1990 – 1999
- 1998
- [c1]Masanori Hariyama, Michitaka Kameyama:
Design of a Collision Detection VLSI Processor Based on Minimization of Area-Time Products. ICRA 1998: 3691-3696 - 1997
- [j3]Masanori Hariyama, Yuichi Araumi, Michitaka Kameyama:
A robot vision VLSI processor for the rectangular solid representation of three-dimensional objects. Syst. Comput. Jpn. 28(2): 54-61 (1997) - 1996
- [j2]Masanori Hariyama, Yuichi Araumi, Michitaka Kameyama:
Robot Vision VLSI Processor for the Rectangular Solid Representation of 3-Dimensional Objects. J. Robotics Mechatronics 8(6): 501-507 (1996) - 1994
- [j1]Masanori Hariyama, Michitaka Kameyama:
Architecture of a CAM-Based Collision Detection VLSI Processor for Intelligent Vehicles. J. Robotics Mechatronics 6(2): 137-142 (1994)
Coauthor Index
[j38] [j37] [j36] [c28] [j35] [j34] [j33] [c27] [j32] [j31] [j30] [c26] [c25] [j29] [j28] [j26] [j25] [c24] [j24] [j23] [j22] [c23] [c22] [c21] [j21] [j20] [c20] [c19] [c18] [c17] [c16] [j19] [j18] [j17] [j16] [j15] [c15] [c14] [c13] [j14] [j13] [c12] [c11] [c10] [c9] [c8] [j12] [j11] [j10] [j8] [c7] [c6] [c5] [c4] [c3] [c2] [j7] [j6] [j5] [j4] [c1] [j3] [j2] [j1]
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