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ORCID19. VDAT 2015: Ahmedabad, India
- 19th International Symposium on VLSI Design and Test, VDAT 2015, Ahmedabad, India, June 26-29, 2015. IEEE Computer Society 2015, ISBN 978-1-4799-1743-3
- Shanky Saxena, Ritu Sharma, B. D. Pant:
Design and development of cantilever-type MEMS based piezoelectric energy harvester. 1-4 - Rakesh Trivedi, N. M. Devashrayee
, Usha Sandeep Mehta, N. M. Desai, Himanshu Patel:
Development of Radiation Hardened by Design(RHBD) primitive gates using 0.18μm CMOS technology. 1-2 - Priyanka Choudhury, Debanjali Nath, Vivek Rai, Sambhu Nath Pradhan:
Thermal aware AND-OR-XOR network synthesis. 1-6 - Krishnendu Guha, Debasri Saha, Amlan Chakrabarti:
RTNA: Securing SOC architectures from confidentiality attacks at runtime using ART1 neural networks. 1-6 - Suraj Gupta, Sabir Ali Mondal, Hafizur Rahaman:
Improved supply regulation and temperature compensated current reference circuit with low process variations. 1-6 - Nupur Jain, Biswajit Mishra:
CORDIC on a configurable serial architecture for biomedical signal processing applications. 1-6 - Anand D. Darji, Raviraj P. Makwana:
High-performance multiplierless DCT architecture for HEVC. 1-5 - Prokash Ghosh, Sandip Ghosh, Pritpal Singh, Saurabh Mishra:
Case study: Re-visiting SoC verification challenges and best practices. 1-9 - Priyankar Talukdar:
On logic depth per pipelining stage with power aware flop, wave and hybrid pipelining with gate size and area constraints. 1-6 - Vibhor Pareek, Gaurvi Goyal:
Area optimized CMOS layouts of a 50 Gb/s low power 4: 1 multiplexer. 1-6 - Hari Shanker Gupta, Shweta Kirkire, Sunil Bhati, Ravi Shankar Chaurasia, Sanjeev Mehta, Arup Roy Choudhary, Dipen Patel, Jaymin Vaghela:
Bipolar voltage level shifter. 1-5 - Mudasir Bashir, Sreehari Rao Patri, K. S. R. Krishna Prasad:
On-chip CMOS temperature sensor with current calibrated accuracy of -1.1°C to +1.4°C (3σ) from -20°C to 150°C. 1-5 - Mudasir Bashir, Sreehari Rao Patri, K. S. R. Krishna Prasad:
High speed self biased current sense amplifier for low power CMOS SRAM's. 1-5 - Niyati Gupta, Manoj Kumar, Vijay Laxmi, Manoj Singh Gaur, Mark Zwolinski:
σLBDR: Congestion-aware logic based distributed routing for 2D NoC. 1-6 - Ruchi, S. Dasgupta:
Sensitivity analysis of DRV for various configurations of SRAM. 1-5 - Vaishali H. Dhare, Usha Mehta:
Defect characterization and testing of QCA devices and circuits: A survey. 1-2 - Rohit Kumar, Manisha Pattanaik:
A novel dual multiplier floating point multiply accumulate architecture. 1-2 - Arvind Kumar Sharma, Neeraj Mishra, Naushad Alam, Sudeb Dasgupta, Anand Bulusu:
Pre-layout estimation of performance and design of basic analog circuits in stress enabled technologies. 1-6 - Ashish Sharma, Prachi Upadhyay, Ruby Ansar, Vijay Laxmi, Lava Bhargava, Manoj Singh Gaur, Mark Zwolinski:
A framework for thermal aware reliability estimation in 2D NoC. 1-6 - K. Sudeendra Kumar, Rakesh Chanamala, Sauvagya Ranjan Sahoo, Kamala Kanta Mahapatra:
An improved AES Hardware Trojan benchmark to validate Trojan detection schemes in an ASIC design flow. 1-6 - Ramandeep Kaur, Rahul Malhotra, Sujay Deb:
MAC based FIR filter: A novel approach for low-power real-time de-noising of ECG signals. 1-5 - Rahul Malhotra, Sujay Deb, Fabio Carlucci:
A novel approach to reusable time-economized STIL based pattern development. 1-5 - (Withdrawn) Super-scale architecture enhancement of LEON3 core for DSP application. 1-2
- Sonal Yadav, Vijay Laxmi, Manoj Singh Gaur, Megha Bhargava:
C2-DLM: Cache coherence aware dual link mesh for on-chip interconnect. 1-2 - D. Malathi, R. Greeshma, R. Sanjay, B. Venkataramani:
A 4 bit medium speed flash ADC using inverter based comparator in 0.18μm CMOS. 1-5 - Priyanka Sharma, Sunil Pandey, Pravin A. Dwaramwar:
An inductorless receiver front-end for multiband wireless applications. 1-5 - S. Dinesh Kumar, S. K. Noor Mahammad:
A novel adiabatic SRAM cell implementation using split level charge recovery logic. 1-2 - Kunal Parihar, M. Venkatesh, Ravikumar Patel:
Realistic dynamic timing verification for complex mixed signal hard macro's using UVM. 1-2 - Sonam Negi, Pitchaiah Madduri:
Implementation of high speed radix-10 parallel multiplier using Verilog. 1-5 - Sonam Negi, Pitchaiah Madduri:
Implementation of high speed radix-10 parallel multiplier using Verilog. 1-5 - Yogesh Chaurasiya, Surabhi Bhargava, Arvind Kumar Sharma, Baljit Kaur, Bulusu Anand:
Timing model for two stage buffer and its application in ECSM characterization. 1-6 - Jaishree Mayank, Arijit Mondal:
Performance optimization of real time control systems using variable time period. 1-6 - Shikhar Tewari, Kirmender Singh:
Intuitive design of PTAT and CTAT circuits for MOSFET based temperature sensor using Inversion Coefficient based approach. 1-6 - Shounak Chakraborty, Shirshendu Das, Hemangee K. Kapoor:
Power aware cache miss reduction by energy efficient victim retention. 1-6 - Kartheek Vanapalli, Hemangee K. Kapoor, Shirshendu Das:
An efficient searching mechanism for dynamic NUCA in chip multiprocessors. 1-5 - Jitendra Yadav, Soumendu Sinha, Amit Sharma, Rekha Chaudhary, Ravindra Mukhiya, Rishi Sharma, Vinod K. Khanna:
Simulation and characterization of dual-gate SOI MOSFET, on-chip fabricated with ISFET. 1-5 - Renu Kumawat, Vineet Sahula, Manoj Singh Gaur:
Modeling and synthesis of molecular memory. 1-2 - Praneet Bhatia, Bhupendra Singh Reniwal, Santosh Kumar Vishvakarma:
An offset-tolerant self-correcting sense amplifier for robust high speed SRAM. 1-6 - Rekha Chaudhary, Amit Sharma, Soumendu Sinha, Jitendra Yadav, Rishi Sharma, Ravindra Mukhiya, Vinod K. Khanna:
Fabrication and characterization of Al gate n-MOSFET, on-chip fabricated with Si3N4 ISFET. 1-4 - Mayank Punetha, Yashvir Singh:
An integrable trench LDMOS transistor on SOI for RF power amplifiers in PICs. 1-4 - Yagya D. Mishra, Mohammad S. Hashmi, Akhilesh C. Mishra:
An efficient approach for estimating the impact of SSO noise on LPDDR2 timing budget. 1-6 - Ranjan Mehera, Arpan Chakraborty, Piyali Datta, Rajat Kumar Pal:
A cost-optimal algorithm for guard zone computation including detection and exclusion of overlapping. 1-6 - Kshitij Agrawal, Shubhajit Roy Chowdhury:
Real time multisensor Laplacian fusion on FPGA. 1-4 - Sabyasachee Banerjee, Subhashis Majumder, Debesh K. Das:
Partitioning-based test time reduction for core-based 3DICs. 1-5 - Madhav Rao, Neha Oraon, S. Ranganatha:
Design and simulation of magnetic logic device for next generation data processing. 1-6 - Samta D. Talatule, Pravin Zode, Pradnya Zode:
A secure architecture for the design for testability structures. 1-6 - Ronak Patel, Amisha Naik, Amit Singh, Archana Arya, Pulkit Bhatnagar:
Advanced UPF based voltage-aware verification for IOs. 1-2 - Arindam Banerjee, Debesh Kumar Das:
Squarer design with reduced area and delay. 1-6 - Sauvagya Ranjan Sahoo, K. Sudeendra Kumar, Kamalakanta Mahapatra:
A novel ROPUF for hardware security. 1-2 - Priyankar Talukdar:
BONY: An algorithm to generate large synthetic combinational benchmark circuits. 1-2 - Jitendra Yadav, Pallavi Das, Abhinav Jain, Anuj Grover:
Area compact 5T portless SRAM cell for high density cache in 65nm CMOS. 1-4 - Vishnuram Abhinav, Amitabh Chatterjee, Dheeraj Kumar Sinha, Rajan Singh:
Methodology for optimizing ESD protection for high speed LVDS based I/Os. 1-5 - Rohan Sinha, Pranay Samanta:
Analysis of stability and different speed boosting assist techniques towards the design and optimization of high speed SRAM cell. 1-6 - Bidesh Chakraborty, Bhanu Pratap Singh, M. Chinnapureddy, Mamata Dalui, Biplab K. Sikdar:
Design of coherence verification unit for heterogeneous CMPs. 1-6 - Harikrishna Parmar, Usha Sandeep Mehta:
A Hamming code based technique to resolve the bit flip impact on compressed VLSI test data in IP core based SoC. 1-6 - Saha Mousumi, Navneet Kumar Gautam, Biplab K. Sikdar:
A fault tolerant test hardware for L1 cache module in tile CMPs architecture. 1-6 - Satyabrata Dash, Vivek Bangera, Vinay B. Y. Kumar, Gaurav Trivedi, Sachin B. Patkar:
Parallel two step random walk algorithm to analyze VLSI power grid networks. 1-2 - Yogesh M. Jain, Aviraj R. Jadhav, Harish V. Dixit, Akshay S. Hindole, Jithin R. Vadakoott, Devendra Bilaye:
A novel VLSI design of DCTQ processor for FPGA implementation. 1-5 - Rajdeep Kumar Nath, Bibhash Sen, Rachit Daga, Nilesh Chakraborty, Harsh Tibrewal, Biplab K. Sikdar:
Fault masking in Quantum-dot cellular automata using prohibitive logic circuit. 1-5 - Ramprasad Nambisan, S. Santosh Kumar, B. D. Pant:
Sensitivity and non-linearity study and performance enhancement in bossed diaphragm piezoresistive pressure sensor. 1-6 - Hasmukh P. Koringa, Bhushan D. Joshi, Vipul Shah:
High power gain low noise amplifier design for next generation 1-7GHz wideband RF frontend RFIC using 0.18μm CMOS. 1-5 - Anil Sharma:
Design and analysis of a touch mode MEMS capacitive pressure sensor for IUPC. 1-6 - Govinda Rao Locharla, K. Sudeendra Kumar, Kamala Kanta Mahapatra, Samit Ari:
Implementation of input data buffering and scheduling methodology for 8 parallel MDC FFT. 1-6 - Saroj Mondal, Roy P. Paily:
An efficient on-chip energy processing circuit for micro-scale energy harvesting systems. 1-5 - Sanjay Kumar Wadhwa, Avinash Chandra Tripathi:
Measurement of de-assertion threshold of power-on-reset circuits. 1-4 - Michael Skaggs, Sushmita Kadiyala Rao, Ryan W. Robucci, Nilanjan Banerjee, Chintan Patel:
Transient current estimation using S3C (Standard cell current transient characterization). 1-6 - Debarati Dey, Pradipta Roy, Debashis De:
Molecular modeling of Nano bio p-i-n FET. 1-6 - Pradyumna Galgali, Surendra S. Rathod:
Analysis of CMOS inhibitory synapse with varying neurotransmitter concentration, reuptake time and spread delay. 1-5 - Sameer Pawanekar, Gaurav Trivedi:
TSV aware standard cell placement for 3D ICs. 1-6 - Sameer Pawanekar, Gaurav Trivedi:
Net weighing based timing driven standard cell placer. 1-6 - Binal B. Baraiya, Hiren K. Mewada, Amish B. Shah:
FPGA based disk controller and photon counter of optical polarimeter. 1-6 - Vinayak Patil, Aneesh Raveendran, P. M. Sobha, A. David Selvakumar, Vivian Desalphine:
Out of order floating point coprocessor for RISC V ISA. 1-7 - Aneesh Raveendran, Vinayak Patil, Vivian Desalphine, P. M. Sobha, A. David Selvakumar:
RISC-V out-of-order data conversion co-processor. 1-2 - Yericharla Mary Asha Latha, Gargi Khanna:
Design and simulative analysis of a batteryless Teflon coated capacitive pressure sensor for glaucoma diagnosis. 1-5 - Rajesh C. Junghare, Vinayak Pachkawade, Rajendra M. Patrikar:
A 2.47 GHz ultra NanoCrystaline diamond disk resonator with temperature compensation for RF application. 1-2 - Vinayak Pachkawade, Rajesh C. Junghare, Rajendra M. Patrikar:
A small bandwidth microelectromechanical ring resonator-based bandpass filter. 1-5 - Prashant Khot, Rajashekar B. Shettar:
Design of area efficient and low power bandgap voltage reference using sub-threshold MOS transistors. 1-5 - Anupam Bhar, Santanu Chattopadhyay, Indranil Sengupta, Rohit Kapur:
GA based diagnostic test pattern generation for transition faults. 1-6 - Pravin Zode, Raghavendra B. Deshmukh:
Side channel attack resistant architecture for elliptic curve cryptography. 1-2 - Munishamanna Rithesh, G. Harish, B. V. Bhargav Ram, Siva Sankar Yellampalli:
Detection and analysis of hardware trojan using scan chain method. 1-6 - N. Ravi Kiran, G. Harish, A. Karthik, Siva Sankar Yellampalli:
Low power and hardware cost STUMPS BIST. 1-4 - M. R. Gowthami, G. Harish, B. V. Bhargav Ram, Siva Sankar Yellampalli:
Modified low power scan based technique. 1-5 - Rajendra Patel, Arvind Rajawat:
Instruction cache design space exploration for embedded software applications. 1-5 - Rangwani Varsha, Rajat Arora, T. V. S. Ram, Amit Patel:
Design and implementation of DVB-S2 transport stream for onboard processing satellite. 1-6 - Darshana Upadhyay, Trishla Shah, Priyanka Sharma:
Cryptanalysis of hardware based stream ciphers and implementation of GSM stream cipher to propose a novel approach for designing n-bit LFSR stream cipher. 1-6 - Toral Shah, Anzhela Yu. Matrosova, Virendra Singh:
PDF testability of a combinational circuit derived by covering ROBDD nodes using Invert-And-Or circuits. 1-2 - Rohan Sinha, Bhawana Singh Nirwan, Mohammad S. Hashmi:
A new row decoding architecture for fast wordline charging in NOR type Flash memories. 1-5 - S. Santosh Kumar, B. D. Pant:
Fabrication and characterization of pressure sensor, and enhancement of output characteristics by modification of operating pressure range. 1-4 - Namrata Singh, Sujay Deb:
Analysis and design guidelines for customized logic families in CMOS. 1-2 - Vinay M. M., Roy P. Paily, Anil Mahanta:
A low-power subthreshold LNA for mobile applications. 1-5 - Jai Gopal Pandey, Arindam Karmakar, Chandra Shekhar, S. Gurunarayanan:
An embedded framework for accurate object localization using center of gravity measure with mean shift procedure. 1-6 - Vijay Savani, N. M. Devashrayee:
Analysis & characterization of dual tail current based dynamic latch comparator with modified SR latch using 90nm technology. 1-2 - Debasis Dhal, Piyali Datta, Arpan Chakrabarty, Sudipta Roy, Rajat Kumar Pal:
An impressive approach for incorporating parallelism in designing DMFB with cross contamination avoidance. 1-6 - Mohammad Waris, Urvi Mehta, Rajiv Kumaran, Sanjeev Mehta, Arup Roy Chowdhury:
An all digital delay lock loop architecture for high precision timing generator. 1-6 - M. Santhanalakshmi, K. Yasoda:
Verilog-A implementation of energy-efficient SAR ADCs for biomedical application. 1-6 - Shaurya Kaushal, Pulkit Kumar Dubey, Gaurav Prabhudesai, B. D. Pant:
Novel design for wideband piezoelectric vibrational energy harvester (P-VEH). 1-5 - Hari Sarkar, Sudakshina Kundu:
Standby leakage current estimation model for multi threshold CMOS inverter circuit in deep submicron technology. 1-6 - Shyamapada Mukherjee, Suchismita Roy:
Multi terminal net routing for island style FPGAs using nearly-2-SAT computation. 1-6 - G. Ganesh Kumar, Subhendu Kumar Sahoo:
Implementation of a high speed multiplier for high-performance and low power applications. 1-4 - Sarit Chakraborty, Chandan Das, Susanta Chakraborty, Parthasarathi Dasgupta:
A novel two phase heuristic routing technique in digital microfluidic biochip. 1-6 - N. Sudha, D. Bharat Chandrahas:
A pipelined memory-efficient architecture for face detection and tracking on a multicore environment. 1-2 - Gagan Deep Verma, Manisha Pattanaik:
Performance study of side block oxide band gap engineered SONOS: A device simulation approach. 1-4 - Sandeep D'Souza, Soumya J., Santanu Chattopadhyay:
A constructive heuristic for application mapping onto an express channel based Network-on-Chip. 1-6 - Arpita Dutta, Santanu Chattopadhyay:
Particle swarm optimization approach for low temperature BIST. 1-6 - Anshuman Chandra, Santosh Kulkarni, Subramanian Chebiyam, Rohit Kapur:
Designing efficient combinational compression architecture for testing industrial circuits. 1-6 - Karri Manikantta Reddy, Kumar Y. B. Nithin, Dheeraj Sharma, M. H. Vasantha:
Low power, high speed error tolerant multiplier using approximate adders. 1-6 - Mansi S. Masrani, Raghavendra Chilukuri:
Low-leakage architecture for embedded ROM. 1-2 - V. S. Rashmi, Giridhar Somayaji, Sirisha Bhamidipathi:
A methodology to reuse random IP stimuli in an SoC functional verification environment. 1-5 - Nitin S. Kale:
Introduction to MEMS; their applications as sensors for chemical & bio sensing. 1-2 - N. Sudha:
Multicore processor - Architecture and programming. 1-2 - Manoj Singh Gaur, Vijay Laxmi, Mark Zwolinski, Manoj Kumar, Niyati Gupta, Ashish Sharma:
Network-on-chip: Current issues and challenges. 1-3 - Santanu Chattopadhyay:
Power- and thermal-aware testing of VLSI circuits and systems. 1 - Ansuman Banerjee, Arijit Mondal, Arnab Sarkar, Santosh Biswas:
Real-time embedded systems analysis - From theory to practice. 1-2 - Shri H. S. Jatana, Nilesh M. Desai:
SCL 180nm CMOS foundry: High reliability ASIC design for aerospace applications. 1-2 - Aminul Islam:
Technology scaling and its side effects. 1
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