default search action
Google
Google Scholar
Semantic Scholar
Internet Archive Scholar
CiteSeerX
ORCIDHemangee K. Kapoor
Hemangee Kalpesh Kapoor
Person information
- affiliation: Indian Institute of Technology Guwahati, India
Refine list
refinements active!
zoomed in on ?? of ?? records
view refined list in
export refined list as
showing all ?? records
2020 – today
- 2024
[j41]Hemangee K. Kapoor, David A. Patterson:
Increasing Diversity, Equity, and Inclusion Awareness: An Example from India. Commun. ACM 67(4): 35-36 (2024)- [j40]N. S. Aswathy
, Hemangee K. Kapoor:
Migration-aware slot-based memory request scheduler to guarantee QoS in DRAM-PCM hybrid memories. J. Syst. Archit. 152: 103174 (2024) - [j39]Arijit Nath, Hemangee K. Kapoor:
AmLuCEP: Amalgamating LUT-based Compression and Adaptive Encoding Assisted Block Placement To Improve Lifetime of PCM-based Main Memories. ACM Trans. Design Autom. Electr. Syst. 29(6): 1-24 (2024) - [c78]N. S. Aswathy, Hemangee K. Kapoor:
Write Intensity based Foresightful Page Migration for Hybrid memories. ISQED 2024: 1-8 - [c77]Rishabh Mahanta, Hemangee K. Kapoor:
DynaCache: A Checkpoint Aware Reconfigurable Cache for Intermittently Powered Computing Systems. VLSI-SoC 2024: 1-6 - [c76]Zeeshan Anwar, Imlijungla Longchar, Hemangee K. Kapoor:
Bit-Beading: Stringing bit-level MAC results for Accelerating Neural Networks. VLSID 2024: 216-221 - 2023
- [j38]Arijit Nath, Hemangee K. Kapoor:
CADEN: Compression-Assisted Adaptive Encoding to Improve Lifetime of Encrypted Nonvolatile Main Memories. IEEE Embed. Syst. Lett. 15(1): 45-48 (2023) - [j37]Palash Das, Shashank Sharma, Hemangee K. Kapoor:
ALAMNI: Adaptive LookAside Memory Based Near-Memory Inference Engine for Eliminating Multiplications in Real-Time. IEEE Trans. Computers 72(3): 693-706 (2023) - [j36]Sheel Sindhu Manohar, Hemangee K. Kapoor:
CAPMIG: Coherence-Aware Block Placement and Migration in Multiretention STT-RAM Caches. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 42(2): 411-422 (2023) - [j35]N. S. Aswathy, Arnab Sarkar, Hemangee K. Kapoor:
A Predictable QoS-aware Memory Request Scheduler for Soft Real-time Systems. ACM Trans. Embed. Comput. Syst. 22(2): 39:1-39:25 (2023) - [j34]Sonal Yadav, Vijay Laxmi, Hemangee K. Kapoor, Manoj Singh Gaur, Amit Kumar:
Adaptive distribution of control messages for improving bandwidth utilization in multiple NoC. J. Supercomput. 79(15): 17208-17246 (2023) - [c75]Palash Das, Hemangee K. Kapoor:
NDIE: A Near DRAM Inference Engine Exploiting DIMM's Parallelism. APCCAS 2023: 333-337 - [c74]Beth Plale, Preeti Malakar, Meenakshi D'Souza, Hemangee K. Kapoor, Yogesh Simmhan, Ilkay Altintas, Manohar Swaminathan:
CCGRID 2023: A Holistic Approach to Inclusion and Belonging. CCGrid 2023: 684-685 - [c73]N. S. Aswathy, Hemangee K. Kapoor:
AGRAS: Aging and memory request rate aware scheduler for PCM memories. ISQED 2023: 1-8 - [c72]Nishant Bharti, Arijit Nath, Swati Upadhyay, Hemangee K. Kapoor:
ZOCHEN: Compression Using Zero Chain Elimination and Encoding to Improve Endurance of Non-Volatile Memories. ISQED 2023: 1-8 - [c71]Aishwarya Gupta, N. S. Aswathy, Hemangee K. Kapoor:
Look before you leap: An Access-based Prudent Page Migration for Hybrid Memories. VLSI-SoC 2023: 1-6 - [c70]Imlijungla Longchar, Hemangee K. Kapoor:
ADaMaT: Towards an Adaptive Dataflow for Maximising Throughput in Neural Network Inference. VLSI-SoC 2023: 1-6 - [c69]N. S. Aswathy, Deep Bhuinya, Hemangee K. Kapoor:
WIB-SAR: Write Intensity Based Selective Address Remapping. VLSID 2023: 1-6 - 2022
- [j33]Hemangee Kalpesh Kapoor, Mausam, Venkatesh Raman:
Welcome back! Commun. ACM 65(11): 40-42 (2022) - [j32]Arijit Nath, Hemangee K. Kapoor:
SWEL-COFAE : Wear Leveling and Adaptive Encoding Assisted Compression of Frequent Words in Non-Volatile Main Memories. IEEE Trans. Computers 71(9): 2263-2276 (2022) - [j31]Sheel Sindhu Manohar, Sparsh Mittal, Hemangee K. Kapoor:
CORIDOR: Using COherence and TempoRal LocalIty to Mitigate Read Disurbance ErrOR in STT-RAM Caches. ACM Trans. Embed. Comput. Syst. 21(1): 2:1-2:24 (2022) - [j30]Arijit Nath, Hemangee K. Kapoor:
Pop-Crypt: Identification and Management of Popular Words for Enhancing Lifetime of EnCrypted Nonvolatile Main Memories. IEEE Trans. Very Large Scale Integr. Syst. 30(9): 1219-1229 (2022) - [c68]Imlijungla Longchar, Amey Varhade, Chetan Ingle, Saurabh Baranwal, Hemangee K. Kapoor:
CluSpa: Computation Reduction in CNN Inference by exploiting Clustering and Sparsity. AIMLSystems 2022: 9:1-9:8 - [c67]Hemangee K. Kapoor:
DEI activities at the ACM and How to make CS education more inclusive: Keynote Abstract. COMPUTE 2022: 4 - [c66]Palash Das, Ajay Joshi, Hemangee K. Kapoor:
Hydra: A near hybrid memory accelerator for CNN inference. DATE 2022: 1017-1022 - [c65]N. S. Aswathy, Sreesiddesh Bhavanasi, Arnab Sarkar, Hemangee K. Kapoor:
SRS-Mig: Selection and Run-time Scheduling of page Migration for improved response time in hybrid PCM-DRAM memories. ACM Great Lakes Symposium on VLSI 2022: 217-222 - [c64]Arijit Nath, Hemangee K. Kapoor:
CoSeP: Compression and Content-based Selection Procedure to Improve Lifetime of Encrypted Non-Volatile Main Memories. ACM Great Lakes Symposium on VLSI 2022: 393-396 - [c63]Swati Upadhyay, Arijit Nath, Hemangee K. Kapoor:
Exploiting successive identical words and differences with dynamic bases for effective compression in Non-Volatile Memories. ISLPED 2022: 9:1-9:6 - [c62]Neelkamal, Sonal Yadav, Hemangee K. Kapoor:
i-MAX: Just-In-Time Wakeup of Maximally Gated Router for Power Efficient Multiple NoC. VDAT 2022: 107-117 - [c61]Imlijungla Longchar, Palash Das, Hemangee K. Kapoor:
ZaLoBI: Zero avoiding Load Balanced Inference accelerator. VLSI-SoC 2022: 1-6 - 2021
- [j29]Palash Das, Hemangee K. Kapoor:
CLU: A Near-Memory Accelerator Exploiting the Parallelism in Convolutional Neural Networks. ACM J. Emerg. Technol. Comput. Syst. 17(2): 22:1-22:25 (2021) - [j28]Sanjay Moulik, Arnab Sarkar, Hemangee K. Kapoor:
TARTS: A Temperature-Aware Real-Time Deadline-Partitioned Fair Scheduler. J. Syst. Archit. 112: 101847 (2021) - [j27]Khushboo Rani, Hemangee K. Kapoor:
Investigating Frequency Scaling, Nonvolatile, and Hybrid Memory Technologies for On-Chip Routers to Support the Era of Dark Silicon. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 40(4): 633-645 (2021) - [j26]Palash Das, Hemangee K. Kapoor:
nZESPA: A Near-3D-Memory Zero Skipping Parallel Accelerator for CNNs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 40(8): 1573-1585 (2021) - [j25]Sukarn Agarwal, Hemangee K. Kapoor:
Improving the Performance of Hybrid Caches Using Partitioned Victim Caching. ACM Trans. Embed. Comput. Syst. 20(1): 5:1-5:27 (2021) - [c60]Manojit Ghose, Hemangee K. Kapoor:
WeiSub: Weighted Subset-based Cache Replacement Policy for Last Level Caches. ICCCNT 2021: 1-7 - [c59]Mayank Baranwal, Udbhav Chugh, Shivang Dalal, Sukarn Agarwal, Hemangee K. Kapoor:
DAMUS: Dynamic Allocation based on Write Frequency in MUlti-Retention STT-RAM based Last Level Caches. ISQED 2021: 469-475 - [c58]Arijit Nath, Manik B. Bhosle, Hemangee K. Kapoor:
SeNonDiv: Securing Non-Volatile Memory using Hybrid Memory and Critical Data Diversion. ISQED 2021: 522-528 - [c57]N. S. Aswathy, Hemangee K. Kapoor, Arnab Sarkar:
A Soft Real-time Memory Request Scheduler for Phase Change Memory Systems. RTCSA 2021: 109-118 - 2020
- [j24]Arijit Nath, Sukarn Agarwal, Hemangee K. Kapoor:
Reuse Distance-based Victim Cache for Effective Utilisation of Hybrid Main Memory System. ACM Trans. Design Autom. Electr. Syst. 25(3): 24:1-24:32 (2020) - [c56]Khushboo Rani, Hemangee K. Kapoor:
ZENCO: Zero-bytes based ENCOding for Non-Volatile Buffers in On-Chip Interconnects. DAC 2020: 1-6 - [c55]Chirag Joshi, Palash Das, Ashwini A. Kulkarni, Hemangee K. Kapoor:
Dimming Hybrid Caches to Assist in Temperature Control of Chip MultiProcessors. ACM Great Lakes Symposium on VLSI 2020: 487-492 - [c54]Khushboo Rani, Sukarn Agarwal, Hemangee K. Kapoor:
DidaSel: dirty data based selection of VC for effective utilization of NVM buffers in on-chip interconnects. ISLPED 2020: 151-156 - [c53]Arijit Nath, Hemangee K. Kapoor:
WELCOMF: wear leveling assisted compression using frequent words in non-volatile main memories. ISLPED 2020: 157-162 - [c52]Sukarn Agarwal, Hemangee K. Kapoor:
LiNoVo: Longevity Enhancement of Non-Volatile Last Level Caches in Chip Multiprocessors. ISVLSI 2020: 194-199 - [c51]Shashank Suman, Hemangee K. Kapoor:
Reinforcement Learning Based Refresh Optimized Volatile STT-RAM Cache. ISVLSI 2020: 222-227
2010 – 2019
- 2019
- [j23]Khushboo Rani, Hemangee K. Kapoor:
Write-variation aware alternatives to replace SRAM buffers with non-volatile buffers in on-chip interconnects. IET Comput. Digit. Tech. 13(6): 481-492 (2019) - [j22]Dipika Deb, John Jose, Shirshendu Das, Hemangee K. Kapoor:
Cost effective routing techniques in 2D mesh NoC using on-chip transmission lines. J. Parallel Distributed Comput. 123: 118-129 (2019) - [j21]Sheel Sindhu Manohar, Hemangee K. Kapoor:
Dynamic reconfiguration of embedded-DRAM caches employing zero data detection based refresh optimisation. J. Syst. Archit. 100 (2019) - [j20]Sukarn Agarwal, Hemangee K. Kapoor:
Improving the Lifetime of Non-Volatile Cache by Write Restriction. IEEE Trans. Computers 68(9): 1297-1312 (2019) - [j19]Shounak Chakraborty, Hemangee K. Kapoor:
Exploring the Role of Large Centralised Caches in Thermal Efficient Chip Design. ACM Trans. Design Autom. Electr. Syst. 24(5): 52:1-52:28 (2019) - [j18]Khushboo Rani, Hemangee K. Kapoor:
Write Variation Aware Buffer Assignment for Improved Lifetime of Non-Volatile Buffers in On-Chip Interconnects. IEEE Trans. Very Large Scale Integr. Syst. 27(9): 2191-2204 (2019) - [c50]Sonal Yadav, Vijay Laxmi, Manoj Singh Gaur, Hemangee K. Kapoor:
Improving Static Power Efficiency via Placement of Network Demultiplexer over Control Plane of Router in Multi-NoCs. DAC 2019: 225 - [c49]Sukarn Agarwal, Hemangee K. Kapoor:
Enhancing the Lifetime of Non-Volatile Caches by Exploiting Module-Wise Write Restriction. ACM Great Lakes Symposium on VLSI 2019: 213-218 - [c48]Sheel Sindhu Manohar, Sukarn Agarwal, Hemangee K. Kapoor:
Towards Optimizing Refresh Energy in embedded-DRAM Caches using Private Blocks. ACM Great Lakes Symposium on VLSI 2019: 225-230 - [c47]Neelkamal, Sonal Yadav, Hemangee K. Kapoor:
Lightweight Message Encoding of Power-Gating Controller for On-Time Wakeup of Gated Router in Network-on-Chip. ISED 2019: 1-6 - [c46]Sheel Sindhu Manohar, Hemangee K. Kapoor:
Refresh optimised embedded-dram caches based on zero data detection. SAC 2019: 635-642 - [c45]Khushboo Rani, Hemangee K. Kapoor:
Write Variation Aware Non-volatile Buffers for On-Chip Interconnects. VLSID 2019: 7-12 - [c44]Arijit Nath, Hemangee K. Kapoor:
Write Variation Aware Cache Partitioning for Improved Lifetime in Non-volatile Caches. VLSID 2019: 425-430 - 2018
- [j17]Sanjay Moulik, Arnab Sarkar, Hemangee K. Kapoor:
Energy aware frame based fair scheduling. Sustain. Comput. Informatics Syst. 18: 66-77 (2018) - [j16]Shounak Chakraborty, Hemangee K. Kapoor:
Analysing the Role of Last Level Caches in Controlling Chip Temperature. IEEE Trans. Sustain. Comput. 3(4): 289-305 (2018) - [j15]Sukarn Agarwal, Hemangee K. Kapoor:
Reuse-Distance-Aware Write-Intensity Prediction of Dataless Entries for Energy-Efficient Hybrid Caches. IEEE Trans. Very Large Scale Integr. Syst. 26(10): 1881-1894 (2018) - [c43]Palash Das, Hemangee K. Kapoor:
Towards Near-Data Processing of Compare Operations in 3D-Stacked Memory. ACM Great Lakes Symposium on VLSI 2018: 243-248 - [c42]Ashwini A. Kulkarni, Shounak Chakraborty, Shrinivas P. Mahajan, Hemangee K. Kapoor:
Utility Aware Snoozy Caches for Energy Efficient Chip Multi-Processors. ACM Great Lakes Symposium on VLSI 2018: 249-254 - [c41]Khushboo Rani, Sukarn Agarwal, Hemangee K. Kapoor:
Non-blocking Gated Buffers for Energy Efficient on-chip Interconnects in the era of Dark Silicon. ISED 2018: 74-79 - [c40]Ashwini A. Kulkarni, Chirag Joshi, Khushboo Rani, Sukarn Agarwal, Shrinivas P. Mahajan, Hemangee K. Kapoor:
Towards Analysing the Effect of Snoozy Caches on the Temperature of Tiled Chip Multi-Processors. ISED 2018: 230-235 - [c39]Ashwini A. Kulkarni, Khushboo Rani, Sukarn Agarwal, Shrinivas P. Mahajan, Hemangee K. Kapoor:
Towards Analysing the Effect of Hybrid Caches on the Temperature of Tiled Chip Multi-Processors. iSES 2018: 52-57 - [c38]Sonal Yadav, Vijay Laxmi, Hemangee K. Kapoor, Manoj Singh Gaur, Mark Zwolinski:
A Power Efficient Crossbar Arbitration in Multi-NoC for Multicast and Broadcast Traffic. iSES 2018: 243-248 - [c37]Alankar V. Umdekar, Arijit Nath, Shirshendu Das, Hemangee K. Kapoor:
Dynamic Thermal Management by Using Task Migration in Conjunction with Frequency Scaling for Chip Multiprocessors. VLSID 2018: 31-36 - [c36]Sanjay Moulik, Arnab Sarkar, Hemangee K. Kapoor:
DPFair Scheduling with Slowdown and Suspension. VLSID 2018: 43-48 - [c35]Palash Das, Shivam Lakhotia, Prabodh Shetty, Hemangee K. Kapoor:
Towards Near Data Processing of Convolutional Neural Networks. VLSID 2018: 380-385 - [c34]Sharma Priya, Sukarn Agarwal, Hemangee K. Kapoor:
Fault Tolerance in Network on Chip Using Bypass Path Establishing Packets. VLSID 2018: 457-458 - 2017
- [j14]Shounak Chakraborty, Hemangee K. Kapoor:
Performance linked dynamic cache tuning: A static energy reduction approach in tiled CMPs. Microprocess. Microsystems 52: 221-235 (2017) - [j13]Shirshendu Das, Hemangee K. Kapoor:
Dynamic Associativity Management in Tiled CMPs by Runtime Adaptation of Fellow Sets. IEEE Trans. Parallel Distributed Syst. 28(8): 2229-2243 (2017) - [c33]Shirshendu Das, Hemangee K. Kapoor:
Latency Aware Block Replacement for L1 Caches in Chip Multiprocessor. ISVLSI 2017: 182-187 - [c32]Sukarn Agarwal, Hemangee K. Kapoor:
Targeting inter set write variation to improve the lifetime of non-volatile cache using fellow sets. VLSI-SoC 2017: 1-6 - [c31]Sukarn Agarwal, Hemangee K. Kapoor:
Lifetime Enhancement of Non-Volatile Caches by Exploiting Dynamic Associativity Management Techniques. VLSI-SoC (Selected Papers) 2017: 46-71 - [c30]Sukarn Agarwal, Hemangee K. Kapoor:
Towards a Better Lifetime for Non-volatile Caches in Chip Multiprocessors. VLSID 2017: 29-34 - [c29]Shounak Chakraborty, Hemangee K. Kapoor:
Towards Controlling Chip Temperature by Dynamic Cache Reconfiguration in Multiprocessors. VLSID 2017: 75-80 - 2016
- [j12]Ka Lok Man, Chi-Un Lei, Hemangee K. Kapoor, Tomas Krilavicius, Jieming Ma, Nan Zhang:
PAFSV: A Formal Framework for Specification and Analysis of SystemVerilog. Comput. Informatics 35(1): 143-176 (2016) - [j11]Shirshendu Das, Hemangee K. Kapoor:
A Framework for Block Placement, Migration, and Fast Searching in Tiled-DNUCA Architecture. ACM Trans. Design Autom. Electr. Syst. 22(1): 4:1-4:26 (2016) - [c28]Shounak Chakraborty, Shirshendu Das, Hemangee K. Kapoor:
Static energy efficient cache reconfiguration for dynamic NUCA in tiled CMPs. SAC 2016: 1739-1744 - [c27]Shirshendu Das, Hemangee K. Kapoor:
Dynamic associativity enabled DNUCA to improve block localisation in tiled CMPs. SAC 2016: 1745-1750 - [c26]Sukarn Agarwal, Hemangee K. Kapoor:
Towards a dynamic associativity enabled write prediction based hybrid cache. VDAT 2016: 1-6 - [c25]Surajit Das, Shirshendu Das, Hemangee K. Kapoor:
Tag only storage for capacity optimised last level cache in chip multiprocessors. VDAT 2016: 1-6 - [c24]Sukarn Agarwal, Hemangee K. Kapoor:
Restricting writes for energy-efficient hybrid cache in multi-core architectures. VLSI-SoC 2016: 1-6 - [c23]Shounak Chakraborty, Hemangee K. Kapoor:
Static energy reduction by performance linked dynamic cache resizing. VLSI-SoC 2016: 1-6 - [c22]Shirshendu Das, Hemangee K. Kapoor:
Towards a Better Cache Utilization by Selective Data Storage for CMP Last Level Caches. VLSID 2016: 92-97 - 2015
- [j10]Pradeep Kumar Biswal, K. Mishra, Santosh Biswas, Hemangee K. Kapoor:
A Discrete Event System Approach to Online Testing of Speed Independent Circuits. VLSI Design 2015: 651785:1-651785:16 (2015) - [c21]Shounak Chakraborty, Shirshendu Das, Hemangee K. Kapoor:
Performance Constrained Static Energy Reduction Using Way-Sharing Target-Banks. IPDPS Workshops 2015: 444-453 - [c20]Hemangee K. Kapoor, Shirshendu Das, Shounak Chakraborty:
Static energy reduction by performance linked cache capacity management in tiled CMPs. SAC 2015: 1913-1918 - [c19]Shirshendu Das, Hemangee K. Kapoor:
Dynamic associativity management using utility based way-sharing. SAC 2015: 1919-1924 - [c18]Shounak Chakraborty, Shirshendu Das, Hemangee K. Kapoor:
Power aware cache miss reduction by energy efficient victim retention. VDAT 2015: 1-6 - [c17]Kartheek Vanapalli, Hemangee K. Kapoor, Shirshendu Das:
An efficient searching mechanism for dynamic NUCA in chip multiprocessors. VDAT 2015: 1-5 - [c16]Shirshendu Das, Hemangee K. Kapoor:
Exploration of Migration and Replacement Policies for Dynamic NUCA over Tiled CMPs. VLSID 2015: 141-146 - 2014
- [j9]Shirshendu Das, Hemangee K. Kapoor:
Victim retention for reducing cache misses in tiled chip multiprocessors. Microprocess. Microsystems 38(4): 263-275 (2014) - [c15]B. Venkateswarlu Naik, Shirshendu Das, Hemangee K. Kapoor:
RT-DVS for Power Optimization in Multiprocessor Real-Time Systems. ICIT 2014: 24-29 - [c14]M. Lakshmi Prasad, Shirshendu Das, Hemangee K. Kapoor:
An Approach for Multicast Routing in Networks-on-Chip. ICIT 2014: 299-304 - [c13]Apoorv Kumar, Hemangee K. Kapoor:
Modelling and analysis of wireless communication over Networks-on-Chip. VDAT 2014: 1-6 - [c12]Narendra Kumar Meena, Hemangee K. Kapoor, Shounak Chakraborty:
A New Recursive Partitioning Multicast Routing Algorithm for 3D Network-on-Chip. VDAT 2014: 1-6 - 2013
- [j8]Hemangee K. Kapoor, G. Bhoopal Rao, Sharique Arshi, Gaurav Trivedi:
A Security Framework for NoC Using Authenticated Encryption and Session Keys. Circuits Syst. Signal Process. 32(6): 2605-2622 (2013) - [j7]Shirshendu Das, Parasara Sridhar Duggirala, Hemangee K. Kapoor:
A formal framework for interfacing mixed-timing systems. Integr. 46(3): 255-264 (2013) - [j6]Lalit Chandnani, Hemangee K. Kapoor:
Formal Approach for DVS-Based Power Management for Multiple Server System in Presence of Server Failure and Repair. IEEE Trans. Ind. Informatics 9(1): 502-513 (2013) - [j5]Hemangee K. Kapoor, Praveen Kanakala, Malti Verma, Shirshendu Das:
Design and formal verification of a hierarchical cache coherence protocol for NoC based multiprocessors. J. Supercomput. 65(2): 771-796 (2013) - [c11]Prateek D. Halwe, Shirshendu Das, Hemangee K. Kapoor:
Towards a Better Cache Utilization Using Controlled Cache Partitioning. DASC 2013: 179-186 - [c10]Shirshendu Das, Hemangee K. Kapoor:
Dynamic Associativity Management Using Fellow Sets. ISED 2013: 133-137 - [c9]Shirshendu Das, Nagaraju Polavarapu, Prateek D. Halwe, Hemangee K. Kapoor:
Random-LRU: A Replacement Policy for Chip Multiprocessors. VDAT 2013: 204-213 - 2011
- [c8]K. Sajeesh, Hemangee K. Kapoor:
An Authenticated Encryption Based Security Framework for NoC Architectures. ISED 2011: 134-139 - 2010
- [c7]Khan Ajoy, Kushagra Misra, Santosh Biswas, Jatindra Kumar Deka, Hemangee K. Kapoor:
Fair diagnosability in PN-based DES models. ICCA 2010: 2166-2171 - [c6]Alpesh Patel, Hemangee K. Kapoor:
Exploring Use of NoC for Reconfigurable Video Coding. VLSI Design 2010: 134-139
2000 – 2009
- 2009
- [j4]Hemangee K. Kapoor:
A Process Algebraic View of Latency-Insensitive Systems. IEEE Trans. Computers 58(7): 931-944 (2009) - 2007
- [j3]Mark B. Josephs, Hemangee K. Kapoor:
Controllable Delay-Insensitive Processes. Fundam. Informaticae 78(1): 101-130 (2007) - [c5]Hemangee K. Kapoor:
Modelling Latency-Insensitive Systems in CSP. ACSD 2007: 231-232 - 2006
- [j2]Hemangee K. Kapoor, Mark B. Josephs, Dennis P. Furey:
Verification and Implementation of Delay-Insensitive Processes in Restrictive Environments. Fundam. Informaticae 70(1-2): 21-48 (2006) - [c4]Hemangee K. Kapoor:
Formal Modelling and Verification of an Asynchronous DLX Pipeline. SEFM 2006: 118-127 - 2005
- [c3]Hemangee K. Kapoor, Mark B. Josephs:
Controllable Delay-Insensitive Processes and their Reflection, Interaction and Factorisation. ACSD 2005: 58-67 - 2004
- [j1]Hemangee K. Kapoor, Mark B. Josephs:
Modelling and verification of delay-insensitive circuits using CCS and the Concurrency Workbench. Inf. Process. Lett. 89(6): 293-296 (2004) - [c2]Hemangee K. Kapoor, Mark B. Josephs, Dennis P. Furey:
Verification and Implementation of Delay-Insensitive Processes in Restrictive Environments. ACSD 2004: 89-98 - [c1]Hemangee K. Kapoor, Mark B. Josephs:
Decomposing specifications with concurrent outputs to resolve state coding conflicts in asynchronous logic synthesis. DAC 2004: 830-833
Coauthor Index
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.
Unpaywalled article links
Add open access links from 
to the list of external document links (if available).
Privacy notice: By enabling the option above, your browser will contact the API of unpaywall.org to load hyperlinks to open access articles. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the Unpaywall privacy policy.
Archived links via Wayback Machine
For web page which are no longer available, try to retrieve content from the 
of the Internet Archive (if available).
Privacy notice: By enabling the option above, your browser will contact the API of archive.org to check for archived content of web pages that are no longer available. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the Internet Archive privacy policy.
Reference lists
Add a list of references from 
, 
, and 
to record detail pages.
load references from crossref.org and opencitations.net
Privacy notice: By enabling the option above, your browser will contact the APIs of crossref.org, opencitations.net, and semanticscholar.org to load article reference information. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the Crossref privacy policy and the OpenCitations privacy policy, as well as the AI2 Privacy Policy covering Semantic Scholar.
Citation data
Add a list of citing articles from and to record detail pages.
load citations from opencitations.net
Privacy notice: By enabling the option above, your browser will contact the API of opencitations.net and semanticscholar.org to load citation information. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the OpenCitations privacy policy as well as the AI2 Privacy Policy covering Semantic Scholar.
OpenAlex data
Load additional information about publications from 
.
Privacy notice: By enabling the option above, your browser will contact the API of openalex.org to load additional information. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the information given by OpenAlex.
last updated on 2024-12-23 19:30 CET by the dblp team
all metadata released as open data under CC0 1.0 license
see also: Terms of Use | Privacy Policy | Imprint
dblp was originally created in 1993 at:
since 2018, dblp has been operated and maintained by:
the dblp computer science bibliography is funded and supported by:
