CoSeP: Compression and Content-based Selection Procedure to Improve Lifetime of Encrypted Non-Volatile Main Memories
Pages 393 - 396
Abstract
In this paper, we propose a technique called CoSeP that combines the effect of compression and the content of the compressed blocks to reduce bit-flips in the encrypted PCM-based main memories. The blocks are compressed using the technique (out of FPC, BDI, and COMF) that offers minimum block size when the sizes of the two smallest compressed blocks are non-similar. However, for compressed blocks of similar sizes, the block is compressed using the technique that encounters minimum bit-flips, which reduces bit-flips further. Experimental results show that our technique gives a substantial reduction in bit-flips and improvements in lifetime compared to baseline and state-of-the-art techniques.
Supplementary Material
The emerging non-volatile memories need to be secured using encryption to protect their sensitive data contents against data stealing. However, encryption techniques, owing to their diffusion property introduce high randomization in the generated ciphertext, which leads to a spike in bit-flips when the encrypted data are written in the memory. Our technique CoSeP intelligently combines existing compression techniques FPC, BDI, and COMF to compress the data blocks before encryption. Compressed blocks reduce exposure to the NVM cells while writing and improve energy consumption and lifetime of non-volatile memories.
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References
[1]
Alaa Alameldeen and David Wood. 2004. Frequent pattern compression: A significance-based compression scheme for L2 caches. Technical Report. University of Wisconsin-Madison Department of Computer Sciences.
[2]
Amro Awad et al. 2016. Silent shredder: Zero-cost shredding for secure nonvolatile main memory controllers. ACM SIGPLAN Notices 51, 4 (2016), 263--276.
[3]
C Bienia et al. 2008. The PARSEC benchmark suite: Characterization and architectural implications. In PACT. 72--81.
[4]
Nathan Binkert et al. 2011. The gem5 simulator. ACM SIGARCH Computer Architecture News 39, 2 (2011), 1--7.
[5]
S Cho et al. 2009. Flip-N-Write: A simple deterministic technique to improve PRAM write performance, energy and endurance. In IEEE/ACM MICRO. 347--357.
[6]
Dan Feng et al. 2020. A Low-Overhead Encoding Scheme to Extend the Lifetime of Nonvolatile Memories. IEEE TCAD 39, 10 (2020), 2516--2529.
[7]
John L Henning. 2006. SPEC CPU2006 benchmark descriptions. ACM SIGARCH Computer Architecture News 34, 4 (2006), 1--17.
[8]
Majid Jalili and Hamid Sarbazi-Azad. 2016. Endurance-aware security enhancement in non-volatile memories using compression and selective encryption. IEEE Trans. Comput. 66, 7 (2016), 1132--1144.
[9]
Lei Jiang et al. 2012. Improving write operations in MLC phase change memory. In IEEE HPCA. 1--10. https://doi.org/10.1109/HPCA.2012.6169027
[10]
M K. Qureshi et al. 2009. Enhancing lifetime and security of PCM-based Main Memory with Start-Gap Wear Leveling. In MICRO. 14--23.
[11]
E. KÃ"ltÃ?rsay, M. Kandemir, A. Sivasubramaniam, and O. Mutlu. 2013. Evaluating STT-RAM as an energy-efficient main memory alternative. In 2013 IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS). 256--267.
[12]
Benjamin C Lee et al. 2009. Architecting phase change memory as a scalable dram alternative. In ISCA. 2--13.
[13]
Chen Liu and Chengmo Yang. 2015. Secure and Durable (SEDURA) An Integrated Encryption and Wear-leveling Framework for PCM-based Main Memory. ACM Sigplan Notices 50, 5 (2015), 1--10.
[14]
Arijit Nath and Hemangee K. Kapoor. 2020. WELCOMF: Wear Leveling Assisted Compression Using Frequent Words in Non-Volatile Main Memories. In ACM/IEEE ISLPED (Boston, Massachusetts) (ISLPED '20). Association for Computing Machinery, New York, NY, USA, 157--162.
[15]
Poovaiah M Palangappa and Kartik Mohanram. 2018. CASTLE: Compression architecture for secure low latency, low energy, high endurance NVMs. In 2018 55th ACM/ESDA/IEEE DAC. IEEE, 1--6.
[16]
Gennady Pekhimenko et al. 2012. Base-delta-immediate compression: Practical data compression for on-chip caches. In 2012 PACT. IEEE, 377--388.
[17]
Matt Poremba et al. 2012. NVMain: An architectural-level main memory simulator for emerging non-volatile memories. In ISVLSI. IEEE, 392--397.
[18]
Shivam Swami, Joydeep Rakshit, and Kartik Mohanram. 2016. SECRET: Smartly encrypted energy efficient non-volatile memories. In DAC. 1--6.
[19]
Jue Wang et al., Xiangyu Dong, Yuan Xie, and Norman P Jouppi. 2013. i 2 WAP: Improving non-volatile cache lifetime by reducing inter-and intra-set write variations. In IEEE HPCA. IEEE, 234--245.
[20]
B Yang et al. 2007. A Low Power Phase-Change Random Access Memory using a Data-Comparison Write Scheme. In 2007 IEEE International Symposium on Circuits and Systems. 3014--3017.
[21]
Vinson Young, Prashant J Nair, and Moinuddin K Qureshi. 2015. DEUCE: Write efficient encryption for non-volatile memories. ACM SIGARCH Computer Architecture News 43, 1 (2015), 33--44.
[22]
Pengfei Zuo et al. 2018. Improving the performance and endurance of encrypted non-volatile main memory through deduplicating writes. In IEEE/ACM MICRO. IEEE, 442--454.
Index Terms
- CoSeP: Compression and Content-based Selection Procedure to Improve Lifetime of Encrypted Non-Volatile Main Memories
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Published In
June 2022
560 pages
ISBN:9781450393225
DOI:10.1145/3526241
- General Chairs:
- Ioannis Savidis,
- Avesta Sasan,
- Program Chairs:
- Himanshu Thapliyal,
- Ronald F. DeMara
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Published: 06 June 2022
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