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Harry Muljono
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2010 – 2019
- 2019
- [c8]Harry Muljono, Kathy Peng, Linda Sun, Isaac Abraham, Charlie Lin, Yanjie Zhu, Chunrong Song:
A 2.666GT/s 128GB/s 14nm Memory I/O with Jitter and Crosstalk Cancellation. A-SSCC 2019: 21-24 - 2018
- [c7]Horaira Abu, Salem Abdennadher, Benoit Provost, Harry Muljono:
Augmenting ESD and EOS physical analysis with per pin ESD and leakage DFT. ISQED 2018: 20-24 - [c6]Simon M. Tam, Harry Muljono, Min Huang, Sitaraman Iyer, Kalapi Royneogi, Nagmohan Satti, Rizwan Qureshi, Wei Chen, Tom Wang, Hubert Hsieh, Sujal Vora, Eddie Wang:
SkyLake-SP: A 14nm 28-Core xeon® processor. ISSCC 2018: 34-36 - 2015
- [j7]Stefan Rusu, Harry Muljono, David Ayers, Simon M. Tam, Wei Chen, Aaron Martin, Shenggao Li
, Sujal Vora, Raj Varada, Eddie Wang:
A 22 nm 15-Core Enterprise Xeon® Processor Family. IEEE J. Solid State Circuits 50(1): 35-48 (2015) - 2014
- [c5]Stefan Rusu, Harry Muljono, David Ayers, Simon M. Tam, Wei Chen, Aaron Martin, Shenggao Li
, Sujal Vora, Raj Varada, Eddie Wang:
5.4 Ivytown: A 22nm 15-core enterprise Xeon® processor family. ISSCC 2014: 102-103 - 2010
- [j6]Stefan Rusu, Simon M. Tam, Harry Muljono, Jason Stinson, David Ayers, Jonathan Chang, Raj Varada, Matt Ratta, Sailesh Kottapalli, Sujal Vora:
A 45 nm 8-Core Enterprise Xeon¯ Processor. IEEE J. Solid State Circuits 45(1): 7-14 (2010)
2000 – 2009
- 2009
- [c4]Stefan Rusu, Simon M. Tam, Harry Muljono, Jason Stinson, David Ayers, Jonathan Chang, Raj Varada, Matt Ratta, Sailesh Kottapalli, Sujal Vora:
Power reduction techniques for an 8-core xeon® processor. ESSCIRC 2009: 340-343 - [c3]Stefan Rusu, Simon M. Tam, Harry Muljono, Jason Stinson, David Ayers, Jonathan Chang, Raj Varada, Matt Ratta, Sailesh Kottapalli:
A 45nm 8-core enterprise Xeon® processor. ISSCC 2009: 56-57 - 2007
- [j5]Stefan Rusu, Simon M. Tam, Harry Muljono, David Ayers, Jonathan Chang, Brian S. Cherkauer, Jason Stinson, John Benoit, Raj Varada, Justin Leung, Rahul Dilip Limaye, Sujal Vora:
A 65-nm Dual-Core Multithreaded Xeon® Processor With 16-MB L3 Cache. IEEE J. Solid State Circuits 42(1): 17-25 (2007) - 2006
- [c2]Stefan Rusu, Simon M. Tam, Harry Muljono, David Ayers, Jonathan Chang:
A Dual-Core Multi-Threaded Xeon Processor with 16MB L3 Cache. ISSCC 2006: 315-324 - 2004
- [j4]Stefan Rusu, Harry Muljono, Brian S. Cherkauer:
Itanium 2 Processor 6M: Higher Frequency and Larger L3 Cache. IEEE Micro 24(2): 10-18 (2004) - [c1]Benoit Provost, Chee How Lim, Mo Bashir, Ali Muhtaroglu, Tiffany Huang, Kathy Tian, Mubeen Atha, Cangsang Zhao, Harry Muljono:
AC IO Loopback Design for High Speed µProcessor IO Test. ITC 2004: 23-30 - 2003
- [j3]Harry Muljono, Beom-Taek Lee, Yanmei (Kathy) Tian, Yanbin (Eddie) Wang, Mubeen Atha, Tiffany Huang, Mitsuhiro Adachi, Stefan Rusu:
A 400-MT/s 6.4-GB/s multiprocessor bus interface. IEEE J. Solid State Circuits 38(11): 1846-1856 (2003) - [j2]Stefan Rusu, Jason Stinson, Simon Tam, Justin Leung, Harry Muljono, Brian S. Cherkauer:
A 1.5-GHz 130-nm Itanium® 2 Processor with 6-MB on-die L3 cache. IEEE J. Solid State Circuits 38(11): 1887-1895 (2003) - 2001
- [j1]Alper Ilkbahar, Srinivas Venkataraman, Harry Muljono:
ItaniumTM Processor system bus design. IEEE J. Solid State Circuits 36(10): 1565-1573 (2001)
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