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ORCIDGeorge Michelogiannakis
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2020 – today
- 2024
[j12]Patricia Gonzalez-Guerrero
, Kylie Huch, Nirmalendu Patra, Doru-Thom Popovici, George Michelogiannakis:
Toward Practical Superconducting Accelerators for Machine Learning Using U-SFQ. ACM J. Emerg. Technol. Comput. Syst. 20(2): 7:1-7:22 (2024)- [j11]Meriam Gay Bautista, Darren Lyles, Kylie Huch, Patricia Gonzalez-Guerrero, George Michelogiannakis:
Area Efficient Asynchronous SFQ Pulse Round-Robin Distribution Network. IEEE Trans. Circuits Syst. I Regul. Pap. 71(1): 201-208 (2024) - [c42]Jie Li, George Michelogiannakis, Samuel Maloney, Brandon Cook, Estela Suarez, John Shalf, Yong Chen:
Job Scheduling in High Performance Computing Systems with Disaggregated Memory Resources. CLUSTER 2024: 297-309 - [c41]Jie Li, George Michelogiannakis, Brandon Cook, John Shalf, Yong Chen:
Scheduling and Allocation of Disaggregated Memory Resources in HPC Systems. IPDPS (Workshops) 2024: 1202-1203 - 2023
- [j10]Meriam Gay Bautista, Patricia Gonzalez-Guerrero, Darren Lyles, George Michelogiannakis:
Superconducting Shuttle-Flux Shift Register for Race Logic and Its Applications. IEEE Trans. Circuits Syst. I Regul. Pap. 70(1): 17-28 (2023) - [c40]George Michelogiannakis, Yehia Arafa, Brandon Cook, Liang Yuan Dai, Abdel-Hameed A. Badawy, Madeleine Glick, Yuyang Wang, Keren Bergman, John Shalf:
Efficient Intra-Rack Resource Disaggregation for HPC Using Co-Packaged DWDM Photonics. CLUSTER 2023: 158-172 - [c39]Hamza Errahmouni Barkam, Sanggeon Yun, Hanning Chen, Paul Gensler, Albi Mema, Andrew Ding, George Michelogiannakis, Hussam Amrouch, Mohsen Imani:
Reliable Hyperdimensional Reasoning on Unreliable Emerging Technologies. ICCAD 2023: 1-9 - [c38]Patricia Gonzalez-Guerrero, Kylie Huch, Nirmalendu Patra, Doru-Thom Popovici, George Michelogiannakis:
An Area Efficient Superconducting Unary CNN Accelerator. ISQED 2023: 1-8 - [c37]Andrew M. Bartolo, Mohamed M. Sabry Aly, George Michelogiannakis, Subhasish Mitra:
MC-ELMM: Multi-Chip Endurance-Limited Memory Management. MEMSYS 2023: 23:1-23:16 - [c36]Jie Li, George Michelogiannakis, Brandon Cook, Dulanya Cooray, Yong Chen:
Analyzing Resource Utilization in an HPC System: A Case Study of NERSC's Perlmutter. ISC 2023: 297-316 - [i4]George Michelogiannakis, Yehia Arafa, Brandon Cook, Liang Yuan Dai, Abdel-Hameed A. Badawy, Madeleine Glick, Yuyang Wang, Keren Bergman, John Shalf:
Efficient Intra-Rack Resource Disaggregation for HPC Using Co-Packaged DWDM Photonics. CoRR abs/2301.03592 (2023) - [i3]Jie Li, George Michelogiannakis, Brandon Cook, Dulanya Cooray, Yong Chen:
Analyzing Resource Utilization in an HPC System: A Case Study of NERSC Perlmutter. CoRR abs/2301.05145 (2023) - 2022
- [j9]George Michelogiannakis, Benjamin Klenk, Brandon Cook, Min Yee Teh, Madeleine Glick, Larry Dennison, Keren Bergman, John Shalf:
A Case For Intra-rack Resource Disaggregation in HPC. ACM Trans. Archit. Code Optim. 19(2): 29:1-29:26 (2022) - [c35]Patricia Gonzalez-Guerrero, Meriam Gay Bautista, Darren Lyles, George Michelogiannakis:
Temporal and SFQ pulse-streams encoding for area-efficient superconducting accelerators. ASPLOS 2022: 963-976 - [c34]Meriam Gay Bautista, Patricia Gonzalez-Guerrero, Darren Lyles, Kylie Huch, George Michelogiannakis:
Superconducting Digital DIT Butterfly Unit for Fast Fourier Transform Using Race Logic. NEWCAS 2022: 441-445 - [c33]Alvin Oliver Glova, Yukai Yang, Yiyao Wan, Zhizhou Zhang, George Michelogiannakis, Jonathan Balkind, Timothy Sherwood:
Establishing Cooperative Computation with Hardware Embassies. SEED 2022: 85-96 - [i2]Darren Lyles, Patricia Gonzalez-Guerrero, Meriam Gay Bautista, George Michelogiannakis:
PaST-NoC: A Packet-Switched Superconducting Temporal NoC. CoRR abs/2210.09484 (2022) - 2021
- [j8]Georgios Tzimpragos, Jennifer Volk, Dilip Vasudevan, Nestan Tsiskaridze, George Michelogiannakis, Advait Madhavan, John Shalf, Timothy Sherwood:
Temporal Computing With Superconductors. IEEE Micro 41(3): 71-79 (2021) - [c32]George Michelogiannakis, Darren Lyles, Patricia Gonzalez-Guerrero, Meriam Gay Bautista, Dilip Vasudevan, Anastasiia Butko:
SRNoC: A Statically-Scheduled Circuit-Switched Superconducting Race Logic NoC. IPDPS 2021: 1046-1055 - [c31]Meriam Gay Bautista, Patricia Gonzalez-Guerrero, Darren Lyles, George Michelogiannakis:
Superconducting Shuttle-flux Shift Buffer for Race Logic. MWSCAS 2021: 796-801 - 2020
- [j7]Weilong Cui, Georgios Tzimpragos, Yu Tao, Joseph McMahan, Deeksha Dangwal, Nestan Tsiskaridze, George Michelogiannakis, Dilip P. Vasudevan, Timothy Sherwood:
Language Support for Navigating Architecture Design in Closed Form. ACM J. Emerg. Technol. Comput. Syst. 16(1): 9:1-9:28 (2020) - [j6]Madeleine Glick, Nathan C. Abrams, Qixiang Cheng, Min Yee Teh, Yu-Han Hung, Oscar A. Jimenez, Songtao Liu, Yoshitomo Okawachi, Xiang Meng, Leif Johansson, Manya Ghobadi, Larry Dennison, George Michelogiannakis, John Shalf, Alan Y. Liu, John E. Bowers, Alexander L. Gaeta, Michal Lipson, Keren Bergman:
PINE: Photonic Integrated Networked Energy efficient datacenters (ENLITENED Program) [Invited]. JOCN 12(12): 443-456 (2020) - [c30]Georgios Tzimpragos, Dilip Vasudevan, Nestan Tsiskaridze, George Michelogiannakis, Advait Madhavan, Jennifer Volk, John Shalf, Timothy Sherwood:
A Computational Temporal Logic for Superconducting Accelerators. ASPLOS 2020: 435-448 - [c29]Anastasiia Butko, George Michelogiannakis, Samuel Williams, Costin Iancu, David Donofrio, John Shalf, Jonathan Carter, Irfan Siddiqi:
Understanding Quantum Control Processor Capabilities and Limitations through Circuit Characterization. ICRC 2020: 66-75 - [c28]Min Yee Teh, Yu-Han Hung, George Michelogiannakis, Shijia Yan, Madeleine Glick, John Shalf, Keren Bergman:
TAGO: rethinking routing design in high performance reconfigurable networks. SC 2020: 25 - [i1]Anastasiia Butko, Ilyas Turimbetov, George Michelogiannakis, David Donofrio, Didem Unat, John Shalf:
TIGER: Topology-aware Assignment using Ising machines Application to Classical Algorithm Tasks and Quantum Circuit Gates. CoRR abs/2009.10151 (2020)
2010 – 2019
- 2019
- [c27]Anastasiia Butko, George Michelogiannakis, David Donofrio, John Shalf:
TIGER: topology-aware task assignment approach using ising machines. CF 2019: 106-114 - [c26]Anastasiia Butko, George Michelogiannakis, David Donofrio, John Shalf:
Extending classical processors to support future large scale quantum accelerators. CF 2019: 317 - [c25]Pooria M. Yaghini, George Michelogiannakis, Paul V. Gratz:
SpecLock: Speculative Lock Forwarding. ICCD 2019: 273-282 - [c24]Dilip P. Vasudevan, George Michelogiannakis, David Donofrio, John Shalf:
PARADISE - Post-Moore Architecture and Accelerator Design Space Exploration Using Device Level Simulation and Experiments. ISPASS 2019: 139-140 - [c23]Sebastian Werner, Pouya Fotouhi, Xian Xiao, Marjan Fariborz, S. J. Ben Yoo, George Michelogiannakis, Dilip P. Vasudevan:
3D photonics as enabling technology for deep 3D DRAM stacking. MEMSYS 2019: 206-221 - [c22]George Michelogiannakis, Yiwen Shen, Min Yee Teh, Xiang Meng, Benjamin Aivazi, Taylor L. Groves, John Shalf, Madeleine Glick, Manya Ghobadi, Larry Dennison, Keren Bergman:
Bandwidth steering in HPC using silicon nanophotonics. SC 2019: 41:1-41:25 - 2018
- [c21]George Michelogiannakis, Benjamin Aivazi, Yiwen Shen, Larry Dennison, John Shalf, Keren Bergman, Madeleine Glick:
Architectural Opportunities and Challenges from Emerging Photonics in Future Systems. PSC 2018: 1-3 - [c20]Joseph P. Kenny, Khachik Sargsyan, Samuel Knight, George Michelogiannakis, Jeremiah J. Wilke:
The Pitfalls of Provisioning Exascale Networks: A Trace Replay Analysis for Understanding Communication Performance. ISC 2018: 269-288 - 2017
- [c19]George Michelogiannakis, Khaled Z. Ibrahim, John Shalf, Jeremiah J. Wilke, Samuel Knight, Joseph P. Kenny:
APHiD: Hierarchical Task Placement to Enable a Tapered Fat Tree Topology for Lower Power and Cost in HPC Networks. CCGrid 2017: 228-237 - [c18]George Michelogiannakis, John Shalf:
Last Level Collective Hardware Prefetching For Data-Parallel Applications. HiPC 2017: 72-83 - [c17]Dilip P. Vasudevan, George Michelogiannakis, David Donofrio, John Shalf:
CASPER - Configurable design space exploration of programmable architectures for machine learning using beyond moore devices. NANOARCH 2017: 117-118 - [c16]Dilip P. Vasudevan, Anastasiia Butko, George Michelogiannakis, David Donofrio, John Shalf:
Towards an Integrated Strategy to Preserve Digital Computing Performance Scaling Using Emerging Technologies. ISC Workshops 2017: 115-123 - 2016
- [c15]Farzad Fatollahi-Fard, David Donofrio, George Michelogiannakis, John Shalf:
OpenSoC Fabric: On-chip network generator. ISPASS 2016: 194-203 - [c14]Didem Unat, Tan Nguyen, Weiqun Zhang, Muhammed Nufail Farooqi, Burak Bastem, George Michelogiannakis, Ann S. Almgren, John Shalf:
TiDA: High-Level Programming Abstractions for Data Locality Management. ISC 2016: 116-135 - 2015
- [j5]George Michelogiannakis, Xiaoye S. Li, David H. Bailey, John Shalf:
Extending Summation Precision for Network Reduction Operations. Int. J. Parallel Program. 43(6): 1218-1243 (2015) - 2014
- [c13]George Michelogiannakis, Alexander Williams, Samuel Williams, John Shalf:
Collective memory transfers for multi-core chips. ICS 2014: 343-352 - [c12]Farzad Fatollahi-Fard, David Donofrio, George Michelogiannakis, John Shalf:
OpenSoC Fabric: On-Chip Network Generator: Using Chisel to Generate a Parameterizable On-Chip Interconnect Fabric. NoCArc@MICRO 2014: 45-50 - [c11]George Michelogiannakis, John Shalf:
Variable-width datapath for on-chip network static power reduction. NOCS 2014: 96-103 - 2013
- [j4]George Michelogiannakis, William J. Dally:
Elastic Buffer Flow Control for On-Chip Networks. IEEE Trans. Computers 62(2): 295-309 (2013) - [c10]Nan Jiang, Daniel U. Becker, George Michelogiannakis, James D. Balfour, Brian Towles, David E. Shaw, John Kim, William J. Dally:
A detailed and flexible cycle-accurate Network-on-Chip simulator. ISPASS 2013: 86-96 - [c9]George Michelogiannakis, Xiaoye S. Li, David H. Bailey, John Shalf:
Extending Summation Precision for Network Reduction Operations. SBAC-PAD 2013: 41-48 - [c8]George Michelogiannakis, Nan Jiang, Daniel Becker, William J. Dally:
Channel reservation protocol for over-subscribed channels and destinations. SC 2013: 52:1-52:12 - 2012
- [c7]Nan Jiang, Daniel U. Becker, George Michelogiannakis, William J. Dally:
Network congestion avoidance through Speculative Reservation. HPCA 2012: 443-454 - [c6]Daniel U. Becker, Nan Jiang, George Michelogiannakis, William J. Dally:
Adaptive Backpressure: Efficient buffer management for on-chip networks. ICCD 2012: 419-426 - 2011
- [j3]George Michelogiannakis, Nan Jiang, Daniel Becker, William J. Dally:
Packet Chaining: Efficient Single-Cycle Allocation for On-Chip Networks. IEEE Comput. Archit. Lett. 10(2): 33-36 (2011) - [j2]George Michelogiannakis, Daniel Becker, William J. Dally:
Evaluating Elastic Buffer and Wormhole Flow Control. IEEE Trans. Computers 60(6): 896-903 (2011) - [c5]George Michelogiannakis, Nan Jiang, Daniel Becker, William J. Dally:
Packet chaining: efficient single-cycle allocation for on-chip networks. MICRO 2011: 83-94 - 2010
- [j1]Daniel Sánchez, George Michelogiannakis, Christos Kozyrakis:
An analysis of on-chip interconnection networks for large-scale chip multiprocessors. ACM Trans. Archit. Code Optim. 7(1): 4:1-4:28 (2010) - [c4]George Michelogiannakis, Daniel Sánchez, William J. Dally, Christos Kozyrakis:
Evaluating Bufferless Flow Control for On-chip Networks. NOCS 2010: 9-16
2000 – 2009
- 2009
- [c3]George Michelogiannakis, James D. Balfour, William J. Dally:
Elastic-buffer flow control for on-chip networks. HPCA 2009: 151-162 - [c2]George Michelogiannakis, William J. Dally:
Router designs for elastic buffer on-chip networks. SC 2009 - 2007
- [c1]George Michelogiannakis, Dionisios N. Pnevmatikatos, Manolis Katevenis:
Approaching Ideal NoC Latency with Pre-Configured Routes. NOCS 2007: 153-162
Coauthor Index
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