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ORCIDPrem R. Menon
Person information
- affiliation: University of Massachusetts, Department of Electrical and Computer Engineering, Amherst, MA, USA
- affiliation (1963): University of Washington, Seattle, WA, USA
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2000 – 2009
- 2006
[j32]Premachandran R. Menon, Weifeng Xu, Russell Tessier:
Design-specific path delay testing in lookup-table-based FPGAs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(5): 867-877 (2006)- 2001
- [j31]Ramesh C. Tekumalla, Premachandran R. Menon:
Identification of primitive faults in combinational and sequentialcircuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 20(12): 1426-1442 (2001) - [c32]Ian G. Harris, Premachandran R. Menon, Russell Tessier:
BIST-based delay path testing in FPGA architectures. ITC 2001: 932-938 - 2000
- [j30]Ramesh C. Tekumalla, Premachandran R. Menon:
On Redundant Path Delay Faults in Synchronous Sequential Circuits. IEEE Trans. Computers 49(3): 277-282 (2000)
1990 – 1999
- 1999
- [c31]Ramesh C. Tekumalla, Premachandran R. Menon:
Robust testability of primitive faults using test points. ITC 1999: 260-268 - 1998
- [c30]Ramesh C. Tekumalla, Premachandran R. Menon:
On primitive fault test generation in non-scan sequential circuits. ICCAD 1998: 275-282 - 1997
- [j29]Wolfgang Kunz, Dominik Stoffel, Prem R. Menon:
Logic optimization and equivalence checking by implication analysis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 16(3): 266-281 (1997) - [c29]Miron Abramovici, Prem R. Menon:
Fault simulation on reconfigurable hardware. FCCM 1997: 182-191 - [c28]Ramesh C. Tekumalla, Premachandran R. Menon:
Test generation for primitive path delay faults in combinational circuits. ICCAD 1997: 636-641 - [c27]Ramesh C. Tekumalla, Premachandran R. Menon:
Synthesis of Delay Verifiable Sequential Circuits using Partial Enhanced Scan. ICCD 1997: 648-653 - [c26]Ramesh C. Tekumalla, Premachandran R. Menon:
Delay Testing with Clock Control: An Alternative to Enhanced Scan. ITC 1997: 454-462 - 1996
- [c25]Ramesh C. Tekumalla, Premachandran R. Menon:
Identifying Redundant Path Delay Faults in Sequential Circuits. VLSI Design 1996: 406-411 - 1995
- [j28]Wuudiann Ke, Premachandran R. Menon:
Multifault and delay-fault testability of multilevel circuits. J. Electron. Test. 6(3): 333-336 (1995) - [j27]Wuudiann Ke, Premachandran R. Menon:
Synthesis of Delay-Verifiable Combinational Circuits. IEEE Trans. Computers 44(2): 213-222 (1995) - [j26]Wuudiann Ke, Premachandran R. Menon:
Path-delay-fault testable nonscan sequential circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 14(5): 576-582 (1995) - [j25]Wuudiann Ke, Premachandran R. Menon:
Delay-testable implementations of symmetric functions. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 14(6): 772-775 (1995) - [c24]Wuudiann Ke, Premachandran R. Menon:
Multifault testability of delay-testable circuits. VTS 1995: 400-409 - 1994
- [j24]Prem R. Menon, Hitesh Ahuja, Mohan Harihara:
Redundancy identification and removal in combinational circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 13(5): 646-651 (1994) - [c23]Hitesh Ajuha, Premachandran R. Menon:
Delay Reduction by Segment Substitution. EDAC-ETC-EUROASIC 1994: 82-86 - [c22]Wuudiann Ke, Premachandran R. Menon:
Synthesis of Delay-Verifiable Two-Level Circuits. EDAC-ETC-EUROASIC 1994: 297-301 - [c21]Wolfgang Kunz, Prem R. Menon:
Multi-level logic optimization by implication analysis. ICCAD 1994: 6-13 - [c20]Wuudiann Ke, Premachandran R. Menon:
Delay-Verifiability of Combinational Circuits Based on Primitive Faults. ICCD 1994: 86-90 - [c19]Wuudiann Ke, Premachandran R. Menon:
Realization of fully path-delay-fault testable non-scan sequential circuits. VTS 1994: 278-283 - 1993
- [j23]O. Y. Song, Bong-Hee Park, Prem R. Menon:
Divergence and scheduling in functional level concurrent fault simulation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 12(5): 734-736 (1993) - [j22]Ohyoung Song, Premachandran R. Menon:
Acceleration of trace-based fault simulation of combinational circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 12(9): 1413-1419 (1993) - [j21]Ohyoung Song, Premachandran R. Menon:
3-valued trace-based fault simulation of synchronous sequential circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 12(9): 1419-1424 (1993) - 1992
- [c18]Prem R. Menon, Hitesh Ahuja:
Redundancy removal and simplification of combinational circuits. VTS 1992: 268-273 - 1991
- [j20]Premachandran R. Menon, Ytzhak H. Levendel, Miron Abramovici:
SCRIPT: a critical path tracing algorithm for synchronous sequential circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 10(6): 738-747 (1991) - [c17]Bong-Hee Park, Premachandran R. Menon:
Robustly Scan-Testable CMOS Sequential Circuits. ITC 1991: 263-272 - 1990
- [c16]Bong-Hee Park, Premachandran R. Menon:
Design of scan-testable CMOS sequential circuits. ITC 1990: 369-376 - [c15]Ohyoung Song, Premachandran R. Menon:
Parallel pattern fault simulation based on stem faults in combinational circuits. ITC 1990: 706-711
1980 – 1989
- 1989
- [c14]Mohan Harihara, Prem R. Menon:
Identification of undetectable faults in combinational circuits. ICCD 1989: 290-293 - [c13]Miron Abramovici, James J. Kulikowski, David T. Miller, Prem R. Menon:
System-level design verification in the AT&T Computer Division: tools. ICCD 1989: 548-554 - [c12]C. H. Chen, Premachandran R. Menon:
An Approach to Functional Level Testability Analysis. ITC 1989: 373-380 - [c11]P. N. Anirudhan, Premachandran R. Menon:
Symbolic Test Generation for Hierarchically Modeled Digital Systems. ITC 1989: 461-469 - 1988
- [c10]Prem R. Menon, Ytzhak H. Levendel, Miron Abramovici:
Critical path tracing in sequential circuits. ICCAD 1988: 162-165 - 1986
- [j19]Miron Abramovici, James J. Kulikowski, Premachandran R. Menon, David T. Miller:
SMART and FAST: Test Generation for VLSI Scan-Design Circuits. IEEE Des. Test 3(4): 43-54 (1986) - [j18]Miron Abramovici, Prem R. Menon, David T. Miller:
Checkpoint Faults are not Sufficient Target Faults for Test Generation. IEEE Trans. Computers 35(8): 769-771 (1986) - 1985
- [j17]Miron Abramovici, Prem R. Menon:
A Practical Approach to Fault Simulation and Test Generation for Bridging Faults. IEEE Trans. Computers 34(7): 658-663 (1985) - [c9]Miron Abramovici, James J. Kulikowski, Premachandran R. Menon, David T. Miller:
Test Generation In Lamp2: System Overview. ITC 1985: 45-48 - [c8]Miron Abramovici, James J. Kulikowski, Premachandran R. Menon, David T. Miller:
Test Generation In Lamp2: Concepts and Algorithms. ITC 1985: 49-56 - 1984
- [j16]Miron Abramovici, Prem R. Menon, David T. Miller:
Critical Path Tracing: An Alternative to Fault Simulation. IEEE Des. Test 1(1): 83-93 (1984) - 1983
- [j15]Ytzhak H. Levendel, Prem R. Menon, Suresh H. Patel:
Parallel fault simulation using distributed processing. Bell Syst. Tech. J. 62(10): 3107-3137 (1983) - [j14]Gordon K. Lin, Premachandran R. Menon:
Totally Preset Checking Experiments for Sequential Machines. IEEE Trans. Computers 32(2): 101-108 (1983) - [j13]Miron Abramovici, Ytzhak H. Levendel, Premachandran R. Menon:
A Logic Simulation Machine. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2(2): 82-94 (1983) - [c7]Miron Abramovici, Prem R. Menon, David T. Miller:
Critical path tracing - an alternative to fault simulation. DAC 1983: 214-220 - [c6]Miron Abramovici, Premachandran R. Menon:
A Practical Approach to Fault Simulation and Test Generation for Bridging Faults. ITC 1983: 138-142 - 1982
- [j12]Ytzhak H. Levendel, Premachandran R. Menon:
Test Generation Algorithms for Computer Hardware Description Languages. IEEE Trans. Computers 31(7): 577-588 (1982) - [c5]Miron Abramovici, Ytzhak H. Levendel, Prem R. Menon:
A logic simulation machine. DAC 1982: 65-73 - [c4]Miron Abramovici, Ytzhak H. Levendel, Prem R. Menon:
A logic simulation machine. ISCA 1982: 148-157
1970 – 1979
- 1978
- [j11]Premachandran R. Menon, Stephen G. Chappell:
Deductive Fault Simulation with Functional Blocks. IEEE Trans. Computers 27(8): 689-695 (1978) - 1976
- [c3]Stephen G. Chappell, Prem R. Menon, John F. Pellegrin, A. M. Schowe:
Functional simulation in the lamp system. DAC 1976: 42-47 - 1973
- [j10]Arthur D. Friedman, Premachandran R. Menon:
Restricted Checking Sequences for Sequential Machines. IEEE Trans. Computers 22(4): 397-399 (1973) - 1972
- [j9]Arthur D. Friedman, Prem R. Menon:
Comments on "Design of Diagnosable Iterative Arrays". IEEE Trans. Computers 21(5): 511 (1972) - 1971
- [j8]Arthur D. Friedman, Prem R. Menon:
Systems of Asynchronously Operating Modules. IEEE Trans. Computers 20(1): 100-104 (1971) - [j7]Premachandran R. Menon, Arthur D. Friedman:
Fault Detection in Iterative Logic Arrays. IEEE Trans. Computers 20(5): 524-535 (1971)
1960 – 1969
- 1969
- [j6]Premachandran R. Menon:
On Sequential Machine Decompositions for Reducing the Number of Delay Elements. Inf. Control. 15(3): 274-287 (1969) - [j5]Arthur D. Friedman, Prem R. Menon:
Design of Generalized Double Rank and Multiple Rank Sequential Circuits. Inf. Control. 15(5): 436-451 (1969) - [j4]Chung-Jen Tan, Premachandran R. Menon, Arthur D. Friedman:
Structural Simplification and Decomposition of Asynchronous Sequential Circuits. IEEE Trans. Computers 18(9): 830-838 (1969) - [j3]Douglas B. Armstrong, Arthur D. Friedman, Premachandran R. Menon:
Design of Asynchronous Circuits Assuming Unbounded Gate Delays. IEEE Trans. Computers 18(12): 1110-1120 (1969) - 1968
- [j2]Douglas B. Armstrong, Arthur D. Friedman, Premachandran R. Menon:
Realization of Asynchronous Sequential Circuits Without Inserted Delay Elements. IEEE Trans. Computers 17(2): 129-134 (1968) - [j1]Arthur D. Friedman, Prem R. Menon:
Synthesis of Asynchronous Sequential Circuits with Multiple-Input Changes. IEEE Trans. Computers 17(6): 559-566 (1968) - [c2]Chung-Jen Tan, Prem R. Menon, Arthur D. Friedman:
Structural Simplification and Decomposition of Asynchronous Sequential Circuits. SWAT 1968: 7-19 - 1967
- [c1]Douglas B. Armstrong, Arthur D. Friedman, Prem R. Menon:
Synthesis of Asynchronous Sequential Circuits with Minimum Number of Delay Elements. SWAT 1967: 95-105
Coauthor Index
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