default search action
Google
Google Scholar
Semantic Scholar
Internet Archive Scholar
CiteSeerX
ORCIDACM Transactions on Reconfigurable Technology and Systems, Volume 9
Volume 9, Number 1, November 2015
- Joonseok Park, Pedro C. Diniz
:
Program-Invariant Checking for Soft-Error Detection using Reconfigurable Hardware. 1:1-1:13 - Neil Scicluna, Christos-Savvas Bouganis:
ARC 2014: A Multidimensional FPGA-Based Parallel DBSCAN Architecture. 2:1-2:15 - Pascal Sasdrich, Tim Güneysu:
Implementing Curve25519 for Side-Channel-Protected Elliptic Curve Cryptography. 3:1-3:15 - Jianfeng Zhang, Paul Chow, Hengzhu Liu:
An Enhanced Adaptive Recoding Rotation CORDIC. 4:1-4:25
- Diana Goehringer, Marco D. Santambrogio, João M. P. Cardoso, Koen Bertels:
Guest Editorial ARC 2014. 5:1-5:2 - Karel Heyse, Jente Basteleus, Brahim Al Farisi, Dirk Stroobandt, Oliver Kadlcek, Oliver Pell:
On the Impact of Replacing Low-Speed Configuration Buses on FPGAs with the Chip's Internal Configuration Infrastructure. 6:1-6:18 - Rui Policarpo Duarte, Christos-Savvas Bouganis:
ARC 2014 Over-Clocking KLT Designs on FPGAs under Process, Voltage, and Temperature Variation. 7:1-7:17 - Yuhui Bai, Syed Zahid Ahmed, Bertrand Granado:
ARC 2014: Towards a Fast FPGA Implementation of a Heap-Based Priority Queue for Image Coding Using a Parallel Index-Aware Tree. 8:1-8:16
Volume 9, Number 2, February 2016
- Jianfeng Zhang, Paul Chow, Hengzhu Liu:
CORDIC-Based Enhanced Systolic Array Architecture for QR Decomposition. 9:1-9:22 - Felix J. Winterstein, Samuel R. Bayliss, George A. Constantinides:
Separation Logic for High-Level Synthesis. 10:1-10:23 - Hirak J. Kashyap, Ricardo Chaves:
Compact and On-the-Fly Secure Dynamic Reconfiguration for Volatile FPGAs. 11:1-11:22 - Jinwei Xu, Jingfei Jiang, Yong Dou, Xiaolong Shen, Zhiqiang Liu:
Coarse-Grained Architecture for Fingerprint Matching. 12:1-12:15
- Marco D. Santambrogio, Ramachandran Vaidyanathan:
Guest Editorial RAW 2014. 13:1-13:2 - Ali Mustafa Zaidi, David J. Greaves:
Value State Flow Graph: A Dataflow Compiler IR for Accelerating Control-Intensive Code in Spatial Hardware. 14:1-14:22 - Michael Raitza, Markus Vogt, Christian Hochberger, Thilo Pionteck:
RAW 2014: Random Number Generators on FPGAs. 15:1-15:21 - Osama G. Attia, Kevin R. Townsend, Phillip H. Jones, Joseph Zambreno:
A Reconfigurable Architecture for the Detection of Strongly Connected Components. 16:1-16:19
Volume 9, Number 3, July 2016
- Nachiket Kapre:
Optimizing Soft Vector Processing in FPGA-Based Embedded Systems. 17:1-17:17 - André DeHon, Derek Chiou:
Introduction to Special Issue on Reconfigurable Components with Source Code. 19:1-19:2 - Xin Fang, Miriam Leeser:
Open-Source Variable-Precision Floating-Point Library for Major Commercial FPGAs. 20:1-20:17 - David Wilson, Greg Stitt:
The Unified Accumulator Architecture: A Configurable, Portable, and Extensible Floating-Point Accumulator. 21:1-21:23 - Ameer M. S. Abdelhadi, Guy G. F. Lemieux:
Modular Switched Multiported SRAM-Based Memories. 22:1-22:26 - Greg Stitt, Eric Schwartz, Patrick Cooke:
A Parallel Sliding-Window Generator for High-Performance Digital-Signal Processing on FPGAs. 23:1-23:22
Volume 9, Number 4, September 2016
- Zain-ul-Abdin, Bertil Svensson:
A Retargetable Compilation Framework for Heterogeneous Reconfigurable Computing. 24:1-24:22 - Daniel Ziener, Florian Bauer, Andreas Becher, Christopher Dennl, Klaus Meyer-Wegener, Ute Schürfeld, Jürgen Teich, Jörg-Stephan Vogt, Helmut Weber:
FPGA-Based Dynamically Reconfigurable SQL Query Processing. 25:1-25:24 - Eric Matthews, Lesley Shannon, Alexandra Fedorova:
Shared Memory Multicore MicroBlaze System with SMP Linux Support. 26:1-26:22 - Ting Yu, Chris P. Bradley, Oliver Sinnen:
ODoST: Automatic Hardware Acceleration for Biomedical Model Integration. 27:1-27:24
- Deming Chen:
Introduction. 28:1-28:2 - Evan Wegley, Yanhua Yi, Qinhai Zhang:
Application of Specific Delay Window Routing for Timing Optimization in FPGA Designs. 29:1-29:22 - Edin Kadric, David Lakata, André DeHon:
Impact of Parallelism and Memory Architecture on FPGA Communication Energy. 30:1-30:23 - Alex Rodionov, David Biancolin, Jonathan Rose:
Fine-Grained Interconnect Synthesis. 31:1-31:22
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.
last updated on 2025-02-12 00:09 CET by the dblp team
all metadata released as open data under CC0 1.0 license
see also: Terms of Use | Privacy Policy | Imprint
dblp was originally created in 1993 at:
since 2018, dblp has been operated and maintained by:
the dblp computer science bibliography is funded and supported by:
