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ORCIDMiriam Leeser
Miriam E. Leeser
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- affiliation: Northeastern University, Boston, USA
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2020 – today
- 2024
[j51]Yiyue Jiang
, Andrius Vaicaitis, John Dooley, Miriam Leeser:
Efficient Neural Networks on the Edge with FPGAs by Optimizing an Adaptive Activation Function. Sensors 24(6): 1829 (2024)- [c119]Adarsh Salagame, Maria Gianello, Chenghao Wang, Kaushik Venkatesh Krishnamurthy, Shreyansh Pitroda, Rohit Rajput, Eric Sihite, Miriam Leeser, Alireza Ramezani:
Quadrupedal Locomotion Control On Inclined Surfaces Using Collocation Method. ACC 2024: 2838-2843 - [c118]Yiyue Jiang, Andrius Vaicaitis, John Dooley, Miriam Leeser:
Efficient Neural Networks on the Edge with FPGAs by Optimizing an Adaptive Activation Function. FPGA 2024: 184 - [c117]Sandeep Bal, Zhaoyang Han, Suranga Handagala, Mert Cevik, Michael Zink, Miriam Leeser:
P4-Based In-Network Telemetry for FPGAs in the Open Cloud Testbed and FABRIC. INFOCOM (Workshops) 2024: 1-6 - [i10]Xuan Shen, Zhenglun Kong, Changdi Yang, Zhaoyang Han, Lei Lu, Peiyan Dong, Cheng Lyu, Chih-hsiang Li, Xuehang Guo, Zhihao Shu, Wei Niu, Miriam Leeser, Pu Zhao, Yanzhi Wang:
EdgeQAT: Entropy and Distribution Guided Quantization-Aware Training for the Acceleration of Lightweight LLMs on the Edge. CoRR abs/2402.10787 (2024) - [i9]Zhaoyang Han, Andrew Briasco-Stewart, Michael Zink, Miriam Leeser:
Extracting TCPIP Headers at High Speed for the Anonymized Network Traffic Graph Challenge. CoRR abs/2409.07374 (2024) - 2023
- [j50]Miriam Leeser:
Artifact Evaluation for ACM TRETS Papers Submitted from the FPT Journal Track. ACM Trans. Reconfigurable Technol. Syst. 16(3): 40:1-40:2 (2023) - [c116]Yiyue Jiang, Andrius Vaicaitis, Miriam Leeser, John Dooley:
Neural Network on the Edge: Efficient and Low Cost FPGA Implementation of Digital Predistortion in MIMO Systems. DATE 2023: 1-2 - [c115]Dana Diaconu, Yanyue Xie, Mehmet Güngör, Suranga Handagala, Xue Lin, Miriam Leeser:
Machine Learning Across Network-Connected FPGAs. HPEC 2023: 1-7 - [c114]Kai Huang, Mehmet Güngör, Suranga Handagala, Stratis Ioannidis, Miriam Leeser:
Accelerating Garbled Circuits in the Open Cloud Testbed with Multiple Network-Attached FPGAs. HPEC 2023: 1-8 - [c113]Justin Kawakami, Dominik Zajac, Miriam Leeser:
Selective Encryption of Compressed Image Regions on the Edge with Reconfigurable Hardware. HPEC 2023: 1-6 - [c112]Zhaoyang Han, Suranga Handagala, Kalyani Patle, Michael Zink, Miriam Leeser:
A Framework to Enable Runtime Programmable P4-enabled FPGAs in the Open Cloud Testbed. INFOCOM Workshops 2023: 1-6 - [i8]Adarsh Salagame, Maria Gianello, Chenghao Wang, Kaushik Venkatesh Krishnamurthy, Shreyansh Pitroda, Rohit Rajput, Eric Sihite, Miriam Leeser, Alireza Ramezani:
Quadrupedal Locomotion Control On Inclined Surfaces Using Collocation Method. CoRR abs/2312.08621 (2023) - 2022
- [j49]Michaela Blott, Alina Vasilciuc, Miriam Leeser, Linda Doyle:
Evaluating Theoretical Baselines for ML Benchmarking Across Different Accelerators. IEEE Des. Test 39(3): 28-36 (2022) - [j48]Christophe Bobda, Joel Mandebi Mbongue, Paul Chow, Mohammad Ewais, Naif Tarafdar, Juan Camilo Vega, Ken Eguro, Dirk Koch, Suranga Handagala, Miriam Leeser, Martin C. Herbordt, Hafsah Shahzad, H. Peter Hofstee, Burkhard Ringlein, Jakub Szefer, Ahmed Sanaullah, Russell Tessier:
The Future of FPGA Acceleration in Datacenters and the Cloud. ACM Trans. Reconfigurable Technol. Syst. 15(3): 34:1-34:42 (2022) - [c111]Mengshu Sun, Zhengang Li, Alec Lu, Haoyu Ma, Geng Yuan, Yanyue Xie, Hao Tang, Yanyu Li, Miriam Leeser, Zhangyang Wang, Xue Lin, Zhenman Fang:
FPGA-aware automatic acceleration framework for vision transformer with mixed-scheme quantization: late breaking results. DAC 2022: 1394-1395 - [c110]Zhengang Li, Mengshu Sun, Alec Lu, Haoyu Ma, Geng Yuan, Yanyue Xie, Hao Tang, Yanyu Li, Miriam Leeser, Zhangyang Wang, Xue Lin, Zhenman Fang:
Auto-ViT-Acc: An FPGA-Aware Automatic Acceleration Framework for Vision Transformer with Mixed-Scheme Quantization. FPL 2022: 109-116 - [c109]Mehmet Güngör, Kai Huang, Stratis Ioannidis, Miriam Leeser:
Optimizing Designs Using Several Types of Memories on Modern FPGAs. HPEC 2022: 1-7 - [c108]Zhaoyang Han, Yiyue Jiang, Rahul Mushini, John Dooley, Miriam Leeser:
Hardware Software Codesign of Applications on the Edge: Accelerating Digital PreDistortion for Wireless Communications. HPEC 2022: 1-6 - [c107]Suranga Handagala, Miriam Leeser, Kalyani Patle, Michael Zink:
Network Attached FPGAs in the Open Cloud Testbed (OCT). INFOCOM Workshops 2022: 1-6 - [c106]Dana Diaconu, Lucian Petrica, Michaela Blott, Miriam Leeser:
Machine Learning Aided Hardware Resource Estimation for FPGA DNN Implementations. IPDPS Workshops 2022: 77-83 - [i7]Zhengang Li, Mengshu Sun, Alec Lu, Haoyu Ma, Geng Yuan, Yanyue Xie, Hao Tang, Yanyu Li, Miriam Leeser, Zhangyang Wang, Xue Lin, Zhenman Fang:
Auto-ViT-Acc: An FPGA-Aware Automatic Acceleration Framework for Vision Transformer with Mixed-Scheme Quantization. CoRR abs/2208.05163 (2022) - 2021
- [j47]Miriam Leeser, Suranga Handagala, Michael Zink, Volodymyr V. Kindratenko, Anne C. Elster:
FPGAs in the Cloud. Comput. Sci. Eng. 23(6): 72-76 (2021) - [j46]Michaela Blott, Nicholas J. Fraser, Giulio Gambardella, Lisa Halder, Johannes Kath, Zachary Neveu, Yaman Umuroglu, Alina Vasilciuc, Miriam Leeser, Linda Doyle:
Evaluation of Optimized CNNs on Heterogeneous Accelerators Using a Novel Benchmarking Approach. IEEE Trans. Computers 70(10): 1654-1669 (2021) - [c105]Michael Zink, David E. Irwin, Emmanuel Cecchet, Hakan Saplakoglu, Orran Krieger, Martin C. Herbordt, Michael Daitzman, Peter Desnoyers, Miriam Leeser, Suranga Handagala:
The Open Cloud Testbed (OCT): A Platform for Research into new Cloud Technologies. CloudNet 2021: 140-147 - [c104]Zhaoyang Han, Méabh Loughman, Yiyue Jiang, Rahul Mushini, Miriam Leeser, John Dooley:
Computationally Efficient Look-up-Tables for Behavioral Modelling and Digital Pre-distortion of Multi-standard Wireless Systems. CrownCom/WiCON 2021: 39-55 - [c103]Jieming Xu, Miriam Leeser:
Accelerating Matrix Processing for MIMO Systems. HEART 2021: 6:1-6:6 - 2020
- [j45]Suranga Handagala, Miriam Leeser:
Real Time Receiver Baseband Processing Platform for Sub 6 GHz PHY Layer Experiments. IEEE Access 8: 105571-105586 (2020) - [j44]Mahsa Bayati, Miriam Leeser, Jaydeep P. Bardhan:
High-performance transformation of protein structure representation from internal to Cartesian coordinates. J. Comput. Chem. 41(24): 2104-2114 (2020) - [j43]Prasidh Ramabadran, Pavel Afanasyev, David Malone, Miriam Leeser, Darragh McCarthy, Bill O'Brien, Ronan Farrell, John Dooley:
A Novel Physical Layer Authentication With PAPR Reduction Based on Channel and Hardware Frequency Responses. IEEE Trans. Circuits Syst. I Regul. Pap. 67-I(2): 526-539 (2020) - [j42]Mohamed Mohamed, Suranga Handagala, Jieming Xu, Miriam Leeser, Marvin Onabajo:
Strategies and Demonstration to Support Multiple Wireless Protocols with a Single RF Front-End. IEEE Wirel. Commun. 27(3): 88-95 (2020) - [c102]Suranga Handagala, Miriam Leeser:
Demonstrating Spectrally Efficient Asynchronous Coexistence for Machine Type Communication: A Software Defined Radio Approach. CrownCom 2020: 69-88 - [c101]Mengshu Sun, Pu Zhao, Mehmet Güngör, Massoud Pedram, Miriam Leeser, Xue Lin:
3D CNN Acceleration on FPGA using Hardware-Aware Pruning. DAC 2020: 1-6 - [c100]Michaela Blott, Johannes Kath, Lisa Halder, Yaman Umuroglu, Nicholas J. Fraser, Giulio Gambardella, Miriam Leeser, Linda Doyle:
Evaluation of Optimized CNNs on FPGA and non-FPGA based Accelerators using a Novel Benchmarking Approach. FPGA 2020: 317 - [c99]Mahsa Bayati, Miriam Leeser, Ningfang Mi:
Exploiting GPU Direct Access to Non-Volatile Memory to Accelerate Big Data Processing. HPEC 2020: 1-6 - [c98]Kai Huang, Mehmet Güngör, Stratis Ioannidis, Miriam Leeser:
Optimizing Use of Different Types of Memory for FPGAs in High Performance Computing. HPEC 2020: 1-7
2010 – 2019
- 2019
- [j41]Xin Fang, Stratis Ioannidis, Miriam Leeser:
SIFO: Secure Computational Infrastructure Using FPGA Overlays. Int. J. Reconfigurable Comput. 2019: 1439763:1-1439763:18 (2019) - [j40]Michaela Blott, Lisa Halder, Miriam Leeser, Linda Doyle:
QuTiBench: Benchmarking Neural Networks on Heterogeneous Hardware. ACM J. Emerg. Technol. Comput. Syst. 15(4): 37:1-37:38 (2019) - [j39]Mahsa Bayati, Miriam Leeser, Yijia Gu, Thomas Wahl:
Identifying volatile numeric expressions in numeric computing applications. Math. Comput. Simul. 166: 451-460 (2019) - [j38]Janki Bhimani, Ningfang Mi, Miriam Leeser, Zhengyu Yang:
New Performance Modeling Methods for Parallel Data Processing Applications. ACM Trans. Model. Comput. Simul. 29(3): 15:1-15:24 (2019) - [c97]Kai Huang, Mehmet Güngör, Xin Fang, Stratis Ioannidis, Miriam Leeser:
Garbled Circuits in the Cloud using FPGA Enabled Nodes. HPEC 2019: 1-6 - [c96]Miriam Leeser, Mehmet Güngör, Kai Huang, Stratis Ioannidis:
Accelerating Large Garbled Circuits on an FPGA-enabled Cloud. H2RC@SC 2019: 19-25 - [c95]Miriam Leeser, Suranga Handagala, Mohamed Mohamed, Jieming Xu, Marvin Onabajo:
An FPGA Design Technique to Receive Multiple Wireless Protocols with the Same RF Front End. Wireless Days 2019: 1-6 - [i6]Michaela Blott, Lisa Halder, Miriam Leeser, Linda Doyle:
QuTiBench: Benchmarking Neural Networks on Heterogeneous Hardware. CoRR abs/1909.05009 (2019) - [i5]Xin Fang, Stratis Ioannidis, Miriam Leeser:
SIFO: Secure Computational Infrastructure using FPGA Overlays. CoRR abs/1912.01710 (2019) - 2018
- [j37]Benjamin Drozdenko, Matthew Zimmermann, Tuan Dao, Kaushik R. Chowdhury, Miriam Leeser:
Hardware-Software Codesign of Wireless Transceivers on Zynq Heterogeneous Systems. IEEE Trans. Emerg. Top. Comput. 6(4): 566-578 (2018) - [j36]Michaela Blott, Thomas B. Preußer, Nicholas J. Fraser, Giulio Gambardella, Kenneth O'Brien, Yaman Umuroglu, Miriam Leeser, Kees A. Vissers:
FINN-R: An End-to-End Deep-Learning Framework for Fast Exploration of Quantized Neural Networks. ACM Trans. Reconfigurable Technol. Syst. 11(3): 16:1-16:23 (2018) - [c94]Jieming Xu, Miriam Leeser:
High-Level and Compact Design of Cross-Channel LTE DownLink Channel Encoder. CrownCom 2018: 15-24 - [c93]Suranga Handagala, Mohamed Mohamed, Jieming Xu, Marvin Onabajo, Miriam Leeser:
Detection of Different Wireless Protocols on an FPGA with the Same Analog/RF Front End. CrownCom 2018: 25-35 - [c92]Jieming Xu, Miriam Leeser:
Cross Component Optimization for Modern LTE Downlink Shared Channel Implementation. FCCM 2018: 225 - [c91]Declan Byrne, Ronan Farrell, Sidath Madhuwantha, Miriam Leeser, John Dooley:
Digital Pre-distortion Implemented Using FPGA. FPL 2018: 453-454 - [c90]Yanji Chen, Mehmet Güngör, Shweta Singh, Alex Tazin, Mieczyslaw M. Kokar, Miriam Leeser:
Dynamic Deployment of Communication Applications to Different Hardware Platforms using Ontological Representations. HPEC 2018: 1-6 - [c89]John Terragnoli, Miriam Leeser, Paul Monticciolo:
Stripmap SAR Pulse Interleaved Scheduling. HPEC 2018: 1-7 - [c88]Chao Liu, Miriam Leeser:
Local and Global Shared Memory for Task Based HPC Applications on Heterogeneous Platforms. PDP 2018: 316-320 - [i4]Michaela Blott, Thomas B. Preußer, Nicholas J. Fraser, Giulio Gambardella, Kenneth O'Brien, Yaman Umuroglu, Miriam Leeser:
Scaling Neural Network Performance through Customized Hardware Architectures on Reconfigurable Logic. CoRR abs/1807.03123 (2018) - 2017
- [c87]Janki Bhimani, Ningfang Mi, Miriam Leeser, Zhengyu Yang:
FIM: Performance Prediction for Parallel Computation in Iterative Data Processing Applications. CLOUD 2017: 359-366 - [c86]Xin Fang, Stratis Ioannidis, Miriam Leeser:
Secure Function Evaluation Using an FPGA Overlay Architecture. FPGA 2017: 257-266 - [c85]Benjamin Drozdenko, Suranga Handagala, Kaushik R. Chowdhury, Miriam Leeser:
FPGA modeling techniques for detecting and demodulating multiple wireless protocols. FPL 2017: 1-4 - [c84]Chao Liu, Janki Bhimani, Miriam Leeser:
Using High Level GPU Tasks to Explore Memory and Communications Options on Heterogeneous Platforms. SEM4HPC@HPDC 2017: 21-28 - [c83]Janki Bhimani, Zhengyu Yang, Miriam Leeser, Ningfang Mi:
Accelerating big data applications using lightweight virtualization framework on enterprise cloud. HPEC 2017: 1-7 - [c82]Michaela Blott, Thomas B. Preußer, Nicholas J. Fraser, Giulio Gambardella, Kenneth O'Brien, Yaman Umuroglu, Miriam Leeser:
Scaling Neural Network Performance through Customized Hardware Architectures on Reconfigurable Logic. ICCD 2017: 419-422 - [c81]Chao Liu, Miriam Leeser:
A Framework for Developing Parallel Applications with high level Tasks on Heterogeneous Platforms. PMAM@PPoPP 2017: 74-79 - 2016
- [j35]Ramanathan Subramanian, Benjamin Drozdenko, Eric Doyle, Rameez Ahmed, Miriam Leeser, Kaushik Roy Chowdhury:
High-Level System Design of IEEE 802.11b Standard-Compliant Link Layer for MATLAB-Based SDR. IEEE Access 4: 1494-1509 (2016) - [j34]Xin Fang, Miriam Leeser:
Open-Source Variable-Precision Floating-Point Library for Major Commercial FPGAs. ACM Trans. Reconfigurable Technol. Syst. 9(3): 20:1-20:17 (2016) - [c80]Ramanathan Subramanian, Eric Doyle, Benjamin Drozdenko, Miriam Leeser, Kaushik R. Chowdhury:
State-Action Based Link Layer Design for IEEE 802.11b Compliant MATLAB-Based SDR. DCOSS 2016: 193-198 - [c79]Benjamin Drozdenko, Matthew Zimmermann, Tuan Dao, Kaushik R. Chowdhury, Miriam Leeser:
Modeling considerations for the hardware-software co-design of flexible modern wireless transceivers. FPL 2016: 1-4 - [c78]Janki Bhimani, Miriam Leeser, Ningfang Mi:
Design space exploration of GPU Accelerated cluster systems for optimal data transfer using PCIe bus. HPEC 2016: 1-7 - [c77]Chao Liu, Miriam Leeser:
Unified and lightweight tasks and conduits: A high level parallel programming framework. HPEC 2016: 1-7 - [c76]Benjamin Drozdenko, Matthew Zimmermann, Tuan Dao, Miriam Leeser, Kaushik R. Chowdhury:
High-level hardware-software co-design of an 802.11a transceiver system using Zynq SoC. INFOCOM Workshops 2016: 682-683 - [c75]Janki Bhimani, Ningfang Mi, Miriam Leeser:
Performance prediction techniques for scalable large data processing in distributed MPI systems. IPCCC 2016: 1-2 - [c74]Majid Sabbagh, Martin Uecker, Andrew J. Powell, Miriam Leeser, Mehdi Hedjazi Moghari:
Cardiac MRI compressed sensing image reconstruction with a graphics processing unit. ISMICT 2016: 1-5 - [i3]Ramanathan Subramanian, Benjamin Drozdenko, Eric Doyle, Rameez Ahmed, Miriam Leeser, Kaushik R. Chowdhury:
High-Level System Design of IEEE 802.11b Standard-Compliant Link Layer for MATLAB-Based SDR. CoRR abs/1604.07881 (2016) - 2015
- [j33]Nicholas Moore, Miriam Leeser, Laurie A. Smith King:
Kernel Specialization Provides Adaptable GPU Code for Particle Image Velocimetry. IEEE Trans. Parallel Distributed Syst. 26(4): 1049-1058 (2015) - [c73]Xin Fang, Pei Luo, Yunsi Fei, Miriam Leeser:
Balance power leakage to fight against side-channel analysis at gate level in FPGAs. ASAP 2015: 154-155 - [c72]Benjamin Drozdenko, Ramanathan Subramanian, Kaushik R. Chowdhury, Miriam Leeser:
Implementing a MATLAB-Based Self-configurable Software Defined Radio Transceiver. CrownCom 2015: 164-175 - [c71]Yijia Gu, Thomas Wahl, Mahsa Bayati, Miriam Leeser:
Behavioral Non-portability in Scientific Numeric Computing. Euro-Par 2015: 558-569 - [c70]Mahsa Bayati, Jaydeep P. Bardhan, Miriam Leeser:
GPU implementation of reverse coordinate conversion for proteins. HPEC 2015: 1-6 - [c69]Janki Bhimani, Miriam Leeser, Ningfang Mi:
Accelerating K-Means clustering with parallel implementations and GPU computing. HPEC 2015: 1-6 - [c68]Xin Fang, Pei Luo, Yunsi Fei, Miriam Leeser:
Leakage evaluation on power balance countermeasure against side-channel attack on FPGAs. HPEC 2015: 1-6 - [c67]Pei Luo, Yunsi Fei, Xin Fang, A. Adam Ding, David R. Kaeli, Miriam Leeser:
Side-channel analysis of MAC-Keccak hardware implementations. HASP@ISCA 2015: 1:1-1:8 - [i2]Pei Luo, Yunsi Fei, Xin Fang, A. Adam Ding, David R. Kaeli, Miriam Leeser:
Side-Channel Analysis of MAC-Keccak Hardware Implementations. IACR Cryptol. ePrint Arch. 2015: 411 (2015) - 2014
- [c66]Miriam Leeser, Saoni Mukherjee, Jaideep Ramachandran, Thomas Wahl:
Make it real: Effective floating-point reasoning via exact arithmetic. DATE 2014: 1-4 - [c65]Jonathon Pendlum, Miriam Leeser, Kaushik R. Chowdhury:
Reducing Processing Latency with a Heterogeneous FPGA-Processor Framework. FCCM 2014: 17-20 - [c64]Mahsa Bayati, Jaydeep P. Bardhan, David M. King, Miriam Leeser:
Accelerating protein coordinate conversion using GPUs. HPEC 2014: 1-6 - [c63]Pei Luo, Yunsi Fei, Xin Fang, A. Adam Ding, Miriam Leeser, David R. Kaeli:
Power analysis attack on hardware implementation of MAC-Keccak on FPGAs. ReConFig 2014: 1-7 - [p1]Miriam Leeser, James Brock:
Digital Logic. Computing Handbook, 3rd ed. (1) 2014: 17: 1-39 - [i1]Pei Luo, Yunsi Fei, Xin Fang, A. Adam Ding, Miriam Leeser, David R. Kaeli:
Power Analysis Attack on Hardware Implementation of MAC-Keccak on FPGAs. IACR Cryptol. ePrint Arch. 2014: 854 (2014) - 2013
- [c62]Peter Grossmann, Miriam Leeser, Marvin Onabajo:
Minimum energy operation for clustered island-style FPGAs. FPGA 2013: 157-166 - [c61]Xin Fang, Miriam Leeser:
Vendor agnostic, high performance, double precision Floating Point division for FPGAs. HPEC 2013: 1-5 - [c60]David A. Kusinsky, Miriam Leeser:
FPGA-based hyperspectral covariance coprocessor for size, weight, and power constrained platforms. HPEC 2013: 1-6 - [c59]Nicholas Moore, Miriam Leeser, Laurie A. Smith King:
Kernel Specialization for Improved Adaptability and Performance on Graphics Processing Units (GPUs). IPDPS 2013: 1037-1048 - 2012
- [j32]Nicholas Moore, Miriam Leeser, Laurie A. Smith King:
VForce: An environment for portable applications on high performance systems with accelerators. J. Parallel Distributed Comput. 72(9): 1144-1156 (2012) - [j31]Peter Grossmann, Miriam Leeser, Marvin Onabajo:
Minimum Energy Analysis and Experimental Verification of a Latch-Based Subthreshold FPGA. IEEE Trans. Circuits Syst. II Express Briefs 59-II(12): 942-946 (2012) - [c58]George Eichinger, Kaushik R. Chowdhury, Miriam Leeser:
Cognitive radio universal software hardware. DySPAN 2012: 270-271 - [c57]George Eichinger, Kaushik R. Chowdhury, Miriam Leeser:
Cognitive Radio Universal Software Hardware. FCCM 2012: 240 - [c56]Mary Ellen Tie, Miriam Leeser:
Implementing Murf: Accelerating Large State Space Exploration on FPGAs. FCCM 2012: 243 - [c55]Scott Bailie, Miriam Leeser:
Incremental clustering applied to radar deinterleaving: a parameterized FPGA implementation. FPGA 2012: 25-28 - [c54]George Eichinger, Kaushik R. Chowdhury, Miriam Leeser:
CRUSH: Cognitive Radio Universal Software Hardware. FPL 2012: 26-32 - [c53]Saoni Mukherjee, Nicholas Moore, James Brock, Miriam Leeser:
CUDA and OpenCL implementations of 3D CT reconstruction for biomedical imaging. HPEC 2012: 1-6 - 2011
- [j30]Miriam Leeser, Devon Yablonski, Dana H. Brooks, Laurie A. Smith King:
The challenges of writing portable, correct and high performance libraries for GPUs. SIGARCH Comput. Archit. News 39(4): 2-7 (2011) - [c52]Jainik Kathiara, Miriam Leeser:
An Autonomous Vector/Scalar Floating Point Coprocessor for FPGAs. FCCM 2011: 33-36 - [c51]Peter Grossmann, Miriam Leeser:
A prototype FPGA for subthreshold-optimized CMOS (abstract only). FPGA 2011: 279 - 2010
- [j29]Xiaojun Wang, Miriam Leeser:
VFloat: A Variable Precision Fixed- and Floating-Point Library for Reconfigurable Hardware. ACM Trans. Reconfigurable Technol. Syst. 3(3): 16:1-16:34 (2010) - [c50]Nicholas Moore, Miriam Leeser, Laurie A. Smith King:
Efficient template matching with variable size templates in CUDA. SASP 2010: 77-80 - [e3]David R. Kaeli, Miriam Leeser:
Proceedings of 3rd Workshop on General Purpose Processing on Graphics Processing Units, GPGPU 2010, Pittsburgh, Pennsylvania, USA, March 14, 2010. ACM International Conference Proceeding Series 425, ACM 2010, ISBN 978-1-60558-935-0 [contents]
2000 – 2009
- 2009
- [j28]Ben Cordes, Miriam Leeser:
Parallel Backprojection: A Case Study in High-Performance Reconfigurable Computing. EURASIP J. Embed. Syst. 2009 (2009) - [j27]Vinay Sriram, Miriam Leeser:
FPGA Supercomputing Platforms, Architectures, and Techniques for Accelerating Computationally Complex Algorithms. EURASIP J. Embed. Syst. 2009 (2009) - [j26]Xiaojun Wang, Miriam Leeser:
A truly two-dimensional systolic array FPGA implementation of QR decomposition. ACM Trans. Embed. Comput. Syst. 9(1): 3:1-3:17 (2009) - [c49]Abderrahmane Bennis, Miriam Leeser, Gilead Tadmor:
Implementing a Highly Parameterized Digital PIV System on Reconfigurable Hardware. ASAP 2009: 32-37 - [c48]Perhaad Mistry, Sherman Braganza, David R. Kaeli, Miriam Leeser:
Accelerating phase unwrapping and affine transformations for optical quadrature microscopy using CUDA. GPGPU 2009: 28-37 - [c47]Abderrahmane Bennis, Miriam Leeser, Gilead Tadmor:
The Effect of Parameterization on a Reconfigurable Implementation of PIV. ERSA 2009: 105-111 - [e2]David R. Kaeli, Miriam Leeser:
Proceedings of 2nd Workshop on General Purpose Processing on Graphics Processing Units, GPGPU 2009, Washington, DC, USA, March 8, 2009. ACM International Conference Proceeding Series 383, ACM 2009, ISBN 978-1-60558-517-8 [contents] - 2008
- [j25]David R. Kaeli, Miriam Leeser:
Special issue: General-purpose processing using graphics processing units. J. Parallel Distributed Comput. 68(10): 1305-1306 (2008) - [j24]David R. Kaeli, Miriam Leeser:
Acknowledgment to special issue reviewers. J. Parallel Distributed Comput. 68(10): 1402 (2008) - [j23]Joshua Noseworthy, Miriam Leeser:
Efficient Communication Between the Embedded Processor and the Reconfigurable Logic on an FPGA. IEEE Trans. Very Large Scale Integr. Syst. 16(8): 1083-1090 (2008) - [c46]Sherman Braganza, Miriam Leeser:
An efficient implementation of a phase unwrapping kernel on reconfigurable hardware. ASAP 2008: 138-143 - [c45]Mary Ellen Fuess, Miriam Leeser, Tim Leonard:
An FPGA Implementation of Explicit-State Model Checking. FCCM 2008: 119-126 - [c44]Sherman Braganza, Miriam Leeser:
An Efficient Implementation of a Phase Unwrapping Kernel on Reconfigurable Hardware. FCCM 2008: 316-317 - [c43]Xiaojun Wang, Miriam Leeser:
Efficient FPGA implementation of qr decomposition using a systolic array architecture. FPGA 2008: 260 - [c42]Sherman Braganza, Miriam Leeser:
Implementing phase unwrapping using Field Programmable Gate Arrays or Graphics Processing Units: A comparison. HPRCTA@SC 2008: 1-10 - 2007
- [j22]Nicholas Moore, Albert Conti, Miriam Leeser, Laurie A. Smith King:
Vforce: An Extensible Framework for Reconfigurable Supercomputing. Computer 40(3): 39-49 (2007) - [j21]Heather Quinn, Miriam Leeser, Laurie A. Smith King:
Dynamo: a runtime partitioning system for FPGA-based HW/SW image processing systems. J. Real Time Image Process. 2(4): 179-190 (2007) - [c41]Sherman Braganza, Miriam Leeser:
The 1D Discrete Cosine Transform For Large Point Sizes Implemented On Reconfigurable Hardware. ASAP 2007: 101-106 - [c40]Xiaojun Wang, Miriam Leeser:
K-means Clustering for Multispectral Images Using Floating-Point Divide. FCCM 2007: 151-162 - [c39]Nicholas Moore, Albert Conti, Miriam Leeser, Laurie A. Smith King:
Writing Portable Applications that Dynamically Bind at Run Time to Reconfigurable Hardware. FCCM 2007: 229-238 - 2006
- [j20]Miriam Leeser, Scott Hauck, Russell Tessier:
Field-Programmable Gate Arrays in Embedded Systems. EURASIP J. Embed. Syst. 2006 (2006) - [j19]Haiqian Yu, Miriam Leeser, Gilead Tadmor, Stefan Siegel:
Real-Time Particle Image Velocimetry for Feedback Loops Using FPGA Implementation. J. Aerosp. Comput. Inf. Commun. 3(2): 52-62 (2006) - [j18]Peter Soderquist, Miriam Leeser, Juan Carlos Rojas:
Enabling MPEG-2 video playback in embedded systems through improved data cache efficiency. IEEE Trans. Multim. 8(1): 81-89 (2006) - [c38]Joshua Noseworthy, Miriam Leeser:
Efficient Use of Communications Between an FPGAs Embedded Processor and its Reconfigurable Logic. ERSA 2006: 191-197 - [c37]Haiqian Yu, Miriam Leeser:
Automatic Sliding Window Operation Optimization for FPGA-Based. FCCM 2006: 76-88 - [c36]Xiaojun Wang, Sherman Braganza, Miriam Leeser:
Advanced Components in the Variable Precision Floating-Point Library. FCCM 2006: 249-258 - [c35]Joshua Noseworthy, Miriam Leeser:
Efficient use of communications between an FPGA's embedded processor and its reconfigurable logic. FPGA 2006: 233 - [c34]Ben Cordes, Miriam Leeser, Eric L. Miller, Richard W. Linderman:
Poster reception - Improving the performance of parallel backprojection on a reconfigurable supercomputer. SC 2006: 149 - 2005
- [j17]Miriam Leeser, Srdjan Coric, Eric L. Miller, Haiqian Yu, Marc Trepanier:
Parallel-Beam Backprojection: An FPGA Implementation Optimized for Medical Imaging. J. VLSI Signal Process. 39(3): 295-311 (2005) - [c33]Ben Cordes, Jennifer G. Dy, Miriam Leeser, James Goebel:
Enabling a RealTime Solution for Neuron Detection with Reconfigurable Hardware (abstract only). FPGA 2005: 264 - [c32]Ben Cordes, Jennifer G. Dy, Miriam Leeser, James Goebel:
Enabling a Real-Time Solution for Neuron Detection with Reconfigurable Hardware. IEEE International Workshop on Rapid System Prototyping 2005: 128-134 - 2004
- [c31]Laurie A. Smith King, Miriam Leeser, Heather Quinn:
Dynamo: A Runtime Partitioning System. ERSA 2004: 145-154 - [c30]Miriam Leeser, Shawn Miller, Haiqian Yu:
Smart Camera Based on Reconfigurable Hardware Enables Diverse Real-Time Applications. FCCM 2004: 147-155 - [c29]Wang Chen, Panos Kosmas, Miriam Leeser, Carey M. Rappaport:
An FPGA implementation of the two-dimensional finite-difference time-domain (FDTD) algorithm. FPGA 2004: 213-222 - 2003
- [c28]Zhihong Zhao, Miriam Leeser:
Precision Modeling of Floating-Point Applications for Variable Bitwidth Computing. Engineering of Reconfigurable Systems and Algorithms 2003: 208-214 - [c27]Heather Quinn, Laurie A. Smith King, Miriam Leeser, Waleed Meleis:
Runtime Assignment of Reconfigurable Hardware Components for Image Processing Pipelines. FCCM 2003: 173- - [c26]Juan Carlos Rojas, Miriam Leeser:
Programming portable optimized multimedia applications. ACM Multimedia 2003: 291-294 - 2002
- [c25]Srdjan Coric, Miriam Leeser, Eric L. Miller, Marc Trepanier:
Parallel-beam backprojection: an FPGA implementation optimized for medical imaging. FPGA 2002: 217-226 - [c24]Pavle Belanovic, Miriam Leeser:
A Library of Parameterized Floating-Point Modules and Their Use. FPL 2002: 657-666 - 2001
- [j16]Silviu M. S. A. Chiricescu, Miriam Leeser, Mankuan Michael Vai:
Design and analysis of a dynamically reconfigurable three-dimensional FPGA. IEEE Trans. Very Large Scale Integr. Syst. 9(1): 186-196 (2001) - [j15]Miriam E. Leeser, Valerie Ohm:
Accurate Power Estimation for Sequential CMOS Circuits Using Graph-based Methods. VLSI Design 12(2): 187-203 (2001) - [c23]Mike Estlick, Miriam Leeser, James Theiler, John J. Szymanski:
Algorithmic transformations in the implementation of K- means clustering on reconfigurable hardware. FPGA 2001: 103-110 - [c22]Laurie A. Smith King, Heather Quinn, Miriam Leeser, Demetris G. Galatopoullos, Elias S. Manolakos:
Run-Time Execution of Reconfigurable Hardware in a Java Environment. ICCD 2001: 380-387 - 2000
- [j14]Shantanu Tarafdar, Miriam Leeser:
A data-centric approach to high-level synthesis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 19(11): 1251-1267 (2000) - [j13]Yanbing Li, Miriam Leeser:
HML, a novel hardware description language and its translation to VHDL. IEEE Trans. Very Large Scale Integr. Syst. 8(1): 1-8 (2000) - [c21]Ali M. Shankiti, Miriam Leeser:
Implementing a RAKE receiver for wireless communications on an FPGA-based computer system. FPGA 2000: 145-151
1990 – 1999
- 1998
- [j12]Miriam Leeser, Waleed Meleis, Mankuan Michael Vai, Silviu M. S. A. Chiricescu, Weidong Xu, Paul M. Zavracky:
Rothko: A Three-Dimensional FPGA. IEEE Des. Test Comput. 15(1): 16-23 (1998) - [c20]Shantanu Tarafdar, Miriam Leeser:
The DT-Model: High-Level Synthesis Using Data Transfers. DAC 1998: 114-117 - [c19]Goran Doncev, Miriam Leeser, Shantanu Tarafdar:
High Level Synthesis for Designing Custom Computing Hardware. FCCM 1998: 326-328 - [c18]Shantanu Tarafdar, Miriam Leeser, Zixin Yin:
Integrating floorplanning in data-transfer based high-level synthesis. ICCAD 1998: 412-417 - [c17]Goran Doncev, Miriam Leeser, Shantanu Tarafdar:
Truly Rapid Prototyping Requires High-Level Synthesis. International Workshop on Rapid System Prototyping 1998: 101- - 1997
- [j11]Peter Soderquist, Miriam Leeser:
Division and square root: choosing the right implementation. IEEE Micro 17(4): 56-66 (1997) - [c16]Waleed Meleis, Miriam Leeser, Paul M. Zavracky, Mankuan Michael Vai:
Architectural Design of a Three Dimensional FPGA. ARVLSI 1997: 256-269 - [c15]Miriam Leeser, Waleed Meleis, Mankuan Michael Vai, Paul M. Zavracky:
Rothko: A three dimensional FPGA architecture, its fabrication, and design tools. FPL 1997: 21-30 - [c14]Peter Soderquist, Miriam Leeser:
Memory Traffic and Data Cache Behavior of an MPEG-2 Software Decoder. ICCD 1997: 417-422 - [c13]Peter Soderquist, Miriam Leeser:
Optimizing the Data Cache Performance of a Software MPEG-2 Video Decoder. ACM Multimedia 1997: 291-301 - 1996
- [j10]Peter Soderquist, Miriam Leeser:
Area and Performance Tradeoffs in Floating-Point Divide and Square-Root Implementations. ACM Comput. Surv. 28(3): 518-564 (1996) - 1995
- [j9]Andrés Takach, Wayne H. Wolf, Miriam Leeser:
An Automaton Model for Scheduling Constraints in Synchronous Machines. IEEE Trans. Computers 44(1): 1-12 (1995) - [j8]Mark D. Aagaard, Miriam Leeser:
Verifying a Logic-Synthesis Algorithm and Implementation: A Case Study in Software Verification. IEEE Trans. Software Eng. 21(10): 822-833 (1995) - [c12]Peter Soderquist, Miriam Leeser:
An Area/Performance Comparison of Subtractive and Multiplicative Divide/Square Root Implementations. IEEE Symposium on Computer Arithmetic 1995: 132-139 - [c11]Miriam Leeser, John W. O'Leary:
Verification of a subtractive radix-2 square root algorithm and implementation. ICCD 1995: 526-531 - 1994
- [j7]Mark D. Aagaard, Miriam Leeser:
A Methodology for Efficient Hardware Verification. Formal Methods Syst. Des. 5(1/2): 95-117 (1994) - [j6]Mark D. Aagaard, Miriam Leeser:
PBS: proven Boolean simplification. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 13(4): 459-470 (1994) - [c10]Mark H. Linderman, Miriam Leeser:
Simulation of digital circuits in the presence of uncertainty. ICCAD 1994: 248-251 - [c9]Mark D. Aagaard, Miriam Leeser:
Reasoning About Pipelines with Structural Hazards. TPCD 1994: 13-32 - [c8]John W. O'Leary, Miriam Leeser, Jason Hickey, Mark D. Aagaard:
Non-Restoring Integer Square Root: A Case Study in Design by Principled Optimization. TPCD 1994: 52-71 - 1993
- [j5]Miriam Leeser, Richard Chapman, Mark D. Aagaard, Mark H. Linderman, Stephan Meier:
High level synthesis and generating FPGAs with the BEDROC system. J. VLSI Signal Process. 6(2): 191-214 (1993) - [j4]Miriam Leeser:
High level synthesis and generation FPGAs with the BEDROC system. J. VLSI Signal Process. 6(3): 7 (1993) - [c7]John W. O'Leary, Mark H. Linderman, Miriam Leeser, Mark D. Aagaard:
HML: A Hardware Description Language Based on Standard ML. CHDL 1993: 327-334 - [c6]Mark D. Aagaard, Miriam Leeser:
A Framework for Specifying and Designing Pipelines. ICCD 1993: 548-551 - [c5]Mark D. Aagaard, Miriam Leeser, Phillip J. Windley:
Toward a Super Duper Hardware Tactic. HUG 1993: 399-412 - 1992
- [c4]Mark D. Aagaard, Miriam Leeser:
Verifying a Logic Synthesis Tool in Nuprl: A Case Study in Software Verification. CAV 1992: 69-81 - [c3]Mark D. Aagaard, Miriam Leeser:
A Methodology for Reusable Hardware Proofs. TPHOLs 1992: 177-196 - 1991
- [j3]David A. Basin, Geoffrey M. Brown, Miriam Leeser:
Formally verified synthesis of combinational CMOS circuits. Integr. 11(3): 235-250 (1991) - [c2]Mark D. Aagaard, Miriam Leeser:
A Formally Verified System for Logic Synthesis. ICCD 1991: 346-350 - 1990
- [e1]Miriam Leeser, Geoffrey Brown:
Hardware Specification, Verification and Synthesis: Mathematical Aspects, Mathematical Science Institute Workshop, Cornall University, Ithaca, New York, USA, July 5-7, 1989, Proceedings. Lecture Notes in Computer Science 408, Springer 1990, ISBN 3-540-97226-9 [contents]
1980 – 1989
- 1989
- [j2]Miriam Leeser:
Reasoning about the function and timing of integrated circuits with interval temporal logic. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 8(12): 1233-1246 (1989) - [c1]Geoffrey M. Brown, Miriam Leeser:
From Programs to Transistors: Verifying Hardware Synthesis Tools. Hardware Specification, Verification and Synthesis 1989: 129-151 - 1987
- [b1]Miriam Leeser:
Reasoning about the function and timing of integrated circuits with Prolog and temporal logic. University of Cambridge, UK, 1987 - 1986
- [j1]William F. Clocksin, Miriam Leeser:
Automatic determination of signal flow through MOS transistor networks. Integr. 4(1): 53-63 (1986)
Coauthor Index
Kaushik R. Chowdhury
aka: Kaushik Roy Chowdhury
aka: Kaushik Roy Chowdhury
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